Patents Examined by William M. Treat
  • Patent number: 8250346
    Abstract: A processor 2 supporting register renaming has a rename table 20 in which the flag register has multiple tag values associated therewith. These tag values indicate which virtual register corresponds to a destination flag register of the oldest instruction which wrote a still up-to-date value of a subset of the flags.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: August 21, 2012
    Assignee: ARM Limited
    Inventor: James Nolan Hardage
  • Patent number: 8250339
    Abstract: The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 21, 2012
    Assignee: QST Holdings LLC
    Inventors: Paul L. Master, Stephen J. Smith, John Watson
  • Patent number: 8245014
    Abstract: The present invention provides a network multithreaded processor, such as a network processor, including a thread interleaver that implements fine-grained thread decisions to avoid underutilization of instruction execution resources in spite of large communication latencies. In an upper pipeline, an instruction unit determines an-instruction fetch sequence responsive to an instruction queue depth on a per thread basis. In a lower pipeline, a thread interleaver determines a thread interleave sequence responsive to thread conditions including thread latency conditions. The thread interleaver selects threads using a two-level round robin arbitration. Thread latency signals are active responsive to thread latencies such as thread stalls, cache misses, and interlocks. During the subsequent one or more clock cycles, the thread is ineligible for arbitration. In one embodiment, other thread conditions affect selection decisions such as local priority, global stalls, and late stalls.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: August 14, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Donald E Steiss, Earl T Cohen, John J Williams
  • Patent number: 8209518
    Abstract: A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The bits are selectively cleared in the bypass directory each cycle. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: June 26, 2012
    Inventors: Alexander Klaiber, Guillermo Rozas
  • Patent number: 8190859
    Abstract: A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: May 29, 2012
    Assignee: Intel Corporation
    Inventors: Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan
  • Patent number: 8190669
    Abstract: Multipurpose arithmetic functional units can perform planar attribute interpolation and unary function approximation operations. In one embodiment, planar interpolation operations for coordinates (x, y) are executed by computing A*x+B*y+C, and unary function approximation operations for operand x are executed by computing F2(xb)*xh2+F1(xb)*xh+F0(xb), where xh=x?xb. Shared multiplier and adder circuits are advantageously used to implement the product and sum operations for both classes of operations.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: May 29, 2012
    Assignee: NVIDIA Corporation
    Inventors: Stuart F. Oberman, Ming Y. Siu
  • Patent number: 8190856
    Abstract: A processor of SIMD/MIMD dual mode architecture comprises common controlled first processing elements, self-controlled second processing elements and a pipelined (ring) network connecting the first PEs and the second PEs sequentially. An access controller has access control lines, each access control line being connected to each PE of the first and second PEs to control data access timing between each PE and the network. Each PE can be self-controlled or common controlled, such as dual mode SIMD/MIMD architectures, reducing the wiring area requirement.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: May 29, 2012
    Assignee: NEC Corporation
    Inventors: Hanno Lieske, Shorin Kyo
  • Patent number: 8169439
    Abstract: Embodiments of the invention are generally related to image processing, and more specifically to vector units for supporting image processing. A combined vector/scalar unit is provided wherein one or more processing lanes of the vector unit are used for performing scalar operations. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is obviated and a significant amount of chip area is saved.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: May 1, 2012
    Assignee: International Business Machines Corporation
    Inventors: David Arnold Luick, Eric Oliver Mejdrich, Adam James Muff
  • Patent number: 8151098
    Abstract: A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: April 3, 2012
    Assignee: DENSO CORPORATION
    Inventors: Akimasa Niwa, Masahiro Kamiya, Hideaki Ishihara, Yoshinori Teshima
  • Patent number: 8145879
    Abstract: In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: March 27, 2012
    Assignee: XMTT Inc.
    Inventor: Uzi Y. Vishkin
  • Patent number: 8145822
    Abstract: One aspect relates to a computer system including a first data processing unit, a second data processing unit and a data transmission/memory device. The data transmission/memory can transmit sets of data from the first data processing unit to the second data processing unit. The data transmission/memory device includes a first memory region and a second memory region.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: March 27, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Hachmann, Christian Sauer
  • Patent number: 8145890
    Abstract: A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor. The non-user program includes a conditional branch instruction. A first fetch unit fetches instructions of the user program that includes the instruction that is implemented by the non-user program. An instruction decoder decodes the user program instructions and saves a state in response to decoding the user program instruction that is implemented by the non-user program. An execution unit executes the user program instructions fetched by the first fetch unit and executes instructions of the non-user program other than the conditional branch instruction. A second fetch unit fetches the non-user program instructions from the memory and resolves the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: March 27, 2012
    Assignee: VIA Technologies, Inc.
    Inventors: G. Glenn Henry, Terry Parks, Brent Bean
  • Patent number: 8145888
    Abstract: A data processing circuit has an execution circuit (18) with a plurality of functional units (20). An instruction decoder (17) is operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of the functional units (20), and in the second instruction mode instructions control one functional unit. A mode control circuit (12) controls the selection of the instruction modes. In an embodiment, the instruction decoder uses time-stationary decoding of the selection of operations to be executed by the execution circuit (18) and the selection of destination registers from the set of registers (19). Mode switching is a more efficient way of reducing instruction time for time stationary processors than indicating functional units for which the instruction contains commands.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: March 27, 2012
    Assignee: Silicon Hive B.V.
    Inventors: Jeroen Anton Johan Leijten, Hendrik Tjeerd Joannes Zwartenkot
  • Patent number: 8145881
    Abstract: A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: March 27, 2012
    Inventors: Martin Vorbach, Alexander Thomas
  • Patent number: 8138788
    Abstract: There is provided a reconfigurable device that includes a plurality of processing blocks (13), wherein operation logic of each processing block is changeable, and a routing matrix (15) for configuring paths that connect the plurality of the processing blocks. Each processing block (13) includes a logic operation unit (21) whose logic is determined by configuration data (17) and a storage unit (40) for storing processing results of the logic operation unit. Each storage unit (40) includes a plurality of storage elements (31r), input means (32) for selecting one of the plurality of storage elements (31r) based on the configuration data (17) to store the output of the logic operation unit (21), and output means (33) for connecting the plurality of storage elements (31r) to the routing matrix (15).
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: March 20, 2012
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Hiroki Honda
  • Patent number: 8131984
    Abstract: A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, and a serializing instruction that updates the control value in the control register. The microprocessor completes all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction. Execution units update the control value in the control register in response to the serializing instruction. A fetch unit fetches, decodes, and unconditionally correctly resolves and retires the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: March 6, 2012
    Assignee: VIA Technologies, Inc.
    Inventors: G. Glenn Henry, Terry Parks, Brent Bean
  • Patent number: 8108653
    Abstract: A processor includes a compute array comprising a first plurality of compute engines serially connected along a data flow path such that data flows between successive compute engines at successive times. The first plurality of compute engines includes an initial compute engine and a final compute engine. The data flow path includes a recirculation path connecting the final compute engine to the initial compute engine with no compute engine therebetween.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: January 31, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Boris Lerner, Douglas Garde
  • Patent number: 8106679
    Abstract: The present invention provides an architecture code 20 including object circuit information 23 for mapping an object circuit that is at least part of a circuit for executing an application onto part of a logic circuit where circuits can be dynamically reconfigured, interface circuit information 24 for mapping an interface circuit in contact with the object circuit onto the logic circuit, and boundary condition 26 to be realized in the interface circuit. A data processing system in the present invention includes a load unit obtaining an architecture code 20, a mapping unit for mapping the object circuit and the interface circuit in contact with the object circuit onto the logic circuit region according to the object circuit information 23 and the interface circuit information 24 of the architecture code, and a behavior control unit for controlling the interface circuit according to the boundary condition 26 of the architecture code.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: January 31, 2012
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Tomoyoshi Sato
  • Patent number: 8108658
    Abstract: A data processing circuit comprises a register file (14) having read ports and write ports. A plurality of functional units (21a-c), is coupled to receive operand data from a same combination of read ports. Each functional unit is coupled to a respective one of the write ports for writing a respective result. An instruction issue slot has outputs (11) for supplying register selection information to said combination read ports and to the respective ones of the write ports. The output of the issue slot also supplies an operation code. The functional units (21a-c) in the plurality are arranged to respond to at least to one value of the operation code by each executing a respective operation using the same operands from said same combination and each functional unit producing a respective result at a respective ones of the write ports.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: January 31, 2012
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Antonius Adrianus Maria Van Wel
  • Patent number: 8082420
    Abstract: A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructions in a second thread. The method further includes forming a common issue group including an instruction of a first instruction type and an instruction of a second instruction type. The method also includes issuing the common issue group to a first execution unit and a second execution unit. The instruction of the first instruction type is issued to the first execution unit and the instruction of the second instruction type is issued to the second execution unit.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Miguel Comparan, Brent Francis Hilgart, Brian Lee Koehler, Eric Oliver Mejdrich, Adam James Muff, Alfred Thomas Watson, III