Patents Assigned to Advanced Micro Devices, Inc.
  • Publication number: 20240087667
    Abstract: Error correction for stacked memory is described. In accordance with the described techniques, a system includes a plurality of error correction code engines to detect vulnerabilities in a stacked memory and coordinate at least one vulnerability detected for a portion of the stacked memory to at least one other portion of the stacked memory.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Divya Madapusi Srinivas Prasad, Michael Ignatowski, Gabriel Loh
  • Publication number: 20240087636
    Abstract: Dynamic memory operations are described. In accordance with the described techniques, a system includes a stacked memory and one or more memory monitors configured to monitor conditions of the stacked memory. A system manager is configured to receive the monitored conditions of the stacked memory from the one or more memory monitors, and dynamically adjust operation of the stacked memory based on the monitored conditions. In one or more implementations, a system includes a memory and at least one register configured to store a ranking for each of a plurality of portions of the memory. Each respective ranking is determined based on an associated retention time of the respective portion of the memory. A memory controller is configured to dynamically refresh the portions of the memory at different times based on the ranking for each of the plurality of portions of the memory stored in the at least one register.
    Type: Application
    Filed: June 12, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Divya Madapusi Srinivas Prasad, Michael Ignatowski
  • Publication number: 20240087632
    Abstract: A memory device includes memory cells. A memory cell of the memory cells includes gate circuitry, a first capacitor, and a second capacitor. The gate circuitry is connected to a wordline and a bitline. The first capacitor is connected to the gate circuitry and a first drive line. The second capacitor is connected to the gate circuitry and a second drive line.
    Type: Application
    Filed: June 29, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Divya Madapusi Srinivas PRASAD, Michael IGNATOWSKI, Niti MADAN
  • Publication number: 20240087078
    Abstract: Methods, devices, and systems for rendering primitives in a frame. During a visibility pass, state packets are processed to determine a register state, and the register state is stored in a memory device. During a rendering pass, the state packets are discarded and the register state is read from the memory device. In some implementations, a graphics pipeline is configured during the visibility pass based on the register state determined by processing the state packets, and the graphics pipeline is configured during the rendering pass based on the register state read from the memory device. In some implementations, replay control packets, draw packets, and the state packets, from a packet stream, are processed during the visibility pass; the draw packets are modified based on visibility information determined during the visibility pass; and the replay control packets and draw packets are processed, during the rendering pass.
    Type: Application
    Filed: June 19, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander Fuad Ashkar, Vishrut Vaibhav, Manu Rastogi, Harry J. Wise
  • Publication number: 20240087223
    Abstract: A method and a processing device for performing rendering are disclosed. The method comprises generating a base hierarchy tree comprising data representing a first object and generating a second hierarchy tree representing a second object comprising shared data of the base hierarchy tree and the second hierarchy tree and difference data. The method further comprises storing the difference data in the memory without storing the shared data, and generating an overlay hierarchy tree comprising the shared data, the difference data, and indication information indicating nodes of the overlay hierarchy tree that comprise the difference data. The method further comprises rendering the first object using the data stored for the base hierarchy tree, and rendering the second object using any one or a combination of the shared data, the difference data, and the indication information.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Matthäus G. Chajdas, Konstantin I. Shkurko
  • Patent number: 11929114
    Abstract: A system and method for efficiently resetting data stored in a memory array are described. In various implementations, an integrated circuit includes a memory for storing data, and a processing unit that generates access requests for the data stored in the memory. When access circuitry of the memory array begins a reset operation, it reduces a power supply voltage level used by memory bit cells in a column of the array to a value less than a threshold voltage of transistors. Therefore, the p-type transistors of the bit cells do not contend with the write driver during a write operation. The access circuitry provides the reset data on the write bit lines, and asserts each of the write word lines of the memory array. To complete the write operation, the access circuitry returns the power supply voltage level from below the threshold voltage level to an operating voltage level.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 12, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Russell Schreiber, Kyle David Whittle
  • Patent number: 11928060
    Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: March 12, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sriram Srinivasan, John Kelley, Matthew Schoenwald
  • Patent number: 11928770
    Abstract: Methods and systems are disclosed for traversing nodes in a BVH tree by an intersection engine. Techniques disclosed comprise receiving, by the intersection engine, a traversal instruction, including a tracing-mode, ray data, and an identifier of a node to be traversed. Where the tracing-mode includes a closest hit mode and a first hit mode. If the node to be traversed is an internal node, the intersection engine determines, based on the tracing-mode, an order in which children nodes of the node are to be next traversed and output identifiers of the children nodes in the determined order.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: March 12, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Alexandre Tsakok, Skyler Jonathon Saleh
  • Publication number: 20240078017
    Abstract: A data processing system includes a data processor and a memory controller receiving memory access requests from the data processor and generating at least one memory access cycle to a memory system in response to the receiving. The memory controller includes a command queue and a sparse element processor. The command queue is for receiving and storing the memory access requests including a first memory access request including a small element request. The sparse element processor is for causing the memory controller to issue a second memory access request to the memory system in response to the first memory access request with a density greater than a density indicated by the first memory access request.
    Type: Application
    Filed: July 27, 2023
    Publication date: March 7, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vignesh Adhinarayanan, Niti Madan, Marjan Fariborz
  • Publication number: 20240078195
    Abstract: An electronic device includes a processor having processor circuitry and a leader memory controller, a controller coupled to the processor and having a follower memory controller, and a memory. The processor circuitry is operable to access the memory by issuing memory access requests to the leader memory controller. The leader memory controller is operable to complete the memory access requests using the follower memory controller to issue memory commands to the at least one memory die.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 7, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Niti Madan, Gabriel H. Loh, James R. Magro
  • Publication number: 20240078197
    Abstract: A data processing node includes a processor element and a data fabric circuit. The data fabric circuit is coupled to the processor element and to a local memory element and includes a crossbar switch. The data fabric circuit is operable to bypass the crossbar switch for memory access requests between the processor element and the local memory element.
    Type: Application
    Filed: June 29, 2023
    Publication date: March 7, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Gabriel H. Loh
  • Patent number: 11921784
    Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 5, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Dasika, Michael Ignatowski, Michael J Schulte, Gabriel H Loh, Valentina Salapura, Angela Beth Dalton
  • Patent number: 11921634
    Abstract: Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host is disclosed. In an implementation, a memory controller identifies a first write instruction to write first data to a first memory location, where the first write instruction is not a processing-in-memory (PIM) instruction. The memory controller then writes the first data to a first PIM register. Opportunistically, the memory controller moves the first data from the first PIM register to the first memory location. In another implementation, a memory controller identifies a first memory location associated with a first read instruction, where the first read instruction is not a processing-in-memory (PIM) instruction. The memory controller identifies that a PIM register is associated with the first memory location. The memory controller then reads, in response to the first read instruction, first data from the PIM register.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: March 5, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Jagadish B. Kotra, John Kalamatianos, Yasuko Eckert, Yonghae Kim
  • Patent number: 11922107
    Abstract: Systems and methods are disclosed that map quantum circuits to physical qubits of a quantum computer. Techniques are disclosed to generate a graph that characterizes the physical qubits of the quantum computer and to compute the resource requirements of each circuit of the quantum circuits. For each circuit, the graph is searched for a subgraph that matches the resource requirements of the circuit, based on a density matrix. Physical qubits, defined by the matching subgraph, are then allocated to the logical qubits of the circuit.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: March 5, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony T. Gutierrez, Salonik Resch, Yasuko Eckert, Gabriel H. Loh, Mark Henry Oskin, Vedula Venkata Srikant Bharadwaj
  • Patent number: 11923852
    Abstract: A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (I/O) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: March 5, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Prateek Mishra, Thanapandi G, Jagadeesh Anathahalli Singrigowda, Dhruvin Devangbhai Shah, Girish Anathahalli Singrigowda, Animesh Jain
  • Patent number: 11922207
    Abstract: An approach is provided for coalescing network commands in a GPU that implements a SIMT architecture. Compatible next network operations from different threads are coalesced into a single network command packet. This reduces the number of network command packets generated and issued by threads, thereby increasing efficiency, and improving throughput. The approach is applicable to any number of threads and any thread organization methodology, such as wavefronts, warps, etc.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: March 5, 2024
    Assignee: Advanced Micro Devices, Inc
    Inventors: Michael W. LeBeane, Khaled Hamidouche, Brandon K. Potter
  • Patent number: 11924338
    Abstract: A computing system may implement a split random number generator that may use a random number generator to generate and store seed values in a memory for retrieval and use by one or more core processors to generate random numbers for secure processes within each core processor.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: March 5, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David A Kaplan, Paul Moyer
  • Publication number: 20240069811
    Abstract: A data processing system includes a memory accessing agent for generating first memory access requests, a first memory system, and a first memory controller. The first memory system includes a first three-dimensional memory stack comprising a first plurality of stacked memory dice, wherein each memory die of the first three-dimensional memory stack includes a different logical rank of a first memory channel. The first memory controller picks second memory access requests from among the first memory access requests that access a given logical rank of the first memory channel, arbitrates between the second memory access requests, and generates memory access commands to the given logical rank in response to the arbitrating.
    Type: Application
    Filed: September 8, 2023
    Publication date: February 29, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Guanhao Shen, Ravindra Nath Bhargava
  • Publication number: 20240069915
    Abstract: A virtual padding unit provides a virtual padded data structure (e.g., virtually padded matrix) that provides output values for a padded data structure without storing all of the padding elements in memory. When the virtual padding unit receives a virtual memory address of a location in the virtual padded data structure, the virtual padding unit checks whether the location is a non-padded location in the virtual padded data structure or a padded location in the virtual padded data structure. If the location is a padded location in the virtual padded data structure, the virtual padding unit outputs a padding value rather than a value stored in the virtual padded data structure. If the location is a non-padded location in the virtual padded data structure, a value stored at the location is output.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Meysam Taassori, Shaizeen Dilawarhusen Aga, Mohamed Assem Abd ElMohsen Ibrahim, Johnathan Robert Alsop
  • Publication number: 20240070961
    Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include in a coarse binning pass, generating a sorted set of draw calls, based on geometry processed through a world space pipeline and vertex indices obtained from an input assembler.
    Type: Application
    Filed: December 27, 2022
    Publication date: February 29, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael John Livesley, Vishrut Vaibhav, Tad Robert Litwiller