Patents Assigned to Advanced Micro Devices, Inc.
  • Publication number: 20240235376
    Abstract: The disclosed voltage regulator circuit includes a capacitor bank configured for a first voltage step corresponding to a voltage undershoot, and a shunt circuit configured for a second voltage step exceeding the first voltage step. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: September 29, 2023
    Publication date: July 11, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David King Wai Li, Amanullah Samit, Indrani Paul, Meeta Surendramohan Srivastav, Sriram Sambamurthy
  • Publication number: 20240232079
    Abstract: Data routing for efficient decompressor use is described. In accordance with the described techniques, a cache controller receives requests from multiple requestors for elements of data stored in a compressed format in a cache. The requests include at least a first request from a first requestor and a second request from a second requestor. A decompression routing system identifies a redundant element of data requested by both the first requestor and the second requestor and causes decompressors to decompress the requested elements of data. The decompression includes performing a single decompression of the redundant element. After the decompression, the decompression routing system routes the decompressed elements to the plurality of requestors, which includes routing the decompressed redundant element to both the first requestor and the second requestor.
    Type: Application
    Filed: October 25, 2023
    Publication date: July 11, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Jeffrey Christopher Allan
  • Publication number: 20240235233
    Abstract: A device is disclosed that includes a battery charge controller having an input removably connected to a power adapter and an output supplying DC current to a battery, a voltage regulator having an input coupled to the output of the battery charge controller and the battery, and a current sensing unit used by the battery charge controller for sensing a charging current to the battery and by the voltage regulator for sensing a discharging current from the battery. Various other methods and systems are also disclosed.
    Type: Application
    Filed: January 5, 2024
    Publication date: July 11, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David King Wai Li, Amanullah Samit
  • Patent number: 12033035
    Abstract: A processing device, which improves processing performance, is provided which comprises memory configured to store data and a processor, in communication with the memory. The processor is configured to receive tuning parameters, each having a numeric value, for executing a portion of a program on an identified hardware device and convert the numeric values of the tuning parameters to words. The processor is also configured to predict, using one or more machine language learning algorithms, which combination of the words to execute the portion of the program on the identified hardware device based on performance efficiency and convert the predicted combination of the words to corresponding numeric values for executing the portion of the program on the identified hardware device.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jehandad Khan, Daniel Isamu Lowell
  • Patent number: 12034440
    Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rajesh Kumar, Edoardo Prete, Gerald R. Talbot, Ethan Crain, Tracy J. Feist, Jeffrey Cooper
  • Patent number: 12033238
    Abstract: Systems, apparatuses, and methods for implementing register compaction with early release are disclosed. A processor includes at least a command processor, a plurality of compute units, a plurality of registers, and a control unit. Registers are statically allocated to wavefronts by the control unit when wavefronts are launched by the command processor on the compute units. In response to determining that a first set of registers, previously allocated to a first wavefront, are no longer needed, the first wavefront executes an instruction to release the first set of registers. The control unit detects the executed instruction and releases the first set of registers to the available pool of registers to potentially be used by other wavefronts. Then, the control unit can allocate the first set of registers to a second wavefront for use by threads of the second wavefront while the first wavefront is still active.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Brian D. Emberling, Joseph Lee Greathouse, Anthony Thomas Gutierrez
  • Patent number: 12032965
    Abstract: Systems, apparatuses, and methods for arbitrating threads in a computing system are disclosed. A computing system includes a processor with multiple cores, each capable of simultaneously processing instructions of multiple threads. When a thread throttling unit receives an indication that a shared cache has resource contention, the throttling unit sets a threshold number of cache misses for the cache. If the number of cache misses exceeds this threshold, then the throttling unit notifies a particular upstream computation unit to throttle the processing of instructions for the thread. After a time period elapses, if the cache continues to exceed the threshold, then the throttling unit notifies the upstream computation unit to more restrictively throttle the thread by performing one or more of reducing the selection rate and increasing the time period. Otherwise, the unit notifies the upstream computation unit to less restrictively throttle the thread.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul James Moyer, Douglas Benson Hunt, Kai Troester
  • Patent number: 12032487
    Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: July 9, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Benjamin T. Sander, Mark Fowler, Anthony Asaro, Gongxian Jeffrey Cheng, Michael Mantor
  • Patent number: 12032548
    Abstract: A method of maintaining a probabilistic filter includes, in response to receiving a key K1 for adding to the probabilistic filter, generating a fingerprint F1 based on applying a fingerprint hash function HF to the key K1, identifying an initial bucket Bi1 by selecting between at least a first bucket B1 determined based on a first bucket hash function H1 of the key K1 and a second bucket B2 determined based on a second bucket hash function H2 of the key K1, and inserting the fingerprint F1 into the initial bucket Bi1; and resizing the probabilistic filter. Resizing the probabilistic filter includes incrementing a resize counter value, determining a bucket B? for the fingerprint F1 based on a value of the fingerprint F1 and the resize counter value, and inserting the fingerprint F1 into the bucket B? in the probabilistic filter.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Alexander D. Breslow
  • Patent number: 12032967
    Abstract: Devices and methods for partial sorting for coherence recovery are provided. The partial sorting is efficiently executed by utilizing existing hardware along the memory path (e.g., memory local to the compute unit). The devices include an accelerated processing device which comprises memory and a processor. The processor is, for example, a compute unit of a GPU which comprises a plurality of SIMD units and is configured to determine, for data entries each comprising a plurality of bits, a number of occurrences of different types of the data entries by storing the number of occurrences in one or more portions of the memory local to the processor, sort the data entries based on the determined number of occurrences stored in the one or more portions of the memory local to the processor and execute the sorted data entries.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthäus G. Chajdas, Christopher J. Brennan
  • Patent number: 12033714
    Abstract: A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nuwan S. Jayasena, Yasuko Eckert
  • Patent number: 12033275
    Abstract: Methods and systems are disclosed for executing a collaborative task in a shader system. Techniques disclosed include receiving, by the system, input data and computing instructions associated with the collaborative task, as well as a configuration setting, causing the system to operate in a takeover mode. The system then launches, exclusively in one workgroup processor, a workgroup including wavefronts configured to execute the collaborative task.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Brian Emberling, Michael Y. Chow
  • Patent number: 12033239
    Abstract: Systems, apparatuses, and methods for performing dead surface invalidation are disclosed. An application sends draw call commands to a graphics processing unit (GPU) via a driver, with the draw call commands rendering to surfaces. After it is determined that a given surface will no longer be accessed by subsequent draw calls, the application sends a surface invalidation command for the given surface to a command processor of the GPU. After the command processor receives the surface invalidation command, the command processor waits for a shader engine to send a draw call completion message for a last draw call to access the given surface. Once the command processor receives the draw call completion message, the command processor sends a surface invalidation command to a cache to invalidate cache lines for the given surface to free up space in the cache for other data.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Priyadarshi Sharma, Anshuman Mittal, Saurabh Sharma
  • Patent number: 12033721
    Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arijit Banerjee, John J. Wuu, Russell Schreiber
  • Publication number: 20240221284
    Abstract: A technique for performing ray tracing operations is provided. The technique includes determining error bounds for a rotation operation for a ray; selecting a technique for determining whether the ray intersects a bounding box based on the error bounds; and determining whether the ray hits the bounding box based on the selected technique.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sean Keely, Daniel James Skinner
  • Publication number: 20240220251
    Abstract: In accordance with described techniques for processing-in-memory (PIM) search stop control, a computing system or computing device includes a memory system that includes a stop condition check component, which receives an instruction that includes a programmed check value. The stop condition check component compares the programmed check value to outputs of a PIM component, and the stop condition check component initiates a stop instruction to stop the PIM component from processing subsequent computations based on an output of the PIM component matching the programmed check value.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Matthew R. Poremba, Ersin Cukurtas
  • Publication number: 20240219988
    Abstract: The disclosed device for power management of chiplet interconnects includes multiple chiplets connected via multiple interconnects. The device also includes a control circuit that detects activity states of the chiplets and manages power states of the interconnects based on the detected activity states. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: June 16, 2023
    Publication date: July 4, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Nicholas Carmine DeFiore, Sridhar Varadharajulu Gada, Benjamin Tsien, YanFeng Wang, Steven Zhou, Duanduan Chen, Malcolm Earl Stevens
  • Publication number: 20240220415
    Abstract: The disclosed computer-implemented method includes locating, from a processor storage, a partial tag corresponding to a memory request for a line stored in a memory having a tiered memory cache and in response to a partial tag hit for the memory request, locating, from a partition of the tiered memory cache indicated by the partial tag, a full tag for the line. The method also includes fetching, in response to a full tag hit, the requested line from the partition of the tiered memory cache. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Ganesh Balakrishnan, Kevin M. Lepak, Amit P. Apte
  • Publication number: 20240221854
    Abstract: A processing device used for MBIST is provided which comprises a data storage structure configured to store data, data protection circuitry configured to add at least one protection bit to corresponding portions of the data written to the data storage structure, data protection checking circuitry configured to identify one or more errors made by the data protection circuitry and an MBIST controller configured to receive the corresponding portions of data written to the data storage structure and receive at least one indication identifying the one or more errors.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Balatripura S. Chavali, Chetana Nagendra Keltcher, William Andrew Halliday
  • Publication number: 20240220320
    Abstract: An exemplary system comprises a cluster of nodes that are communicatively coupled to one another via at least one direct link and collectively include a plurality of memory devices. The exemplary system also comprises at least one system memory manager communicatively coupled to the cluster of nodes. In one example, the system memory manager is configured to allocate a plurality of sharable memory pools across the memory devices. Various other systems, methods, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Mahesh UdayKumar Wagh, Francisco L. Duran, Vydhyanathan Kalyanasundharam