Patents Assigned to Advanced Micro Devices, Inc.
  • Publication number: 20230305849
    Abstract: Array of pointers prefetching is described. In accordance with described techniques, a pointer target instruction is detected by identifying that a destination location of a load instruction is used in an address compute for a memory operation and the load instruction is included in a sequence of load instructions having addresses separated by a step size. An instruction for fetching data of a future load instruction is injected in an instruction stream of a processor. The data of the future load instruction is stored in a temporary register. An additional instruction is injected in the instruction stream for prefetching a pointer target based on an address of the memory operation and the data of the future load instruction.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Chetana N. Keltcher, Alok Garg, Paul S. Keltcher
  • Publication number: 20230305923
    Abstract: A memory system uses error detection codes to detect when errors have occurred in a region of memory. A count of the number of errors is kept and a notification is output in response to the number of errors satisfying a threshold value. The notification is an indication to a host (e.g., a program accessing or managing a machine learning system) that the threshold number of errors have been detected in the region of memory. As long as the number of errors that have been detected in the region of memory remains under the threshold number no notification need be output to the host.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sudhanva Gurumurthi, Ganesh Suryanarayan Dasika
  • Publication number: 20230307405
    Abstract: An electronic device can include a first die, a second die, and an interconnect. The first die or the second die has a principal function as a power module or a memory. The first die includes a first bond pad, and the second die includes a second bond pad. The device sides of the first and second dies are along the same sides as the first and second bond pads. In an embodiment, the first die and the second die are in a chip first, die face-up configuration. The first and the second bond pads are electrically connected along a first solderless connection that includes the interconnect. In another embodiment, each material within the electrical connection between the first and the second bond pads has a flow point or melting point temperature of at least 300° C.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Lei Fu, Raja Swaminathan, Brett P. Wilkerson
  • Publication number: 20230297381
    Abstract: Load dependent branch prediction is described. In accordance with described techniques, a load dependent branch instruction is detected by identifying that a destination location of a load instruction is used in an operation for determining whether a conditional branch is taken or not taken. The load instruction is included in a sequence of load instructions having addresses separated by a step size. An instruction is injected in an instruction stream of a processor for fetching data of a future load instruction using an address of the load instruction offset by a distance based on the step size. An additional instruction is injected in the instruction stream of the processor for precomputing an outcome of a load dependent branch using an address computed based on an address of the operation and the data of the future load instruction.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Chetana N. Keltcher, Alok Garg, Paul S Keltcher
  • Publication number: 20230298261
    Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include performing two-level primitive batch binning in parallel across multiple rendering engines, wherein tiles for subdividing coarse-level work across the rendering engines have the same size as tiles for performing coarse binning.
    Type: Application
    Filed: June 21, 2022
    Publication date: September 21, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael John Livesley, Ruijin Wu, Mangesh P. Nijasure
  • Publication number: 20230298256
    Abstract: A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.
    Type: Application
    Filed: June 20, 2022
    Publication date: September 21, 2023
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Daniel James Skinner, Michael John Livesley, David William John Pankratz
  • Publication number: 20230290400
    Abstract: A data transmission system includes a first integrated circuit. The first integrated circuit includes a first mixing terminal coupled to a first power supply voltage terminal at a point internal to the first integrated circuit, a first return terminal, a first resistor having a first terminal coupled to the first mixing terminal, and a second terminal for providing a first mixed voltage, and a second resistor having a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to the first return terminal.
    Type: Application
    Filed: June 30, 2022
    Publication date: September 14, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Aaron D Willey, Karthik Gopalakrishnan, Ramon Mangaser
  • Publication number: 20230290035
    Abstract: A system and method for performing graphics processing is provided. The system and method includes processing an allocation command for a buffer object; reserving processor address space for a data store of the buffer object with uncommitted physical memory in response to the allocation command including a null parameter, and reserving processor address space for a data store of the buffer object with committed physical memory in response to the allocation command including a non-null parameter.
    Type: Application
    Filed: May 19, 2023
    Publication date: September 14, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Graham Sellers, Eric Zolnowski, Pierre Boudier, Juraj Obert
  • Publication number: 20230289290
    Abstract: A method includes monitoring one or more metrics for each of a plurality of cache users sharing a cache, and assigning each of the plurality of cache users to one of a plurality of groups based on the monitored one or more metrics.
    Type: Application
    Filed: May 17, 2023
    Publication date: September 14, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventor: John Kelley
  • Publication number: 20230289070
    Abstract: A framework disclosed herein extends a relaxed, scoped memory model to a system that includes nodes across a commodity network and maintains coherency across the system. A new scope, cluster scope, is defined, that allows for memory accesses at scopes less than cluster scope to operate on locally cached versions of remote data from across the commodity network without having to issue expensive network operations. Cluster scope operations generate network commands that are used to synchronize memory across the commodity network.
    Type: Application
    Filed: May 19, 2023
    Publication date: September 14, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael W. LeBeane, Khaled Hamidouche, Hari S. Thangirala, Brandon Keith Potter
  • Publication number: 20230280819
    Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Alexander J. Branover, Christopher T. Weaver, Benjamin Tsien, Indrani Paul, Mihir Shaileshbhai Doctor, Thomas J. Gibney, John P. Petry, Dennis Au, Oswin Hall
  • Publication number: 20230280906
    Abstract: A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.
    Type: Application
    Filed: November 7, 2022
    Publication date: September 7, 2023
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Xuan Chen, Ross V. La Fetra, Michael John Litt
  • Publication number: 20230266975
    Abstract: Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including identifying that no instructions are available for which sufficient processing resources exist for execution together within the processing lane; and in response to the second identifying, executing an instruction independently of any other instruction.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Maxim V. Kazakov
  • Publication number: 20230252713
    Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, and updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 10, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Vineet Goel, Pazhani Pillai, Ruijin Wu, Christopher J. Brennan, Andrew S. Pomianowski
  • Publication number: 20230244751
    Abstract: A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 3, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Shaizeen Aga, Nuwan Jayasena, Allen H. Rush, Michael Ignatowski
  • Publication number: 20230214232
    Abstract: A processing device is provided which comprises memory and a processor, in communication with the memory. The processor is configured to acquire information indicating a sensory perception of a user, determine settings for one or more parameters used to control operation of the device based on the information indicating the sensory perception of the user and control the operation of the device by tuning the one or more parameters according to the determined settings.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventor: William Herz
  • Publication number: 20230214345
    Abstract: A device in an interconnect network is provided. The device comprises an end point processor comprising end point memory and an interconnect network link in communication with an interconnect network switch. The device is configured to issue, by the end point processor, a request to send data from the end point memory to other end point memory of another end point processor of another device in the interconnect network and provide, to the interconnect network switch, the request using memory addresses from a global memory address map which comprises a first global memory address range for the end point processor and a second global memory address range for the other end point processor.
    Type: Application
    Filed: December 30, 2021
    Publication date: July 6, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Brock A. Taylor
  • Publication number: 20230205420
    Abstract: A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the second memory address refers to data in a second memory section that is coupled to the first client via a cross connection; and servicing the second request via the cross connection.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vidyashankar Viswanathan, Richard E. George, Michael Y. Chow
  • Publication number: 20230205435
    Abstract: A phase training update circuit operates during a self-refresh cycle of a memory to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Scott P. Murphy, Huuhau M. Do
  • Publication number: 20230205539
    Abstract: Devices, methods and systems for managing resources in a computing device. Information regarding resource usage is captured. A prediction is generated, based on the information, that resource usage by a processor will exceed a threshold during an upcoming time. An operating parameter of the processor is adjusted, based on the prediction. In some implementations, information regarding memory bandwidth is captured. A prediction is generated, based on the information, that a memory region stored in a first memory device will be addressed by a memory intensive instruction during an upcoming time period. Data stored in the memory region is moved to a second memory device, based on the prediction.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Sergey Blagodurov, Masab Ahmad