Abstract: Disclosed herein are a package substrate, a chip package, and method for fabricating the same. The package substrate includes a package core comprising vias; a plurality of build-up layers disposed on an upper surface of the package core, the plurality of build-up layers comprising metal traces connected with the vias; and a magnetic core inductor disposed in a cavity of the package core. The magnetic core inductor includes a magnetic inlay, and a first metal layer disposed in the cavity on the magnetic inlay below the plurality of build-up layers. A second metal layer may be further disposed between the first metal layer and the metal traces. Both the first and second metal layers may be floating or grounded. The first and second metal layers are configured to shield other electronic components from being interfered by the magnetic field generated by the magnetic core inductor.

Abstract: A computing device and a method of performing crash analysis is provided. Each compute unit of an accelerated processor is configured to execute an application in a crash analysis operation mode, different from a normal operation mode, by executing a single instruction in isolation from any other instruction such that execution of the single instruction is completed prior to beginning execution of any of the other instructions. Examples of selectable crash analysis operation modes include a first mode in which execution of each memory instruction is completed prior to beginning execution of a next instruction, a second mode in which execution of each ALU instruction is completed prior to beginning execution of a next instruction, and a third mode in which execution of both memory and ALU instructions are completed prior to beginning execution of a next instruction.

Abstract: An integrated circuit device performs a method for adjusting a clock signal frequency. The method includes receiving a workload, and determining a latency parameter by sampling data of the workload. Further, an activation parameter is determined based on a data bandwidth on the workload. A clock signal of the IC device is adjusted based on the latency parameter and the activation parameter.

Abstract: Embodiments herein describe active condensation management for a sub-ambient cooling device. In an example, the sub-ambient cooling device includes first and second TEC systems arranged in a stacked configuration, where the first TEC system is positioned between an integrated circuit device and the second TEC system, an IC-facing surface of the second TEC system has features (e.g., channels and ribs) that control a location at which condensation occurs and that direct the condensation to a catch basin positioned within a gap between the TEC systems. The features may be designed to function in multiple orientations, which may be useful to permit a cooled device to operate upright or on its side. The sub-ambient cooling device may include an enclosure to define/restrict a volume of space to be dehumidified.

Abstract: A three-dimensional semiconductor package assembly includes a die. The die includes a plurality of through silicon vias (TSVs). The TSVs includes a first TSV and a second TSV. The first TSV supplies power from an active surface of the die to a back surface of the die. The assembly also includes a passive device coupled to the back surface of the die such that conductive contacts of the passive device electrically interface with the TSVs. The first passive device receives power through the first TSV and supplies power to the first die through the second TSV.

Abstract: Implementing a circuit design for a target integrated circuit includes receiving guide information including placement information for a circuit design from a prior implementation flow. A light incremental flow is performed on the circuit design using the guide information. The light incremental flow generates a placed and routed circuit design that re-uses at least a portion of the placement information from the prior implementation flow.

Abstract: A process of making a stacked semiconductor die can include a step of forming a conformal film of insulating material on one or more surfaces of a singulated semiconductor die. In some examples, the presence of the film tends to reduce the formation of cracks during the die stacking process.

Abstract: A request is received from an application to present content generated by the application in an overlay plane of a multi-plane display system. Responsive to determining that current system resources support presentation of the generated content in the overlay plane, frames of the generated content are displayed in the overlay plane and captured directly from the overlay plane such that the captured frames may be provided to one or more remote client computing systems independently of frames captured from one or more additional overlay planes and from an underlying composited desktop layer. Identifiers of prioritized applications may be maintained based on user preferences to determine specific applications for which generated content is enabled for display via overlay plane.

Abstract: Dynamic memory operations are described. In accordance with the described techniques, a system includes a stacked memory and one or more memory monitors configured to monitor conditions of the stacked memory. A system manager is configured to receive the monitored conditions of the stacked memory from the one or more memory monitors, and dynamically adjust operation of the stacked memory based on the monitored conditions. In one or more implementations, a system includes a memory and at least one register configured to store a ranking for each of a plurality of portions of the memory. Each respective ranking is determined based on an associated retention time of the respective portion of the memory. A memory controller is configured to dynamically refresh the portions of the memory at different times based on the ranking for each of the plurality of portions of the memory stored in the at least one register.

Abstract: An alignment system is provided. In one aspect, the alignment system includes a tray configured to mount into a rack. The tray includes a first electrical connector and a first alignment element. The alignment system also includes a component configured to mount into the rack. The component includes a second electrical connector and a second alignment element. The first alignment element is configured to mate with the second alignment element when the tray is slid into the rack. Mating of the first and second alignment elements aligns the first and second electrical connectors. The first and second electrical connectors are disposed along respective axes that are parallel with a direction that the tray is slid into the rack.

Abstract: A computing system includes a communication system comprising a glitch filter circuitry disposed in an integrated circuit (IC) device configured to receive an input signal and provide a glitch filter output signal based on the input signal. The glitch filter circuitry includes a control path circuitry configured to receive the input signal and generate a control signal based on detecting a glitch within the input signal, the control path circuitry including a configurable resistor capacitor (RC) filter circuitry configured to deliver a configurable RC filter circuitry output signal based on one or more selection signals. The control signal is based on the configurable RC filter circuitry output signal, and a data path circuitry configured to receive the control signal and mitigate glitches within the input signal based on the control signal.

Abstract: Systems and techniques for efficient memory setting are described. Memory setting is a common operation used by computing systems (e.g., operating systems and hypervisors) to write specific values, such as all ones or all zeroes, to obscure the current memory values to a memory region. In one example, a processor core issues a data-less write request that identifies a target address range for setting to a set value (e.g., ones, zeroes, or a random combination thereof). The data-less write request generally does not include a data payload. Instead, the set value is determined based on an index value associated with a lookup table at the memory controller or memory system or based on the target address range. In this way, the described systems and techniques accelerate memory setting operations with minimal data movement to save energy.

Abstract: An apparatus includes one or more controller circuits that are configured to be coupled to a first memory that implements random access and a second memory that implements serial access. A processing unit is configured to generate a map indicating a first set of addresses allocated to the first memory and a second set of addresses allocated to the second memory. The processing unit configures the controller circuit(s) to selectively access either the first memory or the second memory based on the map. In some cases, the first memory is a NOR-based memory, the second memory is a NAND flash memory, and the controller circuit is a serial peripheral interface (SPI) controller circuit. Selectively accessing the first memory or the second memory can include asserting a signal on a first or second chip select pin.

Abstract: A hybrid bonding method includes fabricating plural semiconductor devices in a region of a bottom wafer adjacent to a front surface thereof, fusion bonding the front surface to a carrier substrate, thinning the bottom wafer opposite to the front surface to expose conductive regions of the semiconductor devices, forming a dielectric layer over a backside of the semiconductor devices, forming openings in the dielectric layer to expose the conductive regions, forming metal pads within the openings, dicing the bottom wafer and the carrier substrate to singulate the plural semiconductor devices, bonding the dielectric layer overlying the backside of the semiconductor devices to a dielectric layer overlying a front surface of a top wafer, bonding the metal pads within the openings in the dielectric layer to metal pads overlying the front surface of the top wafer, and removing the carrier substrate from the front surface of the bottom wafer.

Abstract: An electronic device includes a package substrate having a top surface and a bottom surface. An integrated circuit (“IC”) die is disposed on the top surface of the package substrate. The electronic device also includes a stiffener having a ring body and a plurality of support members. The ring body is secured to the top surface of the package substrate and circumscribes the IC die. The plurality of support members extend from the ring body to below the bottom surface of the package substrate.

Abstract: The flow samples in a training set may be produced from a flow log, from an initial set of network rules, or from both. The flow samples may include header values for network flows and may be stored in a memory. A processor coupled to the memory may be configured for unsupervised and automatic networking rule production. The unsupervised and automatic rule production may include producing clusters of the flow samples and producing networking rules from the clusters, wherein each of the clusters may be used to produce one of the networking rules. An unsupervised learning algorithm may be used to produce the clusters.

Abstract: A system includes memory hardware including a memory and a processing-in-memory (PIM) component. A system includes a host including at least one core. The PIM component includes a memory die (e.g., a dynamic random access memory (DRAM) die) and a base die, e.g., a logic die. The base die includes one or more PIM arithmetic logic units (ALU) and one or more sense amplifiers. In at least some implementations the base die includes a shared static random-access memory (SRAM) cache that is shared between different ALU that reside in the base die.

Abstract: Multi-stack compute chip and memory architecture is described. In accordance with the described techniques, a package includes a plurality of computing stacks, and each computing stack includes at least one compute chip and a memory. The package also includes one or more interconnects that couple the computing stacks to at least one other computing stack for sharing the memory in a coherent fashion across the plurality of computing stacks.

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

Abstract: An apparatus and method for efficiently creating less computationally intensive nodes for a neural network. In various implementations, a computing system includes a memory that stores multiple input data values for training a neural network, and a processor. Rather than determine a bit width P of an integer accumulator of a node of the neural network based on bit widths of the input data values and corresponding weight values, the processor selects the bit width P during training. The processor adjusts the magnitudes of the weight values during iterative stages of training the node such that an L1 norm value of the weight values of the node does not exceed a corresponding weight magnitude limit.