Patents Assigned to Advanced Micro Devices, Inc.
  • Patent number: 10299403
    Abstract: Various modular thermal management systems for a computing device and methods of using the same are disclosed. In one aspect, a method of providing thermal management for a heat generating component is provided. The method includes placing a heat sink in thermal contact with the heat generating component and coupling a shroud to the heat sink. The shroud has a first opening to direct air in a first direction past the heat sink and a second opening to direct air in a second direction past the heat sink. Air is moved through the first opening or the second opening.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: May 21, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chris Janak, Christopher Jaggers, Ali Akbar Merrikh
  • Patent number: 10296292
    Abstract: A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: May 21, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Greg Sadowski, Wayne Burleson
  • Patent number: 10296230
    Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 21, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kedarnath Balakrishnan, James Raymond Magro
  • Patent number: 10296378
    Abstract: A system and methods embodying some aspects of the present embodiments for efficient load balancing using predication flags are provided. The load balancing system includes a first processing unit, a second processing unit, and a shared queue. The first processing unit is in communication with a first queue. The second processing unit is in communication with a second queue. The first and second queues are each configured to hold a packet. The shared queue is configured to maintain a work assignment, wherein the work assignment is to be processed by either the first or second processing unit.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 21, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Vinod Tipparaju, Lee Howes, Thomas Scogland
  • Publication number: 20190146799
    Abstract: A method, system, and computer program product synchronize a group of workitems executing an instruction stream on a processor. The processor is yielded by a first workitem responsive to a synchronization instruction in the instruction stream. A first one of a plurality of program counters is updated to point to a next instruction following the synchronization instruction in the instruction stream to be executed by the first workitem. A second workitem is run on the processor after the yielding.
    Type: Application
    Filed: November 29, 2018
    Publication date: May 16, 2019
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Lee W. HOWES, Benedict R. GASTER, Michael C. HOUSTON
  • Patent number: 10291258
    Abstract: Systems, apparatuses, and methods for generating error correction codes (ECCs) with two check symbols are disclosed. In one embodiment, a system receives a data word of length N?2 symbols, wherein N is a positive integer greater than 2, wherein each symbol has m bits, and wherein m is positive integer. The system generates a code word of length N symbols from the data word in accordance with a linear code defined by a parity check matrix. The parity check matrix is generated based on powers of ?, wherein ? is equal to ? raised to the (2m/4?1) power, ? is equal to a raised to the (2m/2+1) power, and ? is a primitive element of GF(2m). In another embodiment, the system receives a (N, N?2) code word and decodes the code word by generating a syndrome S from the code word using the parity check matrix.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 14, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Chin-Long Chen
  • Patent number: 10289413
    Abstract: A hybrid floating-point arithmetic processor includes a scheduler, a hybrid register file, and a hybrid arithmetic operation circuit. The scheduler has an input for receiving floating-point instructions, and an output for providing decoded register numbers in response to the floating-point instructions. The hybrid register file is coupled to the scheduler and contains circuitry for storing a plurality of floating-point numbers each represented by a digital sign bit, a digital exponent, and an analog mantissa. The hybrid register file has an output for providing selected ones of the plurality of floating-point numbers in response to the decoded register numbers. The hybrid arithmetic operation circuit is coupled to the scheduler and to the hybrid register file, for performing a hybrid arithmetic operation between two floating-point numbers selected by the scheduler and providing a hybrid result represented by a result digital sign bit, a result digital exponent, and a result analog mantissa.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 14, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David A. Roberts, Elliot H. Mednick, David John Cownie
  • Patent number: 10290606
    Abstract: Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an identification structure to an interposer. The identification structure is operable to provide identification information about the interposer. The identification structure is programmable to create or alter the identification information.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: May 14, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Alfano, Joe Siegel, Michael Z. Su, Bryan Black, Julius Din
  • Patent number: 10291692
    Abstract: Systems, apparatuses, and methods for implementing trusted cluster attestation techniques are disclosed. A cluster includes multiple computing devices connected together and at least one cluster security module. The cluster security module collects measurement logs and attestations from N computing devices, with N being a positive integer greater than one. The cluster security module also maintains a log and calculates an attestation for its own hardware and/or software. The cluster security module combines the logs from the N computing device and the log of the cluster security module into an aggregate log, with N+1 logs combined into the aggregate log. Then, the cluster security module generates a single attestation for the cluster to represent the cluster as a whole. The cluster security module is configured to provide the single attestation and aggregate log to an external device responsive to receiving a challenge request from the external device.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: May 14, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Andrew G. Kegel
  • Patent number: 10289567
    Abstract: A system for managing cache utilization includes a processor core, a lower-level cache, and a higher-level cache. In response to activating the higher-level cache, the system counts lower-level cache victims evicted from the lower-level cache. While a count of the lower-level cache victims is not greater than a threshold number, the system transfers each lower-level cache victim to a system memory without storing the lower-level cache victim to the higher-level cache. When the count of the lower-level cache victims is greater than the threshold number, the system writes each lower-level cache victim to the higher-level cache. In this manner, if the higher-level cache is deactivated before the threshold number of lower-level cache victims is reached, the higher-level cache is empty and thus may be deactivated without flushing.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 14, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: William L. Walker
  • Publication number: 20190141238
    Abstract: A method and apparatus of performing processing in an image capturing device includes receiving an image by the image capturing device. The image is filtered to generate a first visible light component and a second infrared component. A decontamination is performed on the infrared component to generate a decontaminated infrared component, and an interpolation is performed on the visible component to generate an interpolated visible component, both of which are provided to an image signal processor (ISP) for further processing.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 9, 2019
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Hui Zhou, Allen H. Rush, Yang Ling, Jiangli Ye
  • Publication number: 20190138234
    Abstract: A system includes a memory system comprising a memory module and a processor adapted to access the memory module using a memory controller that includes a controller having an input for receiving a power state change request signal and an output for providing memory operations, and a memory operation array comprising a plurality of entries. Each entry includes a plurality of encoded fields. The memory operation array is programmable to store different sequences of commands for particular types of memory of a plurality of types of memory in the plurality of entries that initiate entry into and exit from supported low power modes for the particular types of memory. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the at least one entry.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 9, 2019
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Thomas H. Hamilton
  • Publication number: 20190138088
    Abstract: A technique for adjusting the brightness values of images to be displayed on a stereoscopic head mounted display is provided herein. This technique improves the perceived dynamic range of the head mounted display by dynamically adjusting the pixel intensities (also known generally as “exposure”) of the images presented on the head mounted display based on a detected gaze direction. The head mounted display includes an eye tracker that is able to sense the gaze directions of the eyes. The eye tracker, head mounted display, or a processor of a computer system receives this information, determines an intersection point of the eye gaze and a screen within the head mounted display and identifies a gaze area around this intersection point. Using this gaze area, the processing system adjusts the pixel intensities of an image displayed on the screen based on the intensities of the pixels within the gaze area.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 9, 2019
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael A. Evans, Nathaniel David Naegle
  • Patent number: 10282309
    Abstract: Systems, apparatuses, and methods for implementing per-page control of physical address space distribution among memory modules are disclosed. A computing system includes a plurality of processing units coupled to a plurality of memory modules. A determination is made as to which physical address space distribution granularity to implement for physical memory pages allocated for a first data structure. The determination can be made on a per-data-structure basis (e.g., file, page, block, etc.) or on a per-application-basis. A physical address space distribution granularity is encoded as a property of each physical memory page allocated for the first data structure, and physical memory pages of the first data structure distributed across the plurality of memory modules based on a selected physical address space distribution granularity.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: May 7, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nuwan S. Jayasena, Hyojong Kim, Hyesoon Kim
  • Patent number: 10281964
    Abstract: A processing system includes one or more processing units to perform operations and one or more sensors to measure a temperature concurrently with the one or more processing units performing the operations. The processing system also includes a controller to receive feedback indicating the temperature and to determine a peak temperature and a thermal time constant for heating of the processing system based on a comparison of the measured temperature to a first temperature that is predicted based on the peak temperature and a previously determined thermal time constant for heating. Some embodiments of the controller can control a performance state of the processing system based on the peak temperature and the thermal time constant for heating of the processing system.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: May 7, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Can Hankendi, Manish Arora, Indrain Paul, Wei Huang, Srilatha Manne
  • Patent number: 10282295
    Abstract: A method includes monitoring, at a cache coherence directory, states of cachelines stored in a cache hierarchy of a data processing system using a plurality of entries of the cache coherence directory. Each entry of the cache coherence directory is associated with a corresponding cache page of a plurality of cache pages, and each cache page representing a corresponding set of contiguous cachelines. The method further includes selectively evicting cachelines from a first cache of the cache hierarchy based on cacheline utilization densities of cache pages represented by the corresponding entries of the plurality of entries of the cache coherence directory.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 7, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William L. Walker, Michael W. Boyer, Yasuko Eckert, Gabriel H. Loh
  • Patent number: 10282308
    Abstract: A method and apparatus for reducing TLB shootdown operation overheads in accelerator-based computing systems is described. The disclosed method and apparatus may also be used in the areas of near-memory and in-memory computing, where near-memory or in-memory compute units may need to share a host CPU's virtual address space. Metadata is associated with page table entries (PTEs) and mechanisms use the metadata to limit the number of processing elements that participate in a TLB shootdown operation.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: May 7, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nuwan Jayasena, Andrew G. Kegel
  • Patent number: 10282292
    Abstract: Cluster manager functional blocks perform operations for migrating pages in portions in corresponding migration clusters. During operation, each cluster manager keeps an access record that includes information indicating accesses of pages in the portions in the corresponding migration cluster. Based on the access record and one or more migration policies, each cluster manager migrates pages between the portions in the corresponding migration cluster.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: May 7, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Andreas Prodromou, Mitesh R. Meswani, Arkaprava Basu, Nuwan S. Jayasena, Gabriel H. Loh
  • Patent number: 10284861
    Abstract: A first memory stores values of blocks of pixels representative of a digital image, a second memory stores partial values of destination pixels in a thumbnail image, and a third memory stores compressed images and thumbnail images. A processor retrieves values of a block of pixels from the first memory. The processor also concurrently compresses the values to generate a compressed image and modify a partial value of a destination pixel based on values of pixels in portions of the block that overlap a scaling window for the destination pixel. The processor stores the modified partial value in the second memory and stores the compressed image and the thumbnail image in the third memory.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: May 7, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mahalakshmi Thikkireddy, Sateesh Lagudu
  • Patent number: 10283437
    Abstract: Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: May 7, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Richard T. Schultz, Omid Rowhani, Charles P. Tung