High frequency divider circuits and methods
Embodiments of the present invention include circuits and methods for dividing high frequency signals. In one embodiment the present invention includes a divider circuit comprising a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input and first and second differential outputs, wherein the differential circuit has a first bias current. The divider circuit further includes a cross-coupled circuit having outputs coupled to the differential circuit outputs and a second frequency control input, wherein the cross-coupled circuit has a second bias current. Embodiments of the present invention may include circuits for controlling the relationship between bias currents and circuit parameters that vary with process or temperature or both.
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The present invention relates to divider circuits, and in particular, to circuits and methods that may be used to implement a high frequency division.
Electronic systems often have many different components that include voltage or current signals that have different frequencies. It is often desirable to modify the frequencies of such signals as the signals are used to perform different tasks. One common modification to a signal is frequency division. Frequency division is the process of dividing a signal's frequency by some value (e.g., an integer or fraction). Circuits that perform frequency division are referred to as “Dividers” and are found in a wide variety of electronic applications.
When transistor M1 receives rising edge transition of the clock input, CK, M1 turns on and activates differential pair M3/M4. Thus, signal values at the gate inputs of M3/M4 (i.e., +in1 and −in1) will drive the outputs of the first DFF (i.e., −out1 and +out1) on the rising edge of CK. During this phase of the clock signal, bias current from transistors M7/M8 is directed through M3, M4 and M1, and the data value at the gate input is stored on the output nodes of the differential pair M3 and M4. When transistor M2 receives a rising edge transition of
The second DFF stage includes transistors M9-M16 connected is the same way as transistors M1-M8 in the first DFF stage. The rising edge of
In high frequency applications, each DFF stage, such as the ones in
Thus, there is a need for improved divider circuits, and in particular, for improved circuits and methods that may be used to implement high frequency division with optimized lock range.
SUMMARYEmbodiments of the present invention improve high frequency performance of divider circuits. In one embodiment, the present invention includes a divider circuit comprising a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input and first and second differential output nodes, wherein the differential circuit has a first bias current, and a cross-coupled circuit having a first control terminal coupled to a second output of the cross-coupled circuit and the first differential output node, a second control terminal coupled to a first output of the cross coupled circuit and the first differential output node, and a second frequency control input, wherein the cross-coupled circuit has a second bias current that is independent of the first bias current.
In another embodiment, the second bias current is a constant current and the first bias current is calibrated so that the ratio of the first bias current and a resistance is a constant. In yet another embodiment, the first bias current is a constant current and the second bias current is calibrated so that the product of the second bias current and a resistance is a constant.
In another embodiment, the present invention includes a first resistor having a first resistance coupled between the first differential output node and a supply terminal and a second resistor having a second resistance coupled between the second differential output node and the supply terminal. The first bias current may be generated by a first bias generator that is calibrated so that the ratio of the first bias current and the first or second resistance is a constant across process or temperature. In another embodiment, the second bias current is generated by a second bias generator that is calibrated so that the product of the second bias current and the first or second resistance is a constant across process or temperature.
In another embodiment, the present invention includes a load impedance coupled between first and second differential output nodes and a supply voltage, the load impedance including a control terminal for changing the impedance between the first and second differential output nodes and the supply voltage.
In another embodiment, the present invention includes a divider circuit comprising a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input and first and second differential output nodes, wherein the differential circuit is coupled to a first bias current generator, and a cross-coupled circuit having a first control terminal coupled to a second output of the cross-coupled circuit and the first differential output node, a second control terminal coupled to a first output of the cross coupled circuit and the first differential output node, and a second frequency control input, wherein the cross-coupled circuit is coupled to a second bias current generator.
In another embodiment, the present invention includes a divider circuit comprising first and second transistors having sources coupled together to form a differential circuit, the first transistor having a first output terminal and the second transistor having a second output terminal, first and second cross-coupled transistors having sources coupled together, the first cross-coupled transistor having a first output terminal coupled to the first output terminal of the first transistor and the second cross-coupled transistor having a second output terminal coupled to the second output terminal of the second transistor, a first resistor coupled between the first output terminal of the first transistor and a supply terminal, the first resistor having a first resistance value, a second resistor coupled between the second output terminal of the second transistor and the supply terminal, the second resistor having a second resistance value approximately equal to the first resistance value, a third transistor having a control terminal coupled to a signal to be divided and a first terminal coupled to the sources of the first and second transistors, wherein the third transistor is coupled to a first bias generator that generates first bias current in the first and second transistors, and a fourth transistor having an control terminal coupled to a complement of the signal to be divided and a first terminal coupled to the sources of the cross-coupled transistors, wherein the fourth transistor is coupled to a second bias generator that generates second bias current in the first and second cross-coupled transistors.
The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present invention.
Described herein are techniques for implementing high frequency division with optimized lock range. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.
One advantage of using different bias currents is that the lock performance of the circuit may be improved. The lock range is a function of the amplitude of oscillation and the center frequency, ωc, of the circuit. The amplitude of oscillation is given by the following equation:
Vs=4IyR/π,
where R is the resistance of the load impedance. The center frequency of the circuit is given by:
ωc=(1/RC)Ix/Iy,
where R is the resistance of the load impedance and C is the capacitance at the output nodes (i.e., +out1 and −out1). In one embodiment, Iy is maintained constant using a constant process and temperature invariant current source, and the differential bias current source, Ix, is calibrated so that the ratio of a differential bias current and a resistance is a constant (i.e., Ix/R=constant). In another embodiment, Ix is maintained constant using a constant process and temperature invariant current source, and the cross-coupled bias current source, Iy, is calibrated so that the product of a cross-coupled bias current and a resistance is a constant (i.e., R*Iy=constant).
Since the output of differential amplifier 710 is coupled back to the differential amplifier input, the feedback action will result in V1 and Vref being approximately equal. Variable resistor, Ro, can be calibrated using resistors 722-724 and switches 732-734. Such calibration may include a calibration for process variations (e.g., a one time process calibration) or a real-time calibration for temperature variations, or both, resulting in a substantially constant value for Ro. Since Io is a constant current source, the ratio of Io/Ro is constant. Constant Ix/R can be seen from the following equations:
Vref=V1
Ix*Ro=Io*R
Ix/R=Io/Ro
Therefore, since the voltage at the output of differential amplifier 710, Ix_bias, is used as the bias voltage for other stages in the circuit (e.g., the differential stage of
Maintaining a constant Ix/R, as illustrated above, will ensure that the center frequency of the oscillator will not vary with process or temperature. However, variation of resistance in the load impedance will also affect amplitude. For example, if the process resistance is low, the amplitude may be reduced and higher currents may be required for the circuit to operate properly. Alternatively, if the process resistance is high, the amplitude may be increased, which means that the circuit has more current than necessary for proper operation. Amplitude variations thus translate into increased power consumption because the current in the circuit is not optimized. To reduce the adverse effects of both center frequency variation and amplitude variation, embodiments of the present invention may use a constant current source for Ix, and use another bias generator that may be used to produce a cross-coupled bias current, Iy, wherein the product of Iy and a load resistance is a constant (i.e., R*Iy=constant).
Since the output of differential amplifier 810 is coupled back to the differential amplifier input, the feedback action will result in V2 and Vref being approximately equal. Vref may be maintained constant across process and temperature. Thus, constant Iy*R can be seen from the following equations:
V2=Vref
Iy*R=Vref=Constant
Therefore, since the voltage at the output of differential amplifier 810, Iy_bias, is used as the bias voltage for other stages in the circuit (e.g., the cross-coupled stage of
In this example, the bias current values in the differential circuit and cross-coupled circuit are set by bias voltages. Bias voltage Ix_bias is coupled to the control terminals of NMOS transistors M1 and M7 through resistors R5 and R7, respectively. Bias voltage Iy_bias is coupled to the control terminals of NMOS transistors M2 and M8 through resistors R6 and R8, respectively. In each stage, the differential circuit receives a bias voltage Ix_bias to produce a bias current Ix, and the cross-coupled circuit receives a bias voltage Iy_bias to produce a bias current Iy. Bias voltages Ix_bias and Iy_bias may be generated by bias generators (not shown), which may be of the type described above and illustrated in
The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents will be evident to those skilled in the art and may be employed without departing from the spirit and scope of the invention as defined by the claims. The terms and expressions that have been employed here are used to describe the various embodiments and examples. These terms and expressions are not to be construed as excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the appended claims.
Claims
1. A divider circuit comprising:
- a differential circuit having first and second inputs to receive a first differential signal and first and second differential output nodes, wherein the differential circuit has a first bias current generated by a first bias generator; and
- a cross-coupled circuit having a first control terminal coupled to a second output of the cross-coupled circuit and the first differential output node and a second control terminal coupled to a first output of the cross coupled circuit and the second differential output node, and wherein the cross-coupled circuit has a second bias current generated by a second bias generator that is independent of the first bias current,
- wherein the differential circuit is coupled to a first transistor having a control terminal to receive a signal to be divided, and wherein the first bias generator is coupled to the differential circuit through the first transistor, and
- wherein the cross-coupled circuit is coupled to a second transistor having a control terminal to receive the complement of the signal to be divided, and wherein the second bias generator is coupled to the cross-coupled circuit through the second transistor.
2. The divider circuit of claim 1 wherein the second bias current is a constant current and the first bias current is calibrated so that die ratio of the first bias current and a resistance is a constant.
3. The divider circuit of claim 1 wherein the first bias current is a constant current and the second bias current is calibrated so that the product of the second bias current and a resistance is a constant.
4. The divider circuit of claim 1 further comprising a first resistor having a first resistance coupled between the first differential output node and a supply terminal and a second resistor having a second resistance coupled between the second differential output node and the supply terminal, wherein the first bias generator is calibrated so that the ratio of the first bias current and the first or second resistance is a constant across process or temperature.
5. The divider circuit of claim 1 further comprising a first resistor having a first resistance coupled between the first differential output node and a supply terminal and a second resistor having a second resistance coupled between the second differential output node and the supply terminal, wherein the second bias generator is calibrated so that the product, of the second bias current and the first or second resistance is a constant across process or temperature.
6. The divider circuit of claim 1 further comprising a load impedance coupled between first and second differential output nodes and a supply voltage, the load impedance including a control terminal for changing the impedance between the first and second differential output nodes and the supply voltage.
7. A divider circuit comprising:
- a differential circuit having first and second inputs to receive a first differential signal, and first and second differential output nodes, wherein the differential circuit is coupled to a first bias current generator; and
- a cross-coupled circuit having a first control terminal coupled to a second output of the cross-coupled circuit and the first differential output node and a second control terminal coupled to a first output of the cross coupled circuit and the second differential output node, wherein the cross-coupled circuit is coupled to a second bias current generator,
- wherein the differential circuit is coupled to a first transistor having a control terminal for receiving a signal to be divided, and wherein the first bias current generator is coupled to the differential circuit through the first transistor, and
- wherein the cross-coupled circuit is coupled to a second transistor having a control terminal for receiving the complement of the signal to be divided, and wherein the second bias current generator is coupled to the differential circuit through the second transistor.
8. The divider circuit of claim 7 further comprising a first resistor coupled between the first differential output node and a supply terminal and a second resistor coupled between the second differential output node and the supply terminal, the first and second resistors having approximately equal resistance values, wherein the first bias current generator includes a third resistor having an approximately equal resistance value as the first and second resistors for generating a replica current, wherein, the ratio of the replica current and the resistance value of the third resistor is a constant across process or temperature.
9. The divider circuit of claim 7 further comprising a first resistor coupled between the first differential output node and a supply terminal and a second resistor coupled between the second differential output node and the supply terminal, die first and second resistors having approximately equal resistance values, wherein the first bias current generator includes a third resistor having an approximately equal resistance value as the first and second resistors for generating a replica current, wherein the product of the replica current and the resistance value of the third resistor is a constant across process or temperature.
10. The divider circuit or claim 7 wherein the first bias current generator is coupled through the first transistor in a folded cascade configuration.
11. The divider circuit of claim 7 wherein the second bias current generator is coupled through the second transistor in a folded cascade configuration.
12. A divider circuit comprising:
- first and second transistors having sources coupled together to form a differential circuit, the first transistor having a first output terminal and the second transistor having a second output terminal;
- first and second cross-coupled transistors having sources coupled together, the first cross-coupled transistor having a first output terminal coupled to the first output terminal of the first transistor and the second cross-coupled transistor having a second output terminal coupled to the second output terminal of the second transistor;
- a first resistor coupled between the first output terminal of the first transistor and a supply terminal, the first resistor having a first resistance value;
- a second resistor coupled between the second output terminal of the second transistor and the supply terminal, the second resistor having a second resistance value approximately equal to the first resistance value;
- a third transistor having a control terminal coupled to a signal to be divided and a first terminal coupled to the sources of the first and second transistors, wherein the third transistor is coupled to a first bias generator that generates first bias current in the first and second transistors; and
- a fourth transistor having an control terminal coupled to a complement of the signal to be divided and a first terminal coupled to the sources of the cross-coupled transistors, wherein the fourth transistor is coupled to a second bias generator that generates second bias current in the first and second cross-coupled transistors.
13. The divider circuit of claim 12, wherein the first bias generator is calibrated so that the ratio of the first bias current arid the first resistance value is constant across process or temperature.
14. The divider circuit of claim 13 wherein the first bias generator comprises a third resistor having a third resistance value approximately equal to the first resistance value, an amplifier, and a fifth transistor coupled between a first amplifier input and an output of the amplifier for generating a replica current in the fifth transistor, wherein the ratio of the replica current and the first resistance value is a constant across process or temperature.
15. The divider circuit of claim 12 wherein the second bias generator is calibrated so that the product of the second bias current and the first resistance value is a constant across process or temperature.
16. The divider circuit of claim 15 wherein the second bias generator comprises a third resistor having a third resistance value approximately equal to the first resistance value, an amplifier, and a fifth transistor coupled between a first amplifier input and an output of the amplifier for generating a replica current in the fifth transistor, wherein the product of the replica current and the first resistance value is a constant across process or temperature.
17. The divider circuit of claim 12 wherein first bias generator is coupled to the control terminal of the third transistor and the second bias generator is coupled to the control terminal of the fourth transistor.
18. The divider circuit of claim 12 wherein first bias generator is coupled to a second terminal of the third transistor and the second bins generator is coupled to a second terminal of the fourth transistor.
19. A divider circuit comprising:
- a differential circuit having first and second inputs to receive a first differential signal and first and second differential output nodes;
- a cross-coupled circuit having a first control terminal coupled to a second output of the cross-coupled circuit and the first differential output node and a second control terminal coupled to a first output of the cross coupled circuit and the second differential output node;
- a first transistor coupled to the differential circuit;
- a second transistor coupled to the cross coupled circuit;
- first bias means for biasing the differential circuit with a first bias current coupled to the differential circuit through the first transistor; and
- second bias means for biasing the cross-coupled circuit with a second bias current coupled to the cross-coupled circuit through the second transistor.
20. The divider circuit of claim 19 wherein the second bias means generates a constant current and the first bias means is calibrated so that the ratio of the first bias current and a resistance is a constant.
21. The divider circuit of claim 19 wherein the first bias means generates a constant current and the second bias means is calibrated so that the product of the second bias current and a resistance is a constant.
22. The divider circuit of claim 19 further comprising means for calibrating the first bias means.
23. The divider circuit of claim 19 further comprising means for calibrating the second bias means.
24. A method of dividing a signal comprising:
- receiving a first input signal to be divided on a frequency control input of a first transistor;
- receiving a complement of the first input signal on a frequency control input of a second transistor;
- coupling the first input signal to a differential circuit;
- coupling the complement of the first input signal to a cross-coupled circuit;
- coupling a first bias current through the first transistor to the differential circuit using a first bias current generator;
- coupling a second bias current through the second transistor to the cross-coupled circuit using a second bias current generator;
- operating the differential circuit using the first bias current; and
- operating the cross-coupled circuit using the second bias current.
25. The method of claim 24 wherein the first and second bias current generators output first and second voltages, and wherein the first voltage is coupled to a control terminal of the first transistor for generating the first bias current in the differential circuit, and wherein the second voltage is coupled to a control terminal of the second transistor for generating the second bias current.
26. The method of claim 24 wherein the first and second bias current generators output first and second currents, and wherein the first voltage is coupled to a terminal of the first transistor for generating the first bias current in the differential circuit, and wherein the second current is coupled to a terminal of the second transistor for generating the second bias current.
27. The method of claim 26 wherein the first and second bias current generators are folded cascade circuits.
28. The method of claim 24 wherein the second bias current is a constant current and the first bias current is calibrated so that the ratio of the first bias current and a resistance is a constant.
29. The method of claim 24 wherein the first bias current is a constant current and the second bias current is calibrated so that the product of the second bias current and a resistance is a constant.
30. The method of claim 24 wherein the second bias current is independent of the first bias current.
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Type: Grant
Filed: Jun 1, 2005
Date of Patent: Nov 20, 2007
Patent Publication Number: 20070024330
Assignee: WiLinx Corp. (Los Angeles, CA)
Inventors: Ahmad Mirzaei (Los Angeles, CA), Mohammad E Heidari (Los Angeles, CA), Masoud Djafari (Marina Del Rey, CA), Rahim Bagheri (Los Angeles, CA)
Primary Examiner: Linh My Nguyen
Assistant Examiner: Khaeem E. Almo
Attorney: Fountainhead Law Group P.C.
Application Number: 11/142,705
International Classification: H03K 21/00 (20060101);