Frequency Division Patents (Class 327/115)
  • Patent number: 10432183
    Abstract: A clock generation circuit having a deskew function and a semiconductor integrated circuit device including the same are provided. The clock generation circuit includes a clock gating circuit configured to gate an input clock signal based on a first waveform signal to generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and to generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal having a period which is N times a period of the input clock signal.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Ook Song, Bong Il Park, Jae Gon Lee
  • Patent number: 10432209
    Abstract: Disclosed is a linear feedback shift register (LFSR)-based clock signal generator that includes an LFSR, which outputs multi-bit states based on a system clock signal (CLK0). Based on the multi-bit states, a single-phase pulse generator generates first and second clock signals (CLK1 and CLK2), where the pulse rate of CLK1 is slower than that of the CLK0 and greater than that of CLK2. In some embodiments, a first multi-phase pulse generator can generate N-phases of the CLK1 based on CLK1 and N-phases of the CLK0 and a second multi-phase pulse generator can generate N-phases of CLK2 based on CLK2 and N-phases of CLK0. Furthermore, additional registers can optionally use the N-phases of CLK2 to further generate N sets of M-phases of the CLK2. Also disclosed are a multi-level circuit (e.g., a time domain-interleaved analog-to-digital converter (ADC)), which incorporates the LFSR-based clock signal generator, and associated methods.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven E. Mikes, Hayden C. Cranford, Jr., John K. Koehler, Steven J. Baumgartner
  • Patent number: 10425083
    Abstract: A divider circuit and method for generating one or more digital signals is presented. The circuit has a first output section for generating a first digital signal. There is a first output section with an output node to output the first digital signal, and a plurality of switches with one or more control switches. The plurality of switches selectively couple the output node to a first voltage and/or to selectively couple the output node to a second voltage, thereby generating the first digital signal. The or each control switch is prevents at least one of (i) the output node being coupled to the first and second voltages simultaneously and (ii) the output node being decoupled from both the first and second voltages simultaneously.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: September 24, 2019
    Assignee: Dialog Semiconductor B.V.
    Inventors: Vaibhav Maheshwari, Michail Papamichail
  • Patent number: 10411714
    Abstract: A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: September 10, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuki Yanagihara, Koji Tsutsumi
  • Patent number: 10401898
    Abstract: A signal processing circuit includes a clock generating circuit, a divider circuit, a converter, and an amplifier. The clock generating circuit outputs a first clock. The divider circuit divides the first clock to output a second clock having a frequency lower than a frequency of the first clock. The converter converts an input signal into a digital signal based on a first clock output from the clock generating circuit and a second clock output from the divider circuit. The amplifier, disposed between the clock generating circuit and the divider circuit, has a phase variation property opposite to a phase variation property of the divider circuit. The phase variation property of the divider circuit indicates a relationship between a phase variation amount of an output signal with respect to an input signal in the divider circuit and an ambient temperature of the divider circuit.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: September 3, 2019
    Assignee: NIHON DEMPA KOGYO CO., LTD.
    Inventor: Tomoya Yorita
  • Patent number: 10374651
    Abstract: An apparatus is disclosed for relocking of a locked loop. In an example aspect, the apparatus includes a locked loop, and the locked loop includes a loop and a locked-loop controller that is coupled to the loop. The loop is configured to run responsive to a run signal. The loop includes a memory state component and signal characteristic adjustment circuitry coupled to the memory state component. The signal characteristic adjustment circuitry is configured to produce an output signal having a characteristic that is based on the memory state component. The locked-loop controller is configured to receive an external power mode signal (EPMS). The locked-loop controller is also configured to generate the run signal to have an enable value at a first time when the EPMS is indicative of an external normal mode and at a second time when the EPMS is indicative of an external standby mode.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: August 6, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shyam Sundar Sivakumar, Kevin Jia-Nong Wang
  • Patent number: 10361627
    Abstract: An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) voltage converter coupled to the timebase generator. The timebase generator comprises a first linear feedback shift register (LFSR), a signal generator having an input coupled to an output of the first LFSR; and a digital divider comprising a second LFSR and a programmable digital divider, wherein a clock input of the programmable digital divider is coupled to an output of the signal generator, wherein an output of the programmable digital divider is coupled to a clock input of the first LFSR and is coupled to a clock input of the second LFSR, and wherein an output of the second LFSR is coupled to a program input of the programmable digital divider.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: July 23, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Joerg Erik Goller
  • Patent number: 10348316
    Abstract: A frequency division correction circuit includes: a first frequency divider configured to perform decimal frequency division on an input signal and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio; and a corrector configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: July 9, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Atsushi Matsuda
  • Patent number: 10340897
    Abstract: A clock circuit includes a first latch, second latch, first trigger circuit and clock trigger circuit. The first latch generates a first latch output signal based on a first control signal, an enable signal and an output clock signal. The second latch is coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal. The first trigger circuit is coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by a first node, is configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Yangsyu Lin
  • Patent number: 10313104
    Abstract: In some aspects, the disclosure is directed to methods and systems for controlling periodic jitter arising from a phase interpolator (PI). A receiver can receive incoming data. A fractional-N phase-locked loop (PLL) can receive a reference clock. Measurement circuitry can measure a parts per million (PPM) offset between the incoming data and the reference clock, of a PI. The fractional-N PLL can restrict jitter arising from the PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the PI.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 4, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Amiad Dvir, Mike Rolfe Ferrara, Vitaly Zborovski, Mario Caresosa, Ryan Hirth, Assaf Naor
  • Patent number: 10310015
    Abstract: An integrated circuit device includes a plurality of flip flops configured into a scan chain. The plurality of flip flops includes at least flip flop of a first type and at least one flip flop of a second type. A method includes generating a first scan clock signal for loading scan data into at least one flip flop of a first type, generating a second scan clock signal and a third scan clock signal for loading the scan data into at least one flip flop of a second type, and loading a test pattern into a scan chain defined by the at least flip flop of the first type and the at least one flip flop of the second type responsive to the first, second, and third scan clock signals.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: June 4, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas A. Clouqueur, Dwight K. Elvey, Kamran Zarrineh
  • Patent number: 10250237
    Abstract: An electronic latch circuit (100) and a multi-phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third output (Z, 108). The electronic latch circuit (100) further comprises an input circuit (101) comprising a first input (A, 102), a second input (B, 103) and a clock signal input (CLK, 104). The electronic latch circuit (100) is configured to change state based on input signals at the inputs (A, B, CLK) of the input circuit (101) and a present state of the output circuit (105). The multi-phase signal generator (300) comprises a plurality N of the electronic latch circuit (100) for generating N phase signals with individual phases. The plurality N of the electronic latch circuit (100) are cascaded with each other.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: April 2, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventor: Reza Bagger
  • Patent number: 10236889
    Abstract: An apparatus includes a fractional divider and a modulator circuit. The fractional divider circuit may be configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal. The modulator circuit may be configured to generate the selection signal in response to the feedback clock signal. The fractional divider may generate four phase clock signals from the divided clock signal. The four phase clock signals may be interleaved by the fractional divider circuit to select one of the four phase clock signals as the feedback clock signal. The fractional divider operates at a divide-by-4 clock speed. The selection signal may be synchronized in response to the divided clock signal to generate the feedback clock signal. The fractional divider circuit may be implemented using CMOS logic.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: March 19, 2019
    Assignee: Ambarella, Inc.
    Inventors: Tu-I Tsai, David Chiong, Dennis He, Chien-Tang Hu
  • Patent number: 10200020
    Abstract: A semiconductor device has a clock signal generation circuit that generates a clock signal, and a processing circuit that operates in accordance with the clock signal. The semiconductor device can also include an external terminal and a power source terminal that is coupled to the processing circuit. The clock signal generation circuit changes the frequency of the clock signal to be generated in accordance with the voltage value of a current consumption signal supplied to the external terminal. Further, the voltage value of the current consumption signal is changed in accordance with current consumption flowing in the power source terminal. The clock signal generation circuit can change the frequency of the clock signal to be generated in accordance with a value of an analog signal supplied to the external terminal.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: February 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuaki Gemma
  • Patent number: 10177748
    Abstract: The present invention relates to an electronic latch circuit, a method, and a 4-phase generator. The electronic latch circuit comprises an output circuit comprising an output X, and an output Y. The electronic latch circuit further comprises an input circuit, comprising an input A, an input B, and a clock signal input. The input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of a first state, a second state, and a third state. The input circuit is further configured to select the first state upon detecting a high state on the input B, a transition on the clock signal input from a low state to a high state, and a low state on the input A, and that the electronic latch circuit is in the second state.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: January 8, 2019
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventor: Reza Bagger
  • Patent number: 10128855
    Abstract: Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Shenggao Li, Stefan Rusu
  • Patent number: 10090842
    Abstract: A frequency divider may be provided. The frequency divider may be configured to generate a division signal having a variable cycle according to transition timing information and a division ratio signal.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: October 2, 2018
    Assignee: SK hynix Inc.
    Inventor: In Hwa Jung
  • Patent number: 10084458
    Abstract: According to one embodiment, a frequency divider circuit includes a 1st flip-flop including a 1st terminal to which a clock signal is input, and including a 2nd terminal to which a 1st signal is input; a 2nd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 2nd signal is input, the 2nd signal being output from the 1st flip-flop; a 3rd flip-flop including a 1st terminal to which the clock signal is input, and including a 2nd terminal to which a 3rd signal is input, the 3rd signal being output from the 2nd flip-flop; and an exclusive OR gate including a 1st terminal to which the 4th signal is input, and including a 2nd terminal to which a 5th signal is input, the 5th signal being output from the 2nd flip-flop.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: September 25, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoaki Kanagawa
  • Patent number: 10006964
    Abstract: Disclosed are a chip performance monitoring system, method and a computer program product, wherein a performance monitor output signal is propagated through an adjacent scan chain to avoid signal degradation incident to across-chip transmission of high frequency signals. Since the clock signal frequency used to control signal propagation through the scan chain will typically be less than twice the performance monitor output signal frequency, frequency sub-sampling with aliasing occurs. To compensate, signal propagation through the scan chain can be controlled during different time periods using different clock signals having different clock signal frequencies and, during these different time periods, different data outputs can be captured at an output node of the scan chain. The data output frequencies of these different data outputs can be measured and the performance monitor output signal frequency can be determined based on the different data output frequencies given the different clock signal frequencies.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Tad J. Wilder
  • Patent number: 9966964
    Abstract: An example embodiment disclosed herein enables at least one frequency divider chain of a multiphase divider circuit to ensure proper phase relations after multiple frequency divisions. Another example embodiment enables a unique reset sequence to maximize a timing margin for reset signals of the at least one frequency divider chain and, thus, maximizes a bandwidth of the multiphase divider circuit.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: May 8, 2018
    Assignee: Cavium, Inc.
    Inventors: Scott E. Meninger, JingDong Deng
  • Patent number: 9935579
    Abstract: A master voltage controlled oscillator (VCO) produces an output signal at an operating frequency of at least 100 gigaHertz (GHz). A buffer VCO injection-locked to an output of the master VCO produces an output signal at the operating frequency with a voltage swing greater than 50% of an output voltage swing of the master VCO output signal. The buffer VCO operates without pulling, and can drive a load of at least three times greater than a nominal load. Phase noise in the output of the buffer VCO is as much as ?96 decibels (dB) relative to the carrier (dBc) per Hertz (Hz) at 125 GHz with a 1 megaHertz (MHz) offset.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: April 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Richard Gu, Daquan Huang
  • Patent number: 9906226
    Abstract: A multi-modulus frequency divider includes a frequency division module, a frequency selection module, and a retiming module. The frequency division module is configured to receive an input signal and perform mufti-mode frequency processing on the input signal, so as to generate and output a plurality of divided signals to the frequency selection module. The frequency selection module is configured to receive the plurality of divided signals from the frequency division module, select a divided signal having a desired frequency from among the plurality of divided signals, and output the selected divided signal to the retiming module. The retiming module is configured to receive the selected divided signal from the frequency selection module, perform a retiming operation on the selected divided signal, and output a retimed selected divided signal.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: February 27, 2018
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Hailong Jia
  • Patent number: 9859899
    Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: January 2, 2018
    Assignee: Rambus Inc.
    Inventors: Marko Aleksić, Brian S. Leibowitz
  • Patent number: 9859875
    Abstract: A latch and a frequency divider are provided. The latch includes: a first logic unit coupled between a power supply and a ground wire, wherein the first logic unit includes a first input terminal and a first output terminal; a second logic unit having a structure symmetrical to that of the first logic unit, wherein the second logic unit includes a second input terminal and a second output terminal; and a first feedforward control unit adapted for cutting off a first current path, wherein the first feedforward control unit includes a first clock signal input terminal adapted for receiving a first clock signal, a third output terminal coupled to the first output terminal, and at least two feedforward control terminals, at least one of which is coupled to the first input terminal or the second input terminal. Power consumption of the latch and the frequency divider can be reduced.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: January 2, 2018
    Assignee: SPREADTRUM COMMUNICATIONS (SHANGHAI) CO., LTD.
    Inventors: Yiqiang Wu, Jiewei Lai
  • Patent number: 9853540
    Abstract: A power supply circuit is intended to suppress power consumption when a load is not driven and to shorten a required time to be taken until a boosted voltage to be supplied to a high-side MOS transistor is stabilized when the load is changed from a deactivated state to an activated state. The power supply circuit (power supply circuit 3) supplying power to a load driving circuit (motor driving circuit 2) that drives a load by controlling a high-side MOS transistor M1 on the basis of an input load control signal includes a booster circuit (charge pump 23) configured to boost a voltage of input power and supplies the power of which the voltage is boosted as power for driving the high-side MOS transistor. The booster circuit has power supply capability which varies depending on the load control signal.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: December 26, 2017
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Masami Aiura
  • Patent number: 9843329
    Abstract: A frequency divider circuit can achieve multi-modulus operation. The frequency divider includes clocking transistor devices, memory transistor circuits, write transistor devices, and a current source bias. The clocking transistor devices receive a differential input signal having a first frequency at an input of the frequency divider. The memory transistor circuits store signals based on the differential input signal from the clocking transistor devices. The write transistor devices make a divided frequency signal available at an output terminal. The current source bias is coupled to the clocking transistor devices. The current source bias applies a bias current to adapt the frequency divider to a common-mode at the input of the frequency divider.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: December 12, 2017
    Assignee: NXP B.V.
    Inventor: Javier Mauricio Velandia Torres
  • Patent number: 9838020
    Abstract: A programming method includes an upper computer, a calculation module, and a first signal conversion module. The calculation module includes a second signal conversion module and a programming interface. The upper computer is configured to convert programming data into first bus signals. When the calculation module is in a normal programming state, the second signal conversion module converts the first bus signals into first clock signals and first data signals to program the calculation module. When the calculation module is in a non-normal programming state, the first signal conversion module converts the first bus signals into second clock signals and second data signals to program the calculation module. A programming method is also provided.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: December 5, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Yao-Tsung Chang
  • Patent number: 9797936
    Abstract: An improved counter may implement dynamic frequency measurement while also remaining fully backwards compatible with traditional frequency measurement methods. The counter may operate according to low-frequency, large range, and/or high frequency modes of operation. It may be programmable with a divisor value associated with the large range operating mode, and a measurement time associated with the high frequency mode of operation. The divisor and measurement time settings may be enabled or disabled, and when either setting is disabled, the counter becomes backwards compatible with traditional frequency measurement methods. The counter may also be provided with inputs representative of the desired type of measurement and the minimum and maximum expected values for the signal to be measured. The counter may perform the frequency measurement according to any one or more of the operating modes, and return a measurement result obtained in the operating mode that completes the measurement first.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: October 24, 2017
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventors: Adam H. Dewhirst, Chee Fai Yap
  • Patent number: 9788379
    Abstract: An LED based illumination device is dimmed by controlling an average current supplied to the LED based illumination device. The currently supplied to the LED may be supplied by an LED driver that is in communication with a dimming control engine. The dimming control engine may receive an indication of a desired average current level. The dimming control engine controls the LED driver to periodically switch a current supplied to an LED of the LED based illumination device from a high state to a low state over a switching period, wherein both a duration of the switching period is adjusted and a ratio of a time in the high state to a time in the low state is adjusted as the average current supplied to the LED based illumination device transitions from a first average current level to the desired average current level.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: October 10, 2017
    Assignee: Xicato, Inc.
    Inventors: Barry Mark Loveridge, Jeffrey P. Hushley
  • Patent number: 9756410
    Abstract: Extending a microphone interface. One microphone interface extension includes a controller, a parent microphone, and a child microphone. The controller outputs a controller clock signal. The parent microphone receives the controller clock signal and generates a first data signal. The child microphone generates a second data signal and outputs the second data signal to the first parent microphone. The parent microphone receives the second data signal from the child microphone and outputs a combined data signal to the controller based on the first data signal and the second data signal. The parent microphone outputs the combined data signal to the controller on a phase of a microphone clock signal derived from the controller clock signal.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: September 5, 2017
    Assignee: Robert Bosch GmbH
    Inventors: Philip Sean Stetson, Sucheendran Sridharan
  • Patent number: 9755574
    Abstract: Various aspects of an injection-locked oscillator and method for controlling jitter and/or phase noise are disclosed herein. In accordance with an embodiment, an injection-locked oscillator includes one or more circuits that are configured to receive a pair of complementary phase output signals from one or more gain stages of the injection-locked oscillator. The one or more circuits may be configured to receive one or more switching signals. The received pair of complementary phase output signals are shorted by use of the one or more received switching signals. The shorting reduces the phase difference between an input signal and an output signal of the injection-locked oscillator.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: September 5, 2017
    Assignee: SONY CORPORATION
    Inventor: Jeremy Chatwin
  • Patent number: 9742410
    Abstract: A programming system includes an upper computer, a calculation module, and a first signal conversion module. The calculation module includes a second signal conversion module and a programming interface. The upper computer is configured to convert programming data into first bus signals. When the calculation module is in a normal programming state, the second signal conversion module converts the first bus signals into first clock signals and first data signals to program the calculation module. When the calculation module is in a non-normal programming state, the first signal conversion module converts the first bus signals into second clock signals and second data signals to program the calculation module. A programming method is also provided.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: August 22, 2017
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Yao-Tsung Chang
  • Patent number: 9735813
    Abstract: Described is an apparatus for boosting a transition edge of a signal, the apparatus comprises: a logic to provide input data having a Unit Interval (UI); a programmable delay unit to receive the input data and operable to delay the input data by a fraction of the UI to generate a delayed input data; and one or more drivers to drive the input data and the delayed input data to a node.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Shenggao Li, Xiaoqing Wang
  • Patent number: 9734265
    Abstract: A voltage-controlled oscillator (VCO), includes a resonator circuit connected to receive an input voltage and having a first output node and a second output node; and at least one cross-coupled switching circuit portion, each cross-coupled switching circuit portion comprising a first transistor having a drain connected to the first output node and a second transistor having a drain connected to the second output node, the first transistor having a gate connected between the drain of the second transistor and the second output node and the second transistor having a gate connected between the drain of the first transistor and the first output node, each of the first and second transistors having a threshold voltage that is determined to be the highest threshold voltage available for the process used to create the VCO.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 15, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Himanshu Arora, Siraj Akhtar, Nikolaus Klemmer
  • Patent number: 9729133
    Abstract: According to an embodiment, an electronic transmission element is provided that has a first input and a first output. The first input is coupled to the first output by means of two first, parallel-connected complementary switches. The first switches each have a control input. The electronic transmission element further has a second input and a second output. The second input is coupled to the second output by means of two second, parallel-connected complementary switches. The second switches each have a control input. The first output is coupled to the control inputs of the second switches and the second output is coupled to the control inputs of the first switches.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: August 8, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Thomas Kuenemund
  • Patent number: 9705664
    Abstract: A synthesizer module arranged to generate a timing signal. The synthesizer module comprises an odd-numbered frequency divider circuit arranged to receive a reference timing signal and to output at least one frequency-divided signal having a frequency equal to 1/M times the frequency of the reference timing signal, where M is an odd-numbered integer. A 90° phase-shift component is arranged to receive the reference timing signal and to output a 90° phase-shifted form of the reference timing signal. A re-timing circuit is arranged to re-time a set of transitions of the frequency-divided signal to be temporally aligned to transitions of the 90° phase-shifted form of the reference timing signal to generate the timing signal comprising the re-timed transitions of the frequency-divided signal.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: July 11, 2017
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventor: Nandigam Venkata Murali
  • Patent number: 9698800
    Abstract: A system and a method generate clock signals using an output divider with modulus steps of half-integers (i.e., the output circuit includes a divider which divides by one or more of 2, 2.5, 3, 3.5, 4 . . . ).
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: July 4, 2017
    Assignee: Linear Technology Corporation
    Inventor: Jan-Michael Stevenson
  • Patent number: 9680363
    Abstract: Methods and apparatus relating to a low ripple mechanism of mode change in switched capacitor voltage regulators are described. In an embodiment, a mode change of a Switching Capacitor Voltage Regulator (SCVR) is caused based at least in part on a comparison of an output voltage of the SCVR and a reference voltage. The output voltage is sensed based at least in part on a clock signal. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: George E. Matthew, Rinkle Jain, Vaibhav Vaidya
  • Patent number: 9647669
    Abstract: Disclosed examples include frequency divider circuits, comprising an even number 4 or more differential delay circuits coupled in a cascade ring configuration of a configurable length N, with N?K of the N delay circuits providing an inverted polarity output signal to a succeeding delay circuit in the cascade ring configuration to control an amount of overlap between phase shifted clock signals from the delay circuits.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: May 9, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sudipto Chakraborty
  • Patent number: 9641316
    Abstract: Embodiments of the present invention disclose a frequency divider and a radio communications device. The frequency divider includes a shift register unit and an output frequency synthesizing unit; the shift register unit includes multiple cyclically cascaded basic units; a basic unit at each level includes 2N D flip-flops connected in series and a multiplexer, outputs of the 2N D flip-flops connected in series are separately connected to the multiplexer; an output of the multiplexer is connected to an input of a next-level basic unit; the output frequency synthesizing unit superposes an output signal of the first D flip-flop of the basic unit at each level to generate a frequency division output signal.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: May 2, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zhaoxin Ma, Nianyong Zhu
  • Patent number: 9608801
    Abstract: A divider circuit determines whether an input factor (N) is an even number or an odd number. If N is an even number then the input clock is divided by N/2 to generate an intermediate clock. The intermediate clock is further divided by two to generate a div-by-2 clock, which is provided as the output clock with fifty percent duty cycle. If N is an odd number, the input clock is divided by (N/2?0.5) in a first duration and by (N/2+0.5) in a second duration to generate the intermediate clock, which is then divided by two to generate the div-by-2 clock. A delayed clock is generated from the div-by-2 clock, wherein the delayed clock lags the div-by-2 clock by half cycle duration of the input clock. The div-by-2 clock and the delayed clock are combined to generate the output clock with fifty percent duty cycle.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: March 28, 2017
    Assignee: AURA SEMICONDUCTOR PVT. LTD
    Inventors: Sandeep Perdoor, Vaibhav Maheshwari, Augusto Marques
  • Patent number: 9599673
    Abstract: An integrated circuit (IC) that is operable in scan test and functional modes includes scan-in pads, scan-out pads, scan chains, a compressor, a decompressor, a test control register, and a scan controller. The scan controller includes a multiple input shift register (MISR), an inverter, and multiple logic gates. The scan-in and scan-out pads receive scan test data and masking signals, respectively. The decompressor provides decompressed scan test data to the scan chains, which generate functional responses based on the decompressed scan test data. The compressor provides compressed functional responses to the scan controller. The logic gates receive the compressed functional responses and the masking signals from the compressor and the corresponding scan-out pads, respectively, and generate corresponding masked signals. The masking signals mask non-deterministic values in the decompressed functional responses. The MISR receives the masked signals and generates an error free signature.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: March 21, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Anurag Jindal, Nipun Mahajan
  • Patent number: 9577646
    Abstract: In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: February 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Bupesh Pandita, Hanan Cohen, Eskinder Hailu, Kenneth Luis Arcudia
  • Patent number: 9563227
    Abstract: A modulated clock device is provided that includes an update device for updating a phase of the modulated clock device. In one example, the update device includes an update phase multiplexer coupled to an output phase multiplexer of an output clock generator and configured to receive an input clock signal and one or more phases of the input clock signal; an output phase fractional counter coupled to the update phase multiplexer and configured to receive an update clock signal and to generate an output phase; and an update phase device coupled to the output phase fractional counter and to the update phase multiplexer. The output phase fractional counter is further configured to send the output phase to the output phase multiplexer and to the update phase device. The update phase device is configured to generate an update phase and to send the update phase to the update phase multiplexer.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: February 7, 2017
    Assignee: NVIDIA CORPORATION
    Inventor: Tom J. Verbeure
  • Patent number: 9548724
    Abstract: A clock generation device generates a clock signal which has a predetermined number of clocks for each predetermined time in such a way that a clock signal (32.768 kHz+? (? is zero or a positive number)) is input and some clocks of the clock signal are masked.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: January 17, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Yuichi Toriumi
  • Patent number: 9547475
    Abstract: According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: January 17, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Yasuda, Tetsufumi Tanamoto, Noriko Inoue, Akira Tomita, Ryusuke Murakami, Atsushi Shimbo
  • Patent number: 9543947
    Abstract: A semiconductor device containing a terminal, a power supply voltage dropping circuit that generates a constant voltage, a switch circuit to periodically apply a constant voltage to a terminal in response to a first clock, a current-controlled oscillator circuit, and a counter, and in which the power supply voltage dropping circuit supplies a first current to the switch circuit, the current-controlled oscillator circuit generates a second clock whose frequency changes in response to the value of the first current, and the counter counts the number of second clocks within the counting time.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: January 10, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Masahiro Araki
  • Patent number: 9531358
    Abstract: A signal generating system for generating an output signal with a 50% duty cycle, comprising: a frequency dividing module, comprising an odd number of level triggering devices, for generating a plurality of frequency divided signals utilizing a frequency dividing ratio equaling to M, wherein the M is an positive integer; and a signal combining module, for combining at least two of the frequency divided signals to generate at least one output combined signal. The signal generating system generates the output signal based on the output combined signal. The frequency dividing module cooperates the signal combining module to provide a frequency dividing ratio equaling to N.5, wherein the N is a positive integer.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: December 27, 2016
    Assignee: MEDIATEK INC.
    Inventors: Sheng-Che Tseng, Yao-Chi Wang
  • Patent number: 9520965
    Abstract: A method for reducing a frequency error, including: applying a plurality of dither values to a local reference clock over a first time interval; sampling, during the first time interval and using the local reference clock, a first plurality of data values received over an asynchronous link, where the first plurality of data values are transmitted over the asynchronous link based on a remote reference clock; tracking a plurality of errors from sampling the first plurality of data values; and adjusting, based on the plurality of errors, a frequency of the local reference clock to reduce the frequency error between the local reference clock and the remote reference clock.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: December 13, 2016
    Assignee: Ciena Corporation
    Inventor: Shawn Barrow
  • Patent number: 9515663
    Abstract: A method of configuring a prescaling circuit in a performance counter circuit for a computer processing system can include receiving a first number of signaled events at a prescaling circuit configured to generate event counts for a performance counter circuit. The method can include generating event counts at a current event-count rate for the first number of signaled events and determining a detected event-count rate for the signaled events based on a rate at which the first number of signaled events are received at the prescaling circuit. The method can include determining that the detected event-count rate is greater than the current event-count rate. The method can include increasing the current event-count rate in response to determining that the detected event-count rate is greater than the current event-count rate.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: December 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prasanna Jayaraman, Charles F. Marino, Srinivas B. Purushotham, Srinivasan Ramani