Abstract: A dual-edge aware clock divider configured to generate an output clock based on the input clock and a ratio of an integer M over an integer N is disclosed herein. The frequency of the output clock is based on a frequency of the input clock multiplied by the ratio (M/N), wherein M may be set to a range up to N. The output clock includes M pulses within a sequence time window having a length of N periods of the input clock. The output clock includes one or more rising edges that are substantially time aligned with one or more rising edges and one or more falling edges of the input clock, respectively. The dual-edge aware clock divider is configured to generate the output clock based on inverted and non-inverted portions of the input clock. A hybrid clock divider including the dual-edge and single-edge aware techniques is provided.

Abstract: An AND gate comprises: a first input; a second input; an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output.

Abstract: Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.

Abstract: A dual frequency HF-UHF RFID integrated circuit including a power supply. The power supply includes: an HF branch including an HF rectifier and a linear voltage regulator, wherein the HF rectifier is configured to be connected to a resonance circuit formed by a HF antenna-coil and a resonance capacitor and wherein the HF rectifier is connected to the linear voltage regulator; a UHF branch including a UHF rectifier and a shunt voltage regulator, wherein the UHF rectifier has a charge pump and is configured to be connected to a UHF antenna and wherein the UHF rectifier is connected to the shunt voltage regulator; and a supply line, wherein the linear voltage regulator and the shunt voltage regulator are both connected to the supply line of the power supply.

Abstract: An AND gate comprises: a first input; a second input; an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output.

Abstract: A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.

Abstract: Methods and apparatus for generating phase-shifted clock signals from a reference clock, connecting the phase-shifted clock signals to a counter module so that the phase-shifted clock signals change values in counters in the counter module, and combining the values in the counters to generate an output signal corresponding to an amount of time. One or more events can be detected at a time corresponding to the output signal. In embodiments, pulses can be transmitted and received at a measure time to evaluate connected devices.

Abstract: A semiconductor integrated circuit includes a first circuit and a second circuit. The first circuit is configured to divide a first pulse signal having a first duty cycle by N (where N is an integer of 2 or more), and output 2×N second pulse signals of which phases are different from each other. The first pulse signal is a pair of differential signals. The second circuit is configured to receive one or more selection signals and calculate a logical product of one of the one or more selection signals and two of the 2×N second pulse signals to generate a third pulse signal having a second duty cycle less than the first duty cycle.

Abstract: A frequency adjusting apparatus used in a processing chip operated at an operation frequency according to a power is provided that includes a clock supplying circuit, a frequency division circuit and a control circuit. The clock supplying circuit outputs one of clock signals as a supplied clock signal. The frequency division circuit performs frequency division on the supplied clock signal according to a parameter to generate an output clock signal. The control circuit determines a combination of a selected clock signal and a value of the parameter for gradually increasing the frequency of the output clock signal during the increasing of the voltage value that passes through voltage value sections, wherein when the voltage value is determined to be larger than a second threshold value and when the voltage value sections correspond to higher voltage values, the selected clock signal has a higher frequency.

Abstract: The disclosed systems, structures, and methods are directed to a low jitter phase-lock loop (PLL) based frequency synthesizer, comprising a first frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a voltage control oscillator (VCO), a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises a quadrature generator, an input conditioner, a phase rotator, a current mode logic (CML), and a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector.

Abstract: Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.

Abstract: A communication system allows for clock synchronization between a transmitter and a receiver when switching from transmission of an analog signal to transmission of a digital signal. The system uses clock synchronization during transmission of the digital signal, but the clock synchronization may be lost when switching to transmission of an analog signal. A digital clock synchronization is embedded in the analog signal so that the clock synchronization between the transmitter and the receiver may be reestablished upon switching to a digital signal without any delay in transmission of the digital signal.

Abstract: A timing control circuit in an integrated circuit memory device. The circuit has an input line, a first output line and a second output line. The input line configured to receive a control signal for the timing control circuit to generate, a first selection input on the first output line and a second selection input on the second output line. In response to the control signal transitioning from a first state to a second state, the first selection input completes a first transition before the second selection input starts a second transition (e.g., for selection between 0V and ?4.5V); and in response to the control signal transitioning from the second state to the first state, the second selection input completes a third transition before the first selection input starts fourth transition (e.g., for selection between 5V and 1.2V). The sequential transitions avoid simultaneous selection of 5V and ?4.5V.

Abstract: An integrated circuit (IC) with a TSV test circuit, a TSV test method are provided, pertaining to IC technologies. The IC may include a first TSV, a second TSV and a phase detector. A first end of the first TSV may be coupled to a predetermined signal output, and a second end of the first TSV may be coupled to a first end of the second TSV. A second end of the second TSV may be coupled to a first input of the phase detector, and a second input of the phase detector may be coupled to the predetermined signal output. The phase detector may be configured to determine a phase difference between signals at the first and the second inputs. In this IC, a defective TSV can be identified and segregated with a redundant TSV. This IC facilitates efficient fault correction and signal routing in the IC.

Abstract: A clock phase control circuit includes a clock input gate module, first and second shift register divider modules, and a multiplexer. The clock input gate module is configured to produce, based on an oscillating input clock signal, first and second intermediate clock signals. The first shift register divider module is configured to produce at least one first phase clock signal based on the first intermediate clock signal, where the at least one first phase clock signal has a different frequency than the first intermediate clock signal. The second shift register divider module is configured to produce at least one second phase clock signal based on the second intermediate clock signal, where the at least one second phase clock signal has a different frequency than the second intermediate clock signal. The multiplexer is configured to produce an output clock signal by selecting one of the first or second phase clock signals.

Abstract: A shift register includes a latch clock generation circuit and a clock latch circuit. The latch clock generation circuit generates a latch clock signal and an inverted latch clock signal based on a first internal clock signal, a first inverted internal clock signal, a second internal clock signal, and a second inverted internal clock signal. The clock latch circuit latches a control signal in synchronization with one signal selected from the first internal clock signal, the first inverted internal clock signal, the second internal clock signal, and the second inverted internal clock signal. The clock latch circuit also latches the latched control signal in synchronization with the latch clock signal or the inverted latch clock signal to generate and output a shift control signal.

Abstract: Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.

Abstract: A signal generation circuit includes a clock divider circuit, an off-pulse generation circuit, and an output signal generation circuit. The on-pulse generation circuit delays an input signal in synchronization with the first and second divided clock signals and generates an even on-pulse signal and an odd on-pulse signal. The off-pulse generation circuit delays the even on-pulse signal and the odd-on pulse signal in synchronization with the first divided clock signal and the second divided clock signal and generates a plurality of delay signals. The output signal generation circuit generates a first pre-output signal based on the delay signals delayed in synchronization with the first divided clock signal, generate a second pre-output signal based on the delay signals delayed in synchronization with the second divided clock signal, and generate an output signal based on the first and second pre-output signals.

Abstract: A circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch, and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level, the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includes a level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other of the first power supply voltage level or the second power supply voltage level.

Abstract: An active quadrature generation circuit configured to provide an in-phase output signal and a quadrature output signal based on an input signal and a method of fabricating the active quadrature generation circuit on an integrated circuit are described. The circuit includes an input node to receive the input signal and a first transistor including a collector connected to a power supply pin. The circuit also includes a second transistor including a base connected to the power supply pin, the second transistor differing in size from the first transistor by a factor of K, wherein the in-phase output signal and the quadrature output signal are generated based on an inherent phase difference of 90 degrees between a current at a collector of the first transistor and a current at a base of the second transistor.

Abstract: A continuous-time (CT) delta-sigma modulator (DSM) based analog to digital converter (ADC) in a radio receive chain supports a wide range of data rates in a power efficient way in a small die area. The ADC utilizes a 2nd order loop-filter with a single-amplifier loop-filter topology using a two stage Miller amplifier with a feed forward path and a push-pull output stage. High bandwidth operations utilize a “negative-R” compensation scheme at the amplifier input. Negative-R assistance is disabled for low data rate applications. With the negative-R assistance disabled, loop-filter resistor values are increased, instead of only the loop filter capacitor values to scale the noise transfer function (NTF), thereby limiting the capacitor area needed and enabling lower power operation. The NTF zero location is programmable allowing the NTF zero to be located near the intermediate frequency for different bandwidths to reduce the DSM quantization noise contribution for narrow-band (low data rate) applications.

Abstract: An oscillator circuit includes a phase-locked loop (PLL) with a plurality of voltage controlled oscillator (VCO), a clock divider circuit receiving the VCO phase outputs and outputting a first stage clock signal with an adjustable clock period related to the PLL period based on selecting a combination of two of the VCO phase outputs. The first stage clock signal has a balanced duty cycle at frequencies that are related to the PLL frequency by even fractional divisions of the VCO phase output period based on the quantity VCO phase outputs, and an unbalanced duty cycle at frequencies that are related by odd fractional divisions. A duty cycle adjustment (DCA) circuit receives the first stage clock signal selectively adjusts a falling edge of the first stage clock signal to provide an even duty cycle and feeds a resulting signal to the second stage clock signal output.

Abstract: A driving voltage provider includes: a PLL circuit for generating clock signals with different phases according to a divider value; a DC-DC converter for generating a PWM signal according to the frequency of a first clock signal, and providing a driving voltage based on the duty ratio of the PWM signal; a first tuning circuit for outputting a first tuning signal having a first logic level when the logic levels of first and second sampling signals obtained by sampling the PWM signal at transition times of different clock signals are different, and outputting the first tuning signal having a second logic level when the first and second sampling signals have the same logic level; and a divider value determiner for decreasing the divider value when the logic level of the first tuning signal is the first logic level.

Abstract: A device for phase adjustment preset for an N-path filter comprising a logic block; a ring divider array creating a local oscillator drive for a mixer; the ring divider array comprising: a plurality of registers, each comprising: inputs S, R, D, and clock, and output Q; the plurality of registers comprising at least: a first register; a second register; and an Nth register; a preset control word; wherein the preset control word is applied to the logic block, the logic block providing input to each of the S and the R inputs of each the register; whereby a desired starting phase of the divider is controlled. A method includes defining a desired starting conditions; determining a control word from desired starting conditions; applying control word to logic block; applying a reset signal to logic block; and outputting values for each of S and R to each register.

Abstract: Various example embodiments relate to unifying a plurality of parallel interfaces. A transmitting apparatus configured to serialize parallel bits implements a dynamic divider circuit for loading varying parallel bits into the transmitting apparatus. An input clock generator is configured to generate a desired and/or predefined clock frequency. The dynamic divider circuit receives the desired and/or predefined clock frequency and generates a parallel clock frequency by dividing the desired and/or predefined clock frequency based on a variable division input. Number of parallel bits loaded into the transmitting apparatus is based on the generated parallel clock frequency. Further, a shift register generates a bit stream from the parallel bits loaded into the shift register and the generated bit stream is converted to serial bit by a multiplexer.

Abstract: A negative voltage generation circuit includes a clock generation circuit configured to generate a first clock signal, a first voltage control circuit configured to vary a first resistance value based on a magnitude of a power supply voltage and further configured to control a magnitude of a voltage in a first charge node, based on the varied first resistance value, and a first charge pump circuit configured to charge a voltage, controlled by the first voltage control circuit, in a charge mode, based on the first clock signal, and further configured to output a first voltage, generated by the charging, as a first negative voltage.

Abstract: An apparatus includes a plurality of latches and a plurality of logic gates. Each latch may be setable and resettable. The logic gates may be connected to the latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal. Each latch may be commanded into a corresponding initial state while the command signal is in an initialization state. Each latch is generally free to change states while the command signal is in a run state. A modulus division operation of the multi-modulus divider may start upon an initial edge of the input clock signal after the command signal changes from the initialization state to the run state.

Abstract: A transmission system comprising: an output-terminal configured to provide an output-signal; a phase-shift oscillator comprising a plurality of phase-shifters, each configured to provide one of a plurality of phase-shifted-signals; and a controller configured to provide a selected one of the phase-shifted-signals to the output-signal as a transition in the output-signal, at an instant in time that is based on one or more of the plurality of phase-shifted-signals.

Abstract: A programmable divider is provided. The programmable divider includes a clock input coupled to receive a clock signal, a control input coupled to receive a first control signal, a counter compare block, and a load block. The counter compare block is configured to receive a first load value, update a counter with the first load value, provide a first output signal, and when the first control signal is at a first value, generate a first pulse in the first output signal when the counter reaches an end value. The load block is configured to receive a first divider value and provide the first load value based on a current counter value of the counter.

Abstract: A multi-modulus frequency divider circuit includes first and second frequency division stages. The first frequency division stage receives a first input clock signal having a first oscillating frequency, a first modulus input signal, and a first division bit. The first frequency division stage divides the first oscillating frequency by a first division ratio, and generates a second input clock signal having a second oscillating frequency. The second frequency division stage receives the second input clock signal, a second modulus input signal, and a second division bit. The second frequency division stage generates an output clock signal having an output oscillating frequency by dividing the second oscillating frequency by a second division ratio.

Abstract: A frequency divider circuit includes an oscillator comprising a plurality of delay elements coupled in series with each other, a first coupling circuit coupled to a first oscillator node and including a control terminal to receive a first retiming signal, and a first multiplexer including inputs coupled to receive the input signal and a complementary input signal, a control terminal coupled to a second oscillator node, and an output to provide the first retiming signal. The first multiplexer may be configured to alternate between injecting the input signal into the first oscillator node based on rising edges of the input signal and injecting the input signal into the first oscillator node based on falling edges of the input signal in response to a logic state of an oscillation waveform appearing at the second oscillator node.

Abstract: A frequency-modulated continuous-wave radar system includes a waveform generator, a delta-sigma modulation circuit, a voltage controlled oscillator, a frequency divider circuit, a control circuit, an injection locked oscillator, a power amplifier circuit, a first power detection circuit, a second power detection circuit, a third power detection circuit, and a calibration engine circuit. The waveform generator, the delta-sigma modulation circuit, the voltage controlled oscillator, the frequency divider circuit, and the control circuit form a phase locked loop.

Abstract: Switched adaptive clocking is provided. A switched adaptive clocking circuit includes a digitally controlled oscillator, a clock generator and a glitch-free multiplexer. The switched adaptive clocking circuit to adaptively switch a source of an output clock from a main clock generated by a clock source to a digitally controlled oscillator clock generated by a digitally controlled oscillator upon detection of a voltage droop, and to quickly switch back to the main clock after recovery from the voltage droop.

Abstract: A wireless access point device wirelessly communicates with a plurality of wireless client devices. The wireless access point includes a central processor subsystem and a plurality of transceiver devices each including a plurality of antennas, and a plurality of radio transceivers, each of the plurality of transceiver devices configured for deployment throughout a coverage area, each transceiver device being connected to the central processor subsystem via a respective cable. The central processor subsystem distributes in-phase and quadrature baseband samples across the plurality of transceiver devices associated with traffic to be transmitted and received via the plurality of transceiver devices in one or more frequency bands so as to synthesize a wideband multiple-input multiple-output transmission channel and a wideband multiple-input multiple-output reception channel. The access point transmit and receive functions are “split” or partitioned across the plurality of transceivers devices.

Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.

Abstract: An electronic device (20) has a clock path (24) for propagating a clock signal and a clock propagating element (26) on the clock path. An analogue element (30) coupled to the clock path (24) varies, in dependence on an analogue level of a first signal (32), a switching delay for the clock propagating element (26) to trigger a transition of the clock signal. The first signal is a digitally sampled signal. This provides a mechanism for providing a fast reduction in clock frequency even if the first signal is a metastable signal, which is useful for avoiding errors causes by voltage drops.

Abstract: A divider includes ? divider stages that may be turned off without toggling to extend the divide range of the divider while also reducing the impact of spurs on the divider output, and preserving the timing margin to update the divide ratio glitchlessly. A ? divider stage responds to an input enable signal being deasserted and a modulus input signal being asserted to remain in a disabled state in which the divider stage does not toggle by ensuring storage elements outputs in the divider stage remain constant. The divider further selects an update clock for the divide ratio of the divider utilizing an output from a most downstream stage that remains enabled.

Abstract: Various semiconductor chip clock signal pathways are disclosed. In one aspect, a semiconductor chip with a receiver includes a clock signals pathway for conveying plural clock phases in the receiver. The clock signals pathway includes plural wires in an arrangement that has a first edge, a second edge separated from the first edge and a midline between the first edge and the second edge. Each of the wires conveys a clock phase. The wires of the arrangement are routed so that, along a length of the clock signals pathway, each of the wires spends about the same percentage of time at or nearer the first edge or the second edge and at or nearer the midline.

Abstract: Clock signal control circuitry comprises a clock selector to output a current clock signal selected from two or more candidate clock signals and to execute a clock signal change operation to select a different one of the two or more candidate clock signals for output as the current clock signal; a counter to generate a count value by counting clock pulses of the current clock signal multiplied by a scaling value; and control logic to execute a scaling value change operation to change the scaling value in response to initiation of a clock signal change operation; in which the clock selector and the control logic are configured to cooperate to inhibit the output of the current clock signal during a scaling value change operation.

Abstract: A clock generating circuit includes a dividing unit and a distribution unit. The dividing unit divides a reference clock to generate a divided clock, and the divided clock has a frequency of 1/N times of a frequency of the reference clock, where N is an integer of two or more. The distribution unit distributes the reference clock to a first route and a second route, the first route includes an output terminal that outputs a clock with a frequency identical to the frequency of the reference clock, and the second route includes the dividing unit. The dividing unit includes one or more amplifiers, one or more dividing circuits, and a correction circuit. The correction circuit is disposed between the amplifier and the dividing circuit, and the correction circuit corrects a level of an input clock input to the dividing circuit.

Abstract: An apparatus includes a fractional divider and a modulator circuit. The fractional divider circuit may be configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal. The modulator circuit may be configured to generate the selection signal in response to the feedback clock signal. The fractional divider may generate four phase clock signals from the divided clock signal. The four phase clock signals may be interleaved by the fractional divider circuit to select one of the four phase clock signals as the feedback clock signal. The fractional divider operates at a divide-by-4 clock speed. The selection signal may be synchronized in response to the divided clock signal to generate the feedback clock signal. The fractional divider circuit may be implemented using CMOS logic.

Abstract: A Quadrature-In, Quadrature-Out (QIQO) clock divider divides by an odd divisor, such as three. An IQ input clock has in-phase and quadrature differential signals. Four stages of dynamic logic are arranged into a loop, with each stage output being one of four IQ output signals that have 90-degree phase separations. Each stage output drives the gates of a p-channel charging transistor and an n-channel discharging transistor of a next stage. Two p-channel charging logic transistors are in series between the next stage output and the p-channel charging transistor, and two n-channel evaluation transistors are in series between the next stage output and the n-channel discharging transistor. Different pairs of the four IQ input clock signals are applied to their gates. When the prior stage output is low, the stage output is charged. When the prior stage output is high, the stage output discharge timing is determined by the IQ signals.

Abstract: A clock generation circuit having a deskew function and a semiconductor integrated circuit device including the same are provided. The clock generation circuit includes a clock gating circuit configured to gate an input clock signal based on a first waveform signal to generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and to generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal having a period which is N times a period of the input clock signal.

Abstract: Disclosed is a linear feedback shift register (LFSR)-based clock signal generator that includes an LFSR, which outputs multi-bit states based on a system clock signal (CLK0). Based on the multi-bit states, a single-phase pulse generator generates first and second clock signals (CLK1 and CLK2), where the pulse rate of CLK1 is slower than that of the CLK0 and greater than that of CLK2. In some embodiments, a first multi-phase pulse generator can generate N-phases of the CLK1 based on CLK1 and N-phases of the CLK0 and a second multi-phase pulse generator can generate N-phases of CLK2 based on CLK2 and N-phases of CLK0. Furthermore, additional registers can optionally use the N-phases of CLK2 to further generate N sets of M-phases of the CLK2. Also disclosed are a multi-level circuit (e.g., a time domain-interleaved analog-to-digital converter (ADC)), which incorporates the LFSR-based clock signal generator, and associated methods.

Abstract: A divider circuit and method for generating one or more digital signals is presented. The circuit has a first output section for generating a first digital signal. There is a first output section with an output node to output the first digital signal, and a plurality of switches with one or more control switches. The plurality of switches selectively couple the output node to a first voltage and/or to selectively couple the output node to a second voltage, thereby generating the first digital signal. The or each control switch is prevents at least one of (i) the output node being coupled to the first and second voltages simultaneously and (ii) the output node being decoupled from both the first and second voltages simultaneously.

Abstract: A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.

Abstract: A signal processing circuit includes a clock generating circuit, a divider circuit, a converter, and an amplifier. The clock generating circuit outputs a first clock. The divider circuit divides the first clock to output a second clock having a frequency lower than a frequency of the first clock. The converter converts an input signal into a digital signal based on a first clock output from the clock generating circuit and a second clock output from the divider circuit. The amplifier, disposed between the clock generating circuit and the divider circuit, has a phase variation property opposite to a phase variation property of the divider circuit. The phase variation property of the divider circuit indicates a relationship between a phase variation amount of an output signal with respect to an input signal in the divider circuit and an ambient temperature of the divider circuit.

Abstract: An apparatus is disclosed for relocking of a locked loop. In an example aspect, the apparatus includes a locked loop, and the locked loop includes a loop and a locked-loop controller that is coupled to the loop. The loop is configured to run responsive to a run signal. The loop includes a memory state component and signal characteristic adjustment circuitry coupled to the memory state component. The signal characteristic adjustment circuitry is configured to produce an output signal having a characteristic that is based on the memory state component. The locked-loop controller is configured to receive an external power mode signal (EPMS). The locked-loop controller is also configured to generate the run signal to have an enable value at a first time when the EPMS is indicative of an external normal mode and at a second time when the EPMS is indicative of an external standby mode.

Abstract: An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) voltage converter coupled to the timebase generator. The timebase generator comprises a first linear feedback shift register (LFSR), a signal generator having an input coupled to an output of the first LFSR; and a digital divider comprising a second LFSR and a programmable digital divider, wherein a clock input of the programmable digital divider is coupled to an output of the signal generator, wherein an output of the programmable digital divider is coupled to a clock input of the first LFSR and is coupled to a clock input of the second LFSR, and wherein an output of the second LFSR is coupled to a program input of the programmable digital divider.

Abstract: A frequency division correction circuit includes: a first frequency divider configured to perform decimal frequency division on an input signal and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio; and a corrector configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.