Deglitch circuit removing glitches from input clock signal
An apparatus, method, and system for removing glitches from a clock signal, including a duty cycle lock loop (DCLL) circuit. A glitch, which may produce errors in the clock signal, may occur when a read channel transitions from an acquired clock signal to an adjusted clock signal. In one embodiment of the inventive deglitch circuit, a first capacitor is charged and discharged in response to an input clock signal, and an output clock signal is provided depending upon the first capacitor's voltage. The output clock signal further charges and discharges a second capacitor whose ratio of charge to discharge currents provides a signal to bias the discharge current of the first capacitor. A second DCLL circuit may be provided to restore the output clock signal duty cycle to the original clock signal duty cycle.
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1. Field of the Invention
This invention relates in general to the field of information storage, and more particularly to the acquisition of timing signals in a read channel.
2. Description of the Related Art
Many systems using digital data need to convert an analog signal to digital data for further use. Converting analog data to digital data may require a clock synchronized with the analog data.
Often, in data communication or transmission systems, data is formatted with timing information which may be retrieved in order to establish a clock that has the same frequency and phase offset as the data. The schematic block diagram shown in
Looking at this phenomenon in a little more detail, the interpolator 103 provides a reference clock based upon either CLK A or CLK B. The reference clock is high when the clock from which it is based is high. For example, if the transition occurs when CLK A is low and CLK B is high, the reference clock also goes high for the remainder of the CLK B cycle, thereby generating a glitch. Likewise, if the transition occurs when CLK A is high and CLK B is low, the reference clock also goes high for the remainder of the CLK A cycle, and once again, a glitch will result. If the transition occurs when CLK A and CLK B are both either high or low, no glitch is produced. A desired reference clock signal having a transition from CLK A to CLK B does not have pulses of short duration (glitches), but instead lengthens the cycle in which the transition occurs.
Therefore, a need exists for a circuit to remove glitches from a clock signal, to improve the operational reliability of subsequent circuits which depend on a stable clock signal.
SUMMARY OF THE INVENTIONTo address the stated need and fulfill other desired objectives, in accordance with one embodiment of the invention, a deglitch circuit provides a digital signal free of short unwanted pulses that may interfere with the timing of dependent circuits. In one embodiment, the deglitch circuit comprises a duty cycle lock loop (DCLL) circuit to remove glitches. If necessary, a second DCLL circuit may be provided to restore the input clock duty cycle, though this is not always necessary, particularly where the duty cycle resulting from the first DCLL is acceptable. The DCLL in the inventive deglitch circuit charges a first capacitor at a different rate than discharging the first capacitor in response to an input clock pulse, thereby creating a waveform having an amplitude proportional to the duration of the input clock pulse. An output clock pulse is generated when the amplitude of the waveform exceeds a predetermined threshold, and no pulse is generated when the amplitude fails to exceed the threshold. The output clock pulse may be of a different period than the input clock pulse. The rate of discharge of the first capacitor depends upon the ratio of a second capacitor charge and discharge currents.
Referring now to
CLK1 is the input to inverter 405, which produces a signal CLK2. Inverter 405 changes state when CLK1 falls below a predetermined threshold, and CLK2 has a duty cycle that is determined by the charging and discharging rates of capacitor 407. CLK2 controls the charging and discharging currents to capacitor 408, thereby producing the voltage Vout that is used to bias transistor 403 for controlling the discharge rate of capacitor 407.
CLK2 controls the charging time of capacitor 408 by controlling transistors 411 and 412. Transistor 411 switches on when CLK2 is high, thereby allowing current source 409 to charge capacitor 410. When CLK2 is low, transistor 411 switches off and transistor 412 switches on, allowing capacitor 408 to discharge at a rate determined by current source 410. Each current source 409, 410 may be adjusted to provide a controllable charging or discharging current. The ratio of charging current to discharging current determines the duty cycle of CLK2. For example, a charging current of 4i and a discharging current of i will produce a 20-80 duty cycle in which CLK2 is high for ⅕ of a cycle and low for ⅘ of a cycle. This duty cycle is controllable depending upon the ratio of charging to discharging currents of capacitor 408.
Referring now to
Because the interpolator 203 is configured to provide a reference clock that has a maximum offset of π/2 to the adjusted clock, the maximum duration of a glitch is t/4. Referring to
The present invention is applicable in a variety of areas, essentially, to any application in which glitches in input clock signals are problematic. One such area is in the field of information storage, including hard disk drive systems (HDD).
In an HDD, data is recorded on magnetic media in tracks, each track having a plurality of sectors. A sector comprises a preamble (for acquiring timing signals), timing bits, a position error field, address bits, data bits, and error correction bits. A read channel uses the preamble to recover the frequency of the recorded data, and creates a clock signal having the same frequency and phase offset as the original data. The present invention, which provides a circuit for a deglitched clock signal synchronized to the data, is applicable to outputting read channels for HDDs. However, as noted, the invention also is applicable wherever a synchronized clock is required to convert or acquire data.
Therefore, the foregoing is illustrative only of the principles of the invention. Further, those skilled in the art will recognize that numerous modifications and changes are possible. The disclosure of the foregoing embodiments does not limit the invention to the exact construction and operation shown. Accordingly, all suitable modifications and equivalents fall within the scope of the invention.
Claims
1. A deglitch circuit for removing glitches from an input clock signal, said circuit comprising:
- an input circuit receiving the input clock signal and providing a charging current and a discharging current;
- an inverter providing an output clock signal, wherein the inverter changes state when a voltage related to the discharging current falls below a predetermined threshold, so as to remove glitches from the input clock signal; and
- a further circuit receiving the output clock signal and including a capacitor having a capacitor charging current equal to a capacitor discharging current so that the output clock signal has the same duty cycle as the input clock signal.
2. A deglitch circuit for removing glitches from an input clock signal, said circuit comprising:
- input means receiving the input clock signal and providing a charging current and a discharging current;
- inverter means providing an output clock signal, wherein the inverter means changes state when a voltage related to the discharging current exceeds a predetermined threshold, so as to remove glitches from the input clock signal; and
- further circuit means receiving the output clock signal and restoring a duty cycle of the input clock signal.
3. The deglitch circuit of claim 2, wherein the further circuit means includes capacitor means having a capacitor charging current equal to a capacitor discharging current to provide an output clock signal having the same duty cycle as the input clock signal.
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Type: Grant
Filed: Jan 5, 2004
Date of Patent: Nov 27, 2012
Assignee: Marvell International Ltd. (Hamilton)
Inventors: Chi Fung Cheng (San Jose, CA), Pantas Sutardja (San Jose, CA)
Primary Examiner: Kenneth B. Wells
Application Number: 10/752,785
International Classification: G01R 29/02 (20060101);