Patents Examined by Kenneth B. Wells
  • Patent number: 10693477
    Abstract: An oscillator subsystem included in a phase-locked loop circuit of a computer system may include coarse and fine-tuning circuits. The coarse-tuning circuit may generate a coarse-tuning current based on a reference voltage, and the fine-tuning circuit may generate a fine-tuning current by combining respective currents generated by first and second complement current mirror circuits using a voltage level of a control signal. An oscillator circuit may generate a clock signal whose frequency is based on a combination of the coarse and fine-tuning circuits.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 23, 2020
    Assignee: Apple Inc.
    Inventor: Cristian Marcu
  • Patent number: 10693481
    Abstract: A time-to-digital converter includes N stages of converting circuits, where N2, and N is an integer. Each stage of the converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of the converting circuit outputs a delayed signal of the stage of the converting circuit; and the arbiter in each stage of the converting circuit receives a sampling clock and the delayed signal of the stage of the converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of the converting circuit. The first delayer in each stage of the converting circuit includes at least one first delay cell circuit with a first time unit. The first delayer in any stage of the converting circuit includes a less number of first delay cell circuits than the first delayer in a next stage of the converting circuit.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: June 23, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hao Yan, Jiale Huang, Lei Lu
  • Patent number: 10680627
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang
  • Patent number: 10680614
    Abstract: The present document describes a level-shifter circuit and method to transmit data from a high-voltage domain to a low-voltage domain. The level-shifter circuit has a first current path with a first current control unit to set a first current based on a high-voltage data signal in the high-voltage domain; and a second current path with a second current control unit to set a second current based on the high-voltage data signal. Furthermore, the circuit has an isolation unit to transfer the first current and the second current from the high-voltage domain to the low-voltage domain; and a current comparator unit to compare the first current with the second current to provide a low-voltage data signal in the low-voltage domain, which corresponds to the high-voltage data signal.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: June 9, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Horst Knoedgen, Nebojsa Jelaca, Christoph N. Nagl
  • Patent number: 10680601
    Abstract: A controller circuit for controlling an insulated-gate bipolar transistor (IGBT) is configured to, in response to an IGBT turn off switching event, switch out a first switching element to prevent a pull-up signal from flowing to a gate of the IGBT, switch in a second switching element to create a channel to permit a first pull-down signal to flow to the gate of the IGBT, and switch in a third switching element to create a channel to permit a second pull-down signal to flow to the gate of the IGBT. In response to determining a collector to emitter voltage at the IGBT does not satisfy a threshold, the controller circuit is configured to switch out the third switching element to prevent the second pull-down signal from flowing to the gate of the IGBT.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies AG
    Inventor: Asantha Kempitiya
  • Patent number: 10680590
    Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: June 9, 2020
    Assignee: pSemi Corporation
    Inventors: Jianhua Lu, Naveen Yanduru, Edward Nicholas Comfoltey, Michael Conry, Chieh-Kai Yang
  • Patent number: 10663996
    Abstract: There is provided a constant current circuit having a current characteristic satisfactory in a high voltage circuit while being low in manufacturing cost. The constant current circuit includes a high breakdown-voltage depletion type NMOS transistor and a low breakdown-voltage depletion type NMOS transistor connected in series between a first terminal and a second terminal. The low breakdown-voltage depletion type NMOS transistor includes a first depletion type NMOS transistor and a second depletion type NMOS transistor connected in series. The high breakdown-voltage depletion type NMOS transistor has a gate connected to a connecting point of the first depletion type NMOS transistor and the second depletion type NMOS transistor.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: May 26, 2020
    Assignee: ABLIC INC.
    Inventors: Takashi Matsuda, Fumihiko Maetani
  • Patent number: 10664001
    Abstract: A circuit includes a first transistor that conducts a first current responsive to a DC bias voltage and an RF signal. A second transistor conducts a second current responsive to the DC bias voltage. The first current and the second current are mirrored through a pair of current mirrors coupled together through a low-pass filter to filter the envelope of the RF signal.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: May 26, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Mohamed Abouzied, Rajagopalan Rangarajan, Peter Shah
  • Patent number: 10659010
    Abstract: An RF driver circuit may include a wideband output impedance matching and gain circuit, a wideband input impedance matching and gain circuit, and a summer configured to sum the outputs of the wideband output impedance matching and gain circuit and wideband input impedance matching and gain circuit. The wideband output impedance matching and gain circuit and wideband input impedance matching and gain circuit may collectively provide the gain of the RF driver circuit. The wideband output impedance matching circuit may have a source follower configuration. The wideband input impedance matching circuit may have a common gate configuration. Controllable bias voltages may be used to maintain a constant gain and interface impedances in multiple modes of operation.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: May 19, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Chirag Dipak Patel, Lai Kan Leung, Ravi Sridhara
  • Patent number: 10659041
    Abstract: A circuit for controlling an anode-gate thyristor includes a first transistor that couples a thyristor gate to a first terminal to receive a potential lower than a potential of a second terminal connected to the thyristor anode. A control terminal of the first transistor is driven by a control signal which is positive with respect to the potential of the first terminal.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: May 19, 2020
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Ghafour Benabdelaziz, Romain Pichon
  • Patent number: 10651829
    Abstract: A signal receiver circuit includes: a negative voltage applier suitable for applying a negative voltage to a common source node in response to a first clock is at a first logic level; a first sampling transistor coupled between the common source node and a first sampling node to sink a current from the first sampling node to the common source node in response to a first input signal; a second sampling transistor coupled between the common source node and a second sampling node to sink a current from the second sampling node to the common source node in response to a second input signal; an equalizer suitable for equalizing the first sampling node and the second sampling node in response to the first clock is at a second logic level; a precharger suitable for precharging a first output node and a second output node with a pull-up voltage in response to a second clock is at the first logic level, and electrically coupling the first output node and second output node to the second sampling node and the first sam
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 12, 2020
    Assignee: SK hynix Inc.
    Inventor: Min-Chang Kim
  • Patent number: 10651810
    Abstract: A number of field effect transistor circuits include voltage controlled attenuators or voltage controlled processing circuits. Example circuits include modulators, lower distortion variable voltage controlled resistors, sine wave to triangle wave converters, and or servo controlled biasing circuits.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: May 12, 2020
    Inventor: Ronald Quan
  • Patent number: 10643678
    Abstract: A clock generation circuit, which generates an output clock using an external clock as a target clock, includes a circuit arranged to change the output clock to high level in synchronization with an up edge of the target clock, circuits arranged to generate first and second ramp voltages with a period of interval between neighboring up edges of the target clock, and a circuit arranged to hold a comparison voltage corresponding to a second ramp voltage when an up edge of the target clock occurs. The level of the output clock is changed from high level to low level based on a comparison result between the first ramp voltage and the comparison voltage.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: May 5, 2020
    Assignee: Rohm Co., Ltd.
    Inventors: Takehiro Yoshida, Shun Fukushima
  • Patent number: 10637354
    Abstract: A multi-channel power system and a method of controlling a phase shift of the same are provided. The multi-channel power system includes one or more first DC to DC converters and one or more second DC to DC converters. The first DC-DC converter outputs a first pulse width modulated signal having a first default frequency. When the first DC-DC converter receives a reference clock signal, it outputs the first pulse width modulated signal having a frequency that is the same as that of the reference clock signal. The first DC-DC converter outputs a phase-shifted clock signal having a preset phase shift relative to the first pulse width modulated signal. The second DC-DC converter outputs a second pulse width modulated signal having a second default frequency. The second DC-DC converter outputs the second pulse width modulated signal having the preset phase shift according to the phase shift clock signal.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: April 28, 2020
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Tse-Hsu Wu, Yun-Chiang Chang, Fu-Chuan Chen
  • Patent number: 10627838
    Abstract: A system includes a monitored component and a comparator configured to compare a sense voltage from the monitored component with a reference voltage. The system also includes an adaptive input clamping circuit configured to limit the sense voltage input to the comparator to below an upper threshold voltage.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 21, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Mitsuyori Saito
  • Patent number: 10630239
    Abstract: In certain aspects, an apparatus includes a plurality of phase generators configured to generate a first plurality of local oscillator (LO) phase signals, wherein the plurality of phase generators includes a first set of phase generators and a second set of phase generators. The apparatus also includes a duty cycle generator coupled to the plurality of phase generators, wherein the duty cycle generator is configured to receive the first plurality of LO phase signals and to generate a second plurality of LO phase signals by converting a duty cycle of each of the first plurality of LO phase signals. The first set of phase generators is located adjacent to a first side of the duty cycle generator and the second set of phase generators is located adjacent to a second side of the duty cycle generator, the second side being opposite the first side.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: April 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Ayush Mittal, Gajanan Maroti Devpuje, Krishnaswamy Thiagarajan, Bhushan Shanti Asuri
  • Patent number: 10630181
    Abstract: The present disclosure provides a semiconductor chip power supply system, including: a semiconductor chip including: a first data processing function area and a first power converter control area, the first data processing function area and the first power converter control area being formed on a first semiconductor substrate of the semiconductor chip; and a first power converter power stage located outside the first semiconductor substrate and electrically connected to the first power converter control area and the first data processing function area; wherein the first power converter control area controls the first power converter power stage to supply power to the first data processing function area.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: April 21, 2020
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Jianhong Zeng, Haoyi Ye, Xiaoni Xin, Siyu He, Xinjian Zou
  • Patent number: 10630267
    Abstract: An oscillator circuit including a ring oscillator and a reference current source is provided. The ring oscillator includes an odd number of inverter stages. Each inverter stage includes a first transistor having a first reference threshold that varies over temperature. The reference current source is configured to generate a plurality of currents, where a respective current is applied directly to the drain of a respective first transistor of a respective inverter stage. The reference current source includes a reference transistor that has a second reference threshold that varies over temperature; a resistor coupled between a gate and a source of the reference transistor; a second transistor having a source coupled to the gate of the reference transistor for generating a reference current that flows through the resistor to regulate a voltage of the resistor to the second threshold voltage; and a current mirror configured to generate the plurality of currents.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: April 21, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Giovanni Carlo Tripoli, Cecilia Teresa Rita Gatti, Paul Georges Marie Rose, Roberto Faravelli
  • Patent number: 10630280
    Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: April 21, 2020
    Assignee: pSemi Corporation
    Inventors: Simon Edward Willard, Tero Tapio Ranta
  • Patent number: 10630263
    Abstract: A resonator circuit has first to sixth transconductance units and the first to fourth connectors. The first transconductance unit has the first top, bottom, and control terminals. The second transconductance unit has the second top terminal connected to the first bottom terminal and has the second bottom and control terminals. The third transconductance unit has a third top terminal connected to the first top terminal and has the third bottom and control terminals. The fourth transconductance unit has the fourth top, bottom, and control terminals. The fifth transconductance unit has the fifth top terminal connected to the fourth bottom terminal and has the fifth bottom and control terminals. The sixth transconductance unit has the sixth top terminal connected to the fourth top terminal and has the sixth bottom and control terminals.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: April 21, 2020
    Inventor: Takashi Miki