Abstract: A circuit assembly for cooling a quantum electrical device, use of said circuit assembly, a system and a method for cooling a quantum electric device are provided. The circuit assembly comprises a quantum electric device to be cooled, at least one normal-metal-insulator-superconductor (NIS) tunnel junction electrically connected to the quantum electric device and at least one superconductive lead for supplying a drive voltage VQCR for said at least one NIS tunnel junction. The quantum electric device is cooled when the voltage VQCR is supplied to at least one NIS tunnel junction, said voltage VQCR being equal to or below the voltage N?/e, where N=1 or N=2, N is the number of NIS tunnel junctions electrically coupled in series with the means for generating the voltage, ? is the energy gap in the superconductor density of states, and e is the elementary charge.

Abstract: A circuit assembly for cooling a quantum electrical device, use of said circuit assembly, a system and a method for cooling a quantum electric device are provided. The circuit assembly comprises a quantum electric device to be cooled, at least one normal-metal-insulator-superconductor (NIS) tunnel junction electrically connected to the quantum electric device and at least one superconductive lead for supplying a drive voltage VQCR for said at least one NIS tunnel junction. The quantum electric device is cooled when the voltage VQCR is supplied to at least one NIS tunnel junction, said voltage VQCR being equal to or below the voltage N?/e, where N=1 or N=2, N is the number of NIS tunnel junctions electrically coupled in series with the means for generating the voltage, ? is the energy gap in the superconductor density of states, and e is the elementary charge.

Abstract: A duty cycle measuring circuit, the circuit comprising a synchronizer and a measurer, the synchronizer arranged such that when a signal to be measured comprising pulses having a pulse width and a pulse period is input to the synchronizer, synchronizing signals corresponding to each of pulse rising edge, pulse falling edge, pulse period start and pulse period end are output from the synchronizer, each synchronizing signal comprising a rising or falling edge, wherein the synchronizing signal outputs from the synchronizer are input to the measurer, and wherein the measurer is arranged to provide two measurement outputs based on the synchronizing signal inputs from the synchronizer, the measurement outputs comprising a first measurement output signal indicative of a pulse period measurement of the signal to be measured and a second measurement output signal indicative of a pulse width measurement of the signal to be measured.

Abstract: A clock generator that generates an output clock signal, includes a clock generating circuit that generates an internal clock signal, first and second filter circuits, and an output gate. The first filter circuit receives the internal clock signal and an enable signal, and provides a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the clock signal. The second filter circuit receives the first filtered enable signal, provides a second filtered enable signal in response to the first filtered enable signal, and provides a delayed signal that is a delayed version of the second filtered enable signal. The output gate receives the internal clock signal from the clock generating circuit and the second filtered enable signal from the second filter circuit, and generates the output clock signal.

Abstract: A device having a memory configured to store information indicating debounce times for the device's switches and having circuits configured to determine whether the switches are depressed and closed based on the debounce times. The debounce times are updated based on the age of the device and/or switch usage. The method for debouncing may be performed by a computer having computer-readable media directed to adjusting the debounce times based on the age of the device containing the switches.

Abstract: A clock filter filtering a glitch of an input clock to generate an output clock is provided. A first delay circuit inverts the input clock to generate an inverted clock and delays the inverted clock to generate a first processing clock. A second delay circuit delays the input clock to generate a second processing clock. A first setting circuit generates a reset clock according to the inverted clock and the first processing clock. A second setting circuit generates a set clock according to the input clock and the second processing clock. When the set clock changes from a first level to a second level, a third setting circuit sets the output clock at the second level. When the reset clock changes from the first level to the second level, the third setting circuit sets the output clock to the first level.

Abstract: In some aspects, a mesoscopic system is used to generate entanglement, for example, on a pair of qubits. In some implementations, the mesoscopic system includes a first spin, a second spin and multiple other spins. The initial state of the first and second spins can be separable (non-entangled) states. Measurement outcomes are obtained by performing projective measurements on the mesoscopic system. Based on the measurement outcomes, an entangled state of the first and second spins is detected. The entangled state is transferred from the first and second spins to the first and second qubits.

Abstract: According to one embodiment, a synchronous semiconductor device is disclosed According to this embodiment, the synchronous semiconductor device includes a pulse width detection circuit to determine whether at least one of a plurality of delay step sizes is less than at least one of a high pulse width and a low pulse width of a first clock signal and to select one of the delay step sizes and a delay line to delay the first clock signal to produce as second clock signal by a first delay amount that is changed based at least on the one of the delay step sizes.

Abstract: A transition glitch suppression circuit can be used to remove unwanted glitches occurring within a time delay of the rising edge or falling edge of a signal. The transition glitch suppression circuit has a delay element that can delay the input signal by the time delay to generate a delayed input signal. The transition glitch suppression circuit also has first and second logic circuits that process the input signal and the delayed input signal to generate corresponding outputs. A multiplexer provides the output signal for the suppression circuit by selecting between the output of the first logic circuit and the output of the second logic circuit based on the value of the output signal.

Abstract: A glitch filter circuit has a filter/delay part that always operates on rising or falling pulses for both rising edges and falling edges of the input signal. In this way, the filter delay can be made symmetrical and the circuit will have no duty cycle distortion. The rise and fall delays will track each other when there are PVT (Process, Voltage and Temperature) variations.

Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.

Abstract: A system includes an ADC that, based on a first clock signal, converts an analog signal into a digital signal. A first circuit generates a second clock signal based on the digital signal. An interpolator generates a phase delayed version of the second clock signal and a third clock signal. The third clock signal is generated based on the second clock signal and the phase delayed version and includes transitioning from the second clock signal to the phase delayed version. The third clock signal includes pulses each having a first pulse width and a pulse having a second pulse width. The second pulse width is different than the first pulse width due to the transition from the second clock signal to the third clock signal. A second circuit removes the pulse having the second pulse width from the third clock signal to generate the first clock signal.

Abstract: A noise removal circuit is provided having a first holding circuit (20) and a second holding circuit (22) which holds a value of an input signal (IN) at a plurality of different timings in synchronization with rising and falling of an internal clock signal (ICL) generated within a semiconductor device, and which removes noise of the input signal (IN) according to the held value.

Abstract: An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.

Abstract: This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation with high noise immunity. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and to generate a first output signal. The circuit also includes a second buffer configured to receive the incoming signal and to generate a second output signal. The second buffer exhibits hysteresis with lower and upper thresholds. The circuit also includes an output block configured to receive the first and second output signals and to generate a third output signal. The output block is configured to switch a logic state of the third output signal in response to a transition of a logic state of the first output signal, and to lock the logic state of the third output signal until the output block receives a transition of a logic state of the second output signal.

Abstract: A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.

Abstract: Disclosed is a deglitcher circuit having a programmable hysteresis. The deglitcher samples a received input signal, wherein the input signal may include one or more glitches. Responsive to a change in state of the sampled input signal, the deglitcher counts the number of samples of the changed state of the input signal. The count value increments with each sampled changed state, and decrements with each sampled original state of the input signal. When the count value reaches a threshold, the state of the output signal is changed. The output signal of the disclosed deglitcher circuit provides an accurate, glitch-free reconstruction of the sampled input signal. Additionally, the disclosed deglitcher circuit reduces the number of memory elements required for a given number of samples of the input signal, thereby allowing for a larger number of samples to be taken without necessarily having to increase the memory elements required by the deglitcher.

Abstract: An electric circuit includes a delayed clock generation circuit to which a first clock is supplied and which is configured to generate a first delayed clock and a second delayed clock, the first delayed clock being the first clock delayed by a first delay amount, and the second delayed clock being the first clock delayed by a second delay amount different from the first delay amount, an OR gate configured to receive the first clock, the first delayed clock, and the second delayed clock as inputs and to output a second clock, and a scan circuit to which the second clock is supplied.

Abstract: This disclosure provides examples of circuits, devices, systems, and methods for providing high speed operation and a high noise margin. In one implementation, a circuit includes a first buffer configured to receive an incoming signal and a control signal and to generate an output signal based on the incoming signal. The first buffer exhibits a first hysteresis range while configured in a first hysteresis state and a second hysteresis range while configured in a second hysteresis state. The first buffer is configured to transition from the first to the second hysteresis state and vice versa in response to the control signal. The circuit includes a second buffer configured to receive the incoming signal and to generate the control signal based on the incoming signal. The second buffer exhibits a third hysteresis range with a lower threshold and an upper threshold.

Abstract: Structures and methods are provided for reducing or eliminating crosstalk in devices. Based on a predetermined compensation schemes, a compensation scheme is selected that minimizes the deviation of the non-aggressed victim signal caused by one or more aggressor signals. Instances of a compensation circuit corresponding to the selected compensation scheme are placed along a victim signal line at locations defined by the compensation scheme.

Abstract: A distributed, reconfigurable statistical signal processing apparatus comprises an array of discrete-time analog signal processing circuitry for statistical signal processing based on a local message-passing algorithm and digital configuration circuitry for controlling the functional behavior of the array of analog circuitry. The input signal to the apparatus may be expressed as a probabilistic representation. The analog circuitry may comprise computational elements arranged in a network, with a receiving module that assigns probability values when an input signal arrives and communicates the probability values to one of the computational elements, the computational elements producing outputs based on the assigned probability values. The signal processing apparatus may be an analog logic automata cell or an array of cells, wherein each cell is able to communicate with all neighboring cells.

Abstract: A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.

Abstract: A glitch filter circuit has a filter/delay part that always operates on rising or falling pulses for both rising edges and falling edges of the input signal. In this way, the filter delay can be made symmetrical and the circuit will have no duty cycle distortion. The rise and fall delays will track each other when there are PVT (Process, Voltage and Temperature) variations.

Abstract: A method for reducing spurious for a clock distribution system, the method including a) providing a system controller, b) providing clock distribution system, c) inputting characteristics of the clock distribution system in advance of operation thereof, d) calculating an expected level of the integer boundary spurious as a function of a fractional offset value, e) selecting an integer boundary solution based on the fractional offset value being within a preferred predetermined region, and f) programming the master clock subsystem and the one or more fractional synthesizers with the integer boundary solution, and g) repeating steps d) through f) as needed.

Abstract: The present invention relates a pulse width filter generating a modulation signal that is increased in synchronization with one of an increasing edge and a decreasing edge of the input signal and is decreased in synchronization with the other of the increasing edge and the decreasing edge, and transmitting the input signal of the modulation signal. The input signal passed through the filter unit is inverted thereby being an output signal. The pulse width filter controls the increasing and the decreasing of the modulation signal according to the output signal and the input signal passed through the filter unit, and the modulation signal is a signal to determined whether the pulse width of the input signal is more than the predetermined cut-off pulse width.

Abstract: A debounce apparatus and a method thereof are provided, which includes a debounce module, a register and a timer. The debounce module receives an input signal and eliminates a bounce phenomenon of the input signal within a transient-time of the state-changing of the input signal to produce a debounce signal. The register outputs an output signal according to the value stored in the register. When the input signal changes its state, the timer starts time-counting according to a counting-value of settling-time; when the debounce signal changes its state, the timer recounts time; and when time-counting is ended and when the value corresponding to the debounce signal is different from the register's value, the register's value is updated by the value corresponding to the debounce signal. In this way, the apparatus can eliminate the system misjudgement problem caused by occurred voltage level errors in the stable state.

Abstract: A data channel circuit including an analog to digital converter, a timing loop control circuit, an interpolator circuit, and a deglitch circuit. The analog to digital converter is configured to convert an analog input signal into a corresponding digital signal in accordance with a reference clock signal received from a timing loop. The timing loop control circuit is configured to receive the digital signal from the analog to digital converter, and generate a first clock signal based on the digital signal. The interpolator circuit is configured to receive the first clock signal, and generate a second clock signal based on the first clock signal, and the first clock signal delayed by a predetermined phase delay. The second clock signal has first glitches. The deglitch circuit is configured to, based on the second clock signal, generate the reference clock signal. The reference clock signal does not include the first glitches.

Abstract: A digital glitch filter for filtering glitches in an input signal includes first and second flip-flops and a synchronizer. The synchronizer includes third and fourth flip-flops. A glitch prone input signal is provided to the first and second flip-flops. Additionally, an input clock signal is provided to the first and second flip-flops and the synchronizer. A glitch occurring in the input signal toggles the first and second flip-flops between transmitting and non-transmitting states and first and second intermediate signals are generated. The synchronizer synchronizes the first and second intermediate signals with the input clock signal to generate a filtered output signal.

Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract: A circuit and method for debouncing an electrical signal are disclosed. A representative embodiment of the present invention may be set to remove (i.e., filter) noise or glitches in the low and high portions of an input signal, where the width of the noise or glitches while in the high or low state may be set using a programming interface. The filtering is done in a manner that results in a clean, debounced output signal having a low portion approximately equal to the low portion of the input signal, and a high portion approximately equal to the high portion of the input signal. Noise or glitches of less than programmable high or low glitch widths are filtered from the input signal and do not appear in the output signal.

Abstract: A filter circuit includes a plurality of shifting units configured to each store an initial value, receive at least one input signal, and shift the stored value to a next shifting unit in sequence from among the shifting units in response to at least one input signal, and an initial value setting unit configured to set the initial stored values of the shifting units to different sets of initial stored values in response to different filter setting signals, respectively, wherein the different filter setting signals represent respectively different criteria for filtering the at least one input signal, wherein the initially stored values have a first logic value or a second logic value, wherein the filter circuit is configured to activate an output signal when the first logic value is shifted to a selected shifting unit among the plurality of shifting units.

Abstract: A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element.

Abstract: Noise reduction circuit includes first and second reset signal generation circuits generating first and second reset signals activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high or low level is maintained, and first and second counter circuits that count an inverted signal of clock signal and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit including a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock. The selector circuit selects and outputs any of: signal fixed at a high level or low level, and output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit.

Abstract: An apparatus, method, and system for removing glitches from a clock signal, including a duty cycle lock loop (DCLL) circuit. A glitch, which may produce errors in the clock signal, may occur when a read channel transitions from an acquired clock signal to an adjusted clock signal. In one embodiment of the inventive deglitch circuit, a first capacitor is charged and discharged in response to an input clock signal, and an output clock signal is provided depending upon the first capacitor's voltage. The output clock signal further charges and discharges a second capacitor whose ratio of charge to discharge currents provides a signal to bias the discharge current of the first capacitor. A second DCLL circuit may be provided to restore the output clock signal duty cycle to the original clock signal duty cycle.

Abstract: A narrow pulse filter is disclosed. The narrow pulse filter includes a first tri-state inverter. The narrow pulse filter further includes a pulse generator coupled to the first tri-state inverter. The pulse generator is configured to cause the first tri-state inverter to enter a high-impedance state to filter out a narrow pulse from a signal input to the first tri-state inverter.

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: Noise reduction circuit includes first and second reset signal generation circuits generating first and second reset signals activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high or low level is maintained, and first and second counter circuits that count an inverted signal of clock signal and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit including a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock. The selector circuit selects and outputs any of: signal fixed at a high level or low level, and output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit.

Abstract: A diode-laser having an elongated diode-laser emitter is mounted on a relatively massive heat-sink. Two parallel grooves are machined into the heat-sink to leave a relatively narrow elongated ridge of the heat-sink between the grooves. The ridge has a width about equal to or narrower that the width of the emitter. The diode-laser is mounted on the heat-sink such that thermal communication between the emitter and heat-sink is essentially limited to thermal communication with the ridge.

Abstract: The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.

Abstract: Disclosed is a deglitcher circuit having a programmable hysteresis. The deglitcher samples a received input signal, wherein the input signal may include one or more glitches. Responsive to a change in state of the sampled input signal, the deglitcher counts the number of samples of the changed state of the input signal. The count value increments with each sampled changed state, and decrements with each sampled original state of the input signal. When the count value reaches a threshold, the state of the output signal is changed. The output signal of the disclosed deglitcher circuit provides an accurate, glitch-free reconstruction of the sampled input signal. Additionally, the disclosed deglitcher circuit reduces the number of memory elements required for a given number of samples of the input signal, thereby allowing for a larger number of samples to be taken without necessarily having to increase the memory elements required by the deglitcher.

Abstract: A noise reduction circuit includes first and second reset signal generation circuits that generate first and second reset signals that are activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high level or a low level is maintained, and first and second counter circuits that count an inverted signal of the clock signal, and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit that includes a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock, wherein the selector circuit selects and outputs any of: a signal fixed at a high level or a low level, and an output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit.

Abstract: A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement.

Abstract: The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.

Abstract: The present invention relates a pulse width filter generating a modulation signal that is increased in synchronization with one of an increasing edge and a decreasing edge of the input signal and is decreased in synchronization with the other of the increasing edge and the decreasing edge, and transmitting the input signal of the modulation signal. The input signal passed through the filter unit is inverted thereby being an output signal. The pulse width filter controls the increasing and the decreasing of the modulation signal according to the output signal and the input signal passed through the filter unit, and the modulation signal is a signal to determined whether the pulse width of the input signal is more than the predetermined cut-off pulse width.

Abstract: A filter cut-off frequency correction circuit, inputted with a step function increasing from a first voltage to a second voltage, comprises a linear passive filter, for integrating the step function to obtain a third voltage; a first comparator, outputting a first high-level signal when the third voltage is greater than a first predetermined reference voltage; a second comparator, outputting a second high-level signal in a first period from the time that the second voltage is applied to the time that the first comparator outputs the first high-level signal; a counter, for counting a number of clock pulses of a reference clock inputted in the first period; a digital block, for calculating a variation rate of time constant according to the number of clock pulses of the reference clock, and generating a correction code; and a filter, for correcting the cut-off frequency according to the correction code. The correction circuit can improve the speed of cut-off frequency adjustment.

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: A filtering module filters out high frequency signals, primarily noise, from an input data stream. The filtering module includes an input module, a phase detecting module, and a threshold module. The input module performs either a charging or a discharging across a capacitor on a basis of an RC time constant. The phase detecting module is coupled to the input module to keep identical phase at a first node and an output node. The threshold module is coupled to the phase detecting module for providing an output signal based on a threshold voltage and the charging or the discharging across the capacitor.

Abstract: A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Abstract: There is provided a spike noise eliminating circuit that can eliminate reliably spike noise having a predetermined pulse width or smaller and transmit and output precisely a signal having a pulse width larger than the predetermined width. Spike noise in the input signal is eliminated by: detecting a coincidence in level of the input signal and a first delay signal obtained by delaying the input signal by a maximum pulse width of noise to be eliminated as a delay amount; and sampling the input signal or a second delay signal obtained by delaying the input signal by a certain period of time based on a signal obtained as a result of detecting the coincidence in level.