ESD protection circuit
An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line.
Latest MediaTek Inc. Patents:
- AI frame engine for mobile edge
- Multiplexing of physical sidelink control channel (PSCCH) and physical sidelink shared channel (PSSCH)
- ESD PROTECTION CIRCUIT FOR NEGATIVE VOLTAGE OPERATION
- WIRELESS SENSING METHOD FOR REQUESTING PHASE REPORT FROM SENSING RESPONDER AND SENDING REQUESTED PHASE REPORT TO SENSING INITIATOR AND RELATED WIRELESS COMMUNICATION DEVICE
- VIOLATION CHECKING METHOD BY MACHINE LEARNING BASED CLASSIFIER
This application claims the benefit of U.S. Provisional Application No. 61/557,553, filed on Nov. 9, 2011, and U.S. Provisional Application No. 61/595,956, filed on Feb. 7, 2012, the entireties of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to an ESD protection circuit with high power supply rejection ratio (PSRR).
2. Description of the Related Art
An electrostatic discharge (ESD) event is an important reliability issue for integrated circuits (ICs). To meet component-level ESD reliability, on-chip ESD protection circuits are implemented in the input/output (I/O) cells and power/ground cells of complementary metal-oxide semiconductor (CMOS) ICs.
With the continued miniaturization of IC devices, the current trend in the sub-micron CMOS technology is to produce integrated circuits with shallower junction depths, thinner gate oxides, lightly-doped drain (LDD) structures, shallow trench isolation structures, and silicide processes. However, the advanced IC devices also become more susceptible to ESD damage. ESD phenomenon occurs when excess charges are transmitted from the I/O pin to the integrated circuit too quickly, which damages the internal circuit. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits of the IC against ESD damage.
BRIEF SUMMARY OF THE INVENTIONElectrostatic discharge (ESD) protection circuits are provided. An embodiment of an ESD protection circuit is provided. The ESD protection circuit comprises an impedance device coupled between a pad and a power line, and a first clamp unit coupled between the pad and a ground line.
Furthermore, another embodiment of an ESD protection circuit is provided. The ESD protection circuit comprises: a first resistor coupled to a power line; a first clamp unit coupled between the first resistor and a ground line; a second clamp unit coupled between the first resistor and a pad; a third clamp unit coupled between the pad and the ground line; and a bias unit coupled to the pad. The second clamp unit conducts an ESD current caused by positive voltage ESD pulses from the pad to the first clamp unit. The third clamp unit conducts an ESD current by negative voltage ESD pulses from the ground line to the pad. The bias unit provides a bias voltage at the pad.
Moreover, another embodiment of an ESD protection circuit is provided. The ESD protection circuit comprises: an inductor coupled between a power line and a pad; a first clamp unit coupled between the pad and a ground line; a first resister coupled between the pad and the first clamp unit; and a second clamp unit coupled in parallel with the first resister. The second clamp unit conducts an ESD current caused by positive voltage ESD pulses from the pad to the first clamp unit.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1. An electrostatic discharge (ESD) protection circuit, comprising:
- a first resistor coupled between a pad and a power line, avoiding swing voltage of signal at the pad influencing power voltage of the power line; and
- a first clamp unit coupled between the pad and a ground line,
- wherein the first resistor is not on a discharging path.
2. The ESD protection circuit as claimed in claim 1, further comprising:
- a second clamp unit coupled between the pad and the first resistor, conducting an ESD current caused by positive voltage ESD pulses from the pad to the first clamp unit; and
- a third clamp unit coupled between the pad and the ground line, conducting an ESD current by negative voltage ESD pulses from the ground line to the pad.
3. The ESD protection circuit as claimed in claim 2, wherein the first resistor is a high impedance resistor.
4. The ESD protection circuit as claimed in claim 2, wherein the second clamp unit comprises at least one diode coupled in a forward conduction direction from the pad to the first clamp unit, and the third clamp unit comprises at least one diode coupled in a forward conduction direction from the ground line to the pad.
5. The ESD protection circuit as claimed in claim 2, wherein the second clamp unit comprises at least one PMOS transistor, and the third clamp unit comprises at least one NMOS transistor.
6. The ESD protection circuit as claimed in claim 1, wherein the first clamp unit comprises:
- a first NMOS transistor coupled between the first resistor and the ground line;
- a first PMOS transistor coupled between the first resistor and a gate of the first NMOS transistor;
- a second NMOS transistor coupled between the gate of the first NMOS transistor and the ground line, having a gate coupled to a gate of the first PMOS transistor;
- a second resistor coupled between the first resistor and the gate of the first PMOS transistor; and
- a capacitor coupled between the gate of the first PMOS transistor and the ground line.
7. The ESD protection circuit as claimed in claim 6, wherein the capacitor is formed by a third NMOS transistor, wherein the third NMOS transistor has a gate coupled to the gate of the first PMOS transistor, a drain coupled to the ground line and a source coupled to the ground line.
8. An electrostatic discharge (ESD) protection circuit, comprising:
- a first resistor having a first end coupled to a power line, and a second end coupled to a pad, avoiding swing voltage of signal at the pad influencing power voltage of the power line, wherein the first resistor is not on a discharging path;
- a first clamp unit coupled between the second end of the first resistor and a ground line;
- a second clamp unit coupled between the first resistor and the pad, conducting an ESD current caused by positive voltage ESD pulses from the pad to the first clamp unit;
- a third clamp unit coupled between the pad and the ground line, conducting an ESD current by negative voltage ESD pulses from the ground line to the pad; and
- a bias unit coupled to the pad, providing a bias voltage at the pad.
9. The ESD protection circuit as claimed in claim 8, wherein the bias unit comprises:
- a second resistor coupled in parallel with the second clamp unit.
10. The ESD protection circuit as claimed in claim 8, wherein the bias unit comprises:
- a third resistor coupled between the power line and the pad; and
- a fourth resistor coupled between the pad and the ground line, wherein the bias voltage is determined according to the third and fourth resistors.
11. The ESD protection circuit as claimed in claim 10, wherein the bias unit further comprises:
- a current mirror unit coupled between the power line and the third resistor, providing a bias current to the third resistor,
- wherein the bias voltage is determined according to the third resistor and the bias current.
12. The ESD protection circuit as claimed in claim 8, wherein the first resistor has a high resistance.
13. The ESD protection circuit as claimed in claim 8, wherein the second clamp unit comprises at least one diode coupled in a forward conduction direction from the pad to the first clamp unit, and the third clamp unit comprises at least one diode coupled in a forward conduction direction from the ground line to the pad.
14. The ESD protection circuit as claimed in claim 8, wherein the second clamp unit comprises at least one PMOS transistor, and the third clamp unit comprises at least one NMOS transistor.
15. The ESD protection circuit as claimed in claim 8, wherein the first clamp unit comprises:
- a first NMOS transistor coupled between the impedance device and the ground line;
- a first PMOS transistor coupled between the impedance device and a gate of the first NMOS transistor;
- a second NMOS transistor coupled between the gate of the first NMOS transistor and the ground line, having a gate coupled to a gate of the first PMOS transistor;
- a fifth resistor coupled between the impedance device and the gate of the first PMOS transistor; and
- a capacitor coupled between the gate of the first PMOS transistor and the ground line.
16. The ESD protection circuit as claimed in claim 15, wherein the capacitor is formed by a third NMOS transistor, wherein the third NMOS transistor has a gate coupled to the gate of the first PMOS transistor, a drain coupled to the ground line and a source coupled to the ground line.
17. An electrostatic discharge (ESD) protection circuit, comprising:
- an inductor coupled between a power line and a pad;
- a first clamp unit coupled between the pad and a ground line;
- a first resister coupled between the pad and the first clamp unit; and
- a second clamp unit coupled in parallel with the first resister, conducting an ESD current caused by positive voltage ESD pulses from the pad to the first clamp unit.
18. The ESD protection circuit as claimed in claim 17, further comprising:
- a third clamp unit coupled between the pad and the ground line, conducting an ESD current by negative voltage ESD pulses from the ground line to the pad.
19. The ESD protection circuit as claimed in claim 18, wherein the second clamp unit comprises at least one diode coupled in a forward conduction direction from the pad to the first clamp unit, and the third clamp unit comprises at least one diode coupled in a forward conduction direction from the ground line to the pad.
20. The ESD protection circuit as claimed in claim 18, wherein the second clamp unit comprises at least one PMOS transistor, and the third clamp unit comprises at least one NMOS transistor.
21. The ESD protection circuit as claimed in claim 17, wherein the first clamp unit comprises:
- a first NMOS transistor coupled between the impedance device and the ground line;
- a first PMOS transistor coupled between the impedance device and a gate of the first NMOS transistor;
- a second NMOS transistor coupled between the gate of the first NMOS transistor and the ground line, having a gate coupled to a gate of the first PMOS transistor;
- a second resistor coupled between the impedance device and the gate of the first PMOS transistor; and
- a capacitor coupled between the gate of the first PMOS transistor and the ground line.
22. The ESD protection circuit as claimed in claim 21, wherein the capacitor is formed by a third NMOS transistor, wherein the third NMOS transistor has a gate coupled to the gate of the first PMOS transistor, a drain coupled to the ground line and a source coupled to the ground line.
Type: Grant
Filed: Oct 29, 2012
Date of Patent: Mar 3, 2015
Patent Publication Number: 20130114172
Assignee: MediaTek Inc. (Hsin-Chu)
Inventors: Bo-Shih Huang (Hsinchu), Tsung-Ming Chen (Zhubei), Yuan-Hung Chung (Zhubei)
Primary Examiner: Dharti Patel
Application Number: 13/662,851
International Classification: H01C 7/12 (20060101); H02H 1/00 (20060101); H02H 1/04 (20060101); H02H 3/22 (20060101); H02H 9/06 (20060101); H02H 3/20 (20060101); H02H 9/04 (20060101);