Arrangement for energy conditioning

- X2Y Attenuators, LLC

Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences.

Skip to: Description  ·  Claims  ·  References Cited  · Patent History  ·  Patent History
Description
CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 13/195,495, filed Aug. 1, 2011, which is a continuation of application Ser. No. 13/079,789, filed Apr. 4, 2011, now issued as U.S. Pat. No. 8,023,241, which is a continuation of application Ser. No. 12/749,040, filed Mar. 29, 2010, now issued as U.S. Pat. No. 7,920,367, which is a continuation of application Ser. No. 12/030,253, filed Feb. 13, 2008, now issued as U.S. Pat. No. 7,688,565, which is a continuation of application Ser. No. 10/479,506, filed Dec. 10, 2003, now issued as U.S. Pat. No. 7,336,468, which is a U.S. National Stage Application of International Application PCT/US02/21238, filed Jul. 2, 2002, which is a continuation-in-part of application Ser. No. 10/023,467, filed Dec. 17, 2001, now abandoned, which is a continuation-in-part of application Ser. No. 09/996,355, filed Nov. 29, 2001, now abandoned, which is a continuation-in-part of application Ser. No. 10/003,711, filed Nov. 15, 2001, now abandoned, which is a continuation-in-part of application Ser. No. 09/982,553, filed Oct. 17, 2001, now abandoned;

and this application is a continuation of application Ser. No. 13/195,495, filed Aug. 1, 2011, which is a continuation of application Ser. No. 13/079,789, filed Apr. 4, 2011, now issued as U.S. Pat. No. 8,023,241, which is a continuation of application Ser. No. 12/749,040, filed Mar. 29, 2010, now issued as U.S. Pat. No. 7,920,367, which is a continuation of application Ser. No. 12/030,253, filed Feb. 13, 2008, now issued as U.S. Pat. No. 7,688,565, which is a continuation of application Ser. No. 10/479,506, filed Dec. 10, 2003, now issued as U.S. Pat. No. 7,336,468, which is a continuation-in-part of application Ser. No. 10/115,159, filed Apr. 2, 2002, now issued as U.S. Pat. No. 6,894,884, which is a continuation-in-part of application Ser. No. 09/845,680, filed Apr. 30, 2001, now issued as U.S. Pat. No. 6,580,595, which is a continuation-in-part of application Ser. No. 09/777,021, filed Feb. 5, 2001, now issued as U.S. Pat. No. 6,687,108, which is a continuation-in-part of application Ser. No. 09/632,048, filed Aug. 3, 2000, now issued as U.S. Pat. No. 6,738,249, which is a continuation-in-part of application Ser. No. 09/594,447, filed Jun. 15, 2000, now issued as U.S. Pat. No. 6,636,406, which is a continuation-in-part of application Ser. No. 09/579,606, filed May 26, 2000, now issued as U.S. Pat. No. 6,373,673, which is a continuation-in-part of application Ser. No. 09/460,218, filed Dec. 13, 1999, now issued as U.S. Pat. No. 6,331,926, which is a continuation of application Ser. No. 09/056,379, filed Apr. 7, 1998, now issued as U.S. Pat. No. 6,018,448, which is a continuation-in-part of application Ser. No. 09/008,769, filed Jan. 19, 1998, now issued as U.S. Pat. No. 6,097,581, which is a continuation-in-part of application Ser. No. 08/841,940, filed Apr. 8, 1997, now issued as U.S. Pat. No. 5,909,350;

and application Ser. No. 10/115,159 claims the benefit of provisional Application No. 60/280,819, filed Apr. 2, 2001, provisional Application No. 60/302,429, filed Jul. 2, 2001, provisional Application No. 60/310,962, filed Aug. 8, 2001;

and application Ser. No. 09/845,680 claims the benefit of provisional Application No. 60/200,327, filed Apr. 28, 2000, provisional Application No. 60/215,314, filed Jun. 30, 2000, provisional Application No. 60/225,497, filed Aug. 15, 2000, provisional Application No. 60/255,818, filed Dec. 15, 2000;

and application Ser. No. 09/777,021 claims the benefit of provisional Application No. 60/180,101, filed Feb. 3, 2000, provisional Application No. 60/185,320, filed Feb. 28, 2000, provisional Application No. 60/191,196, filed Mar. 22, 2000, provisional Application No. 60/200,327, filed Apr. 28, 2000, provisional Application No. 60/203,863, filed May 12, 2000, provisional Application No. 60/215,314, filed Jun. 30, 2000, provisional Application No. 60/225,497, filed Aug. 15, 2000, provisional Application No. 60/241,128, filed Oct. 17, 2000, provisional Application No. 60/248,914, filed Nov. 15, 2000, provisional Application No. 60/252,766, filed Nov. 22, 2000, provisional Application No. 60/253,793, filed Nov. 29, 2000, provisional Application 60/255,818, filed Dec. 15, 2000;

and application Ser. No. 09/632,048 claims the benefit of provisional Application No. 60/146,987, filed Aug. 3, 1999, provisional Application No. 60/165,035, filed Nov. 12, 1999, provisional Application No. 60/180,101, filed Feb. 3, 2000, provisional Application No. 60/185,320, filed Feb. 28, 2000, provisional Application No. 60/191,196, filed Mar. 22, 2000, provisional Application No. 60/200,327, filed Apr. 28, 2000, provisional Application No. 60/203,863, filed May 12, 2000, provisional Application No. 60/215,314, filed Jun. 30, 2000;

and application Ser. No. 09/594,447 claims the benefit of provisional Application No. 60/139,182, filed Jun. 15, 1999, provisional Application No. 60/146,987, filed Aug. 3, 1999, provisional Application No. 60/165,035, filed Nov. 12, 1999, provisional Application No. 60/180,101, filed Feb. 3, 2000, provisional Application No. 60/185,320, filed Feb. 28, 2000, provisional Application No. 60/191,196, filed Mar. 22, 2000, provisional Application No. 60/200,327, filed Apr. 28, 2000, provisional Application No. 60/203,863, filed May 12, 2000;

and application Ser. No. 09/579,606 claims the benefit of provisional Application No. 60/136,451, filed May 28, 1999, provisional Application No. 60/139,182, filed Jun. 15, 1999, provisional Application No. 60/146,987, filed Aug. 3, 1999, provisional Application No. 60/165,035, filed Nov. 12, 1999, provisional Application No. 60/180,101, filed Feb. 3, 2000, provisional Application No. 60/185,320, filed Feb. 28, 2000, provisional Application No. 60/200,327, filed Apr. 28, 2000, provisional Application No. 60/203,863, filed May 12, 2000;

and application Ser. No. 10/023,467 claims the benefit of provisional Application No. 60/255,818, filed Dec. 15, 2000, provisional Application No. 60/280,819, filed Apr. 2, 2001, provisional Application No. 60/302,429, filed Jul. 2, 2001, provisional Application No. 60/310,962, filed Aug. 8, 2001;

and application Ser. No. 09/982,553 claims the benefit of provisional Application No. 60/241,128, filed Oct. 17, 2000;

and application Ser. No. 09/996,355 claims the benefit of provisional Application No. 60/253,793, filed Nov. 29, 2000, provisional Application No. 60/255,818, filed Dec. 15, 2000, provisional Application No. 60/280,819, filed Apr. 2, 2001, provisional Application No. 60/302,429, filed Jul. 2, 2001, provisional Application No. 60/310,962, filed Aug. 8, 2001;

and application Ser. No. 10/003,711 claims the benefit of provisional Application No. 60/248,914, filed Nov. 15, 2000, provisional Application No. 60/252,766, filed Nov. 22, 2000, provisional Application No. 60/253,793, filed Nov. 29, 2000, provisional Application No. 60/255,818, filed Dec. 15, 2000, provisional Application No. 60/280,819, filed Apr. 2, 2001, provisional Application No. 60/302,429, filed Jul. 2, 2001, and provisional Application No. 60/310,962, filed Aug. 8, 2001;

and PCT application No. PCT/US02/21238 claims the benefit under 35 U.S.C. 119(e) of provisional Application No. 60/302,429, filed Jul. 2, 2001, provisional Application No. 60/310,962, filed Aug. 8, 2001, provisional Application No. 60/388,388, filed Jun. 12, 2002.

This application incorporates by reference the disclosure of grandparent application Ser. No. 13/079,789, which is a continuation of application Ser. No. 12/749,040, which is a continuation of application Ser. No. 12/030,253, which is a continuation of application Ser. No. 10/479,506, which is a U.S. national stage entry of PCT application No. PCT/US02/21238, filed Jul. 2, 2002, which is continuation-in-part of co-pending application Ser. No. 10/023,467, filed Dec. 17, 2001, which is a continuation-in-part of co-pending application Ser. No. 09/996,355, filed Nov. 29, 2001, which is a continuation-in-part of co-pending application Ser. No. 10/003,711, filed Nov. 15, 2001, which is a continuation-in-part of co-pending application Ser. No. 09/982,553, filed Oct. 17, 2001, each of which is incorporated by reference herein.

In addition, grandparent application Ser. No. 10/479,506 claims the benefit of provisional Application No. 60/302,429, filed Jul. 2, 2001, provisional Application No. 60/310,962, filed Aug. 8, 2001, provisional Application No. 60/349,954, filed Jan. 8, 2002, and provisional Application No. 60/388,388, filed Jun. 12, 2002, each of which is incorporated by reference herein.

TECHNICAL FIELD

This application relates to balanced shielding arrangements that use complementary relative groupings of energy pathways, such as pathways for various energy propagations for multiple energy conditioning functions. These shielding arrangements may be operable as discrete or non-discrete embodiments that can sustain and condition electrically complementary energy confluences.

BACKGROUND OF THE INVENTION

Today, as the density of electronics within applications increases, unwanted noise byproducts of the increased density may limit the performance electronic circuitry.

Consequently, the avoidance of the effects of unwanted noise byproducts, such as by isolation or immunization of circuits against the effects of the undesirable noise is an important consideration for circuit arrangements and circuit design.

Differential and common mode noise energy may be generated by, and may propagate along or around, energy pathways, cables, circuit board tracks or traces, high-speed transmission lines, and/or bus line pathways. These energy conductors may act as, for example, an antenna that radiates energy fields. This antenna-analogous performance may exacerbate the noise problem in that, at higher frequencies, propagating energy utilizing prior art passive devices may experience increased levels of energy parasitic interference, such as various capacitive and/or inductive parasitics.

These increases may be due, in part, to the combination of constraints resulting from functionally or structurally limitations of prior art solutions, coupled with the inherent manufacturing or design imbalances and performance deficiencies of the prior art. These deficiencies inherently create, or induce, unwanted and unbalanced interference energy that may couple into associated electrical circuitry, thereby making at least partial shielding from these parasitics and electromagnetic interference desirable. Consequently, for broad frequency operating environments, solving these problems necessitates at least a combination of simultaneous filtration, careful systems layout having various grounding or anti-noise arrangements, as well as extensive isolating in combination with at least partial electrostatic and electromagnetic shielding.

BRIEF SUMMARY OF THE INVENTION

Thus, a need exists for a self-contained, energy-conditioning arrangement utilizing simplified energy pathway arrangements, which may additionally include other elements, amalgamated into a discrete or non-discrete component, which may be utilized in almost any circuit application for providing effective, symmetrically balanced, and sustainable, simultaneous energy conditioning functions selected from at least a decoupling function, transient suppression function, noise cancellation function, energy blocking function, and energy suppression functions.

BRIEF DESCRIPTION OF THE DRAWINGS

Understanding of the present invention will be facilitated by consideration of the following detailed description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which like numerals refer to like parts and in which:

FIG. 1 is a relative location compass operable for determining relative locations of the various pathway extensions disclosed;

FIGS. 1A-1C show relative locations of the various pathway extensions disclosed according to an aspect of the present invention;

FIG. 2A shows a circuit schematic of the plan view of an embodiment of 2B according to an aspect of the present invention;

FIG. 2B is a plan view of an embodiment according to an aspect of the present invention;

FIG. 3A shows a circuit schematic of the plan view of an embodiment of 3B according to an aspect of the present invention;

FIG. 3B is a plan view of an embodiment according to an aspect of the present invention;

FIG. 3C shows a plan view of a shield according to an aspect of the present invention;

FIG. 4A shows a relative plan view of an embodiment according to an aspect of the present invention;

FIG. 4B shows a relative plan view of an embodiment according to an aspect of the present invention;

FIG. 4C shows a relative plan view of an embodiment according to an aspect of the present invention;

FIG. 4D shows a relative plan view of an embodiment according to an aspect of the present invention;

FIG. 4E shows a relative plan view of an embodiment according to an aspect of the present invention;

FIG. 4F shows a relative plan view of an embodiment according to an aspect of the present invention;

FIG. 4G shows a relative plan view of an embodiment according to an aspect of the present invention;

FIG. 4H shows a relative plan view of an embodiment according to an aspect of the present invention;

FIG. 4I shows a relative plan view of an embodiment according to an aspect of the present invention;

FIG. 5A shows a stacked multiple, circuit network including groups of pathways according to an aspect of the present invention;

FIG. 5B shows a stacked shield according to an aspect of the present invention;

FIG. 5C shows a relative plan view of a stacked multiple, non-shared circuit network having VIAs including groups of pathways according to an aspect of the present invention;

FIG. 6 shows a relative plan view of circuit arrangement variant according to an aspect of the present invention; and,

FIG. 7 shows a relative plan view of circuit arrangement variant according to an aspect of the present invention.

 DETAILED DESCRIPTION OF THE INVENTION

It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for the purpose of clarity, many other elements found in typical energy conditioning systems and methods. Those of ordinary skill in the art will recognize that other elements and/or steps are desirable and/or required in implementing the present invention. However, because such elements and steps are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements and steps is not provided herein. The disclosure herein is directed to all such variations and modifications to such elements and methods known to those skilled in the art.

Additionally, it will be apparent to those skilled in the art that terms used herein that may include a whole, or a portion of a whole, such as “energy”, “system”, circuit, and the like, are contemplated to include both the portions of the whole, and the entire of the whole, as used, unless otherwise noted.

As used herein, an “energy pathway” or “pathway” may be at least one, or a number, of conductive materials, each one operable for sustained propagation of energy. Pathways may be conductive, thereby better propagating various electrical energies as compared to non-conductive or semi-conductive materials directly or indirectly coupled to, or adjacent to, the pathways. An energy pathway may facilitate propagation of a first energy by allowing for various energy conditioning functions, such as conditioning functions arising due to any one or a number of aspects, such as, but not limited to, the shielding, the orientation and/or the positioning of the energy pathways within the energy pathway arrangement, which various arrangements having an orientation and/or positioning thereby allow for interaction of the first energy with propagating energies that are complementary to at least the first energy. An energy pathway may include an energy pathway portion, an entire energy pathway, a conductor, an energy conductor, an electrode, at least one process-created conductor, and/or a shield. A plurality of energy pathways may include a plurality of each device or element discussed hereinabove with respect to energy pathway. Further, as used generally herein, a conductor may include, for example, an individual conductive material portion, a conductive plane, a conductive pathway, a pathway, an electrical wire, a via, an aperture, a conductive portion such as a resistive lead, a conductive material portion, or an electrical plate, such as plates separated by at least one medium 801, for example.

A shield may include a shielding electrode, a shielding pathway portion, a shielded pathway, a shielded conductor, a shielded energy conductor, a shielded electrode, and/or at least one process-created shielded pathway portion. A plurality of shields may include a plurality of the devices discussed hereinabove with respect to a shield.

As used generally herein, a pathway may be complementary positioned, or complementary orientated, with respect to a main-body 80,81, having various pathway extensions, designated 79“X”, 812“X”, 811“X” and 99“X”. Main-bodies 80, 81 may be in three-dimensional physical relationships individually, in pairs, groups, and/or pluralities as to distance, orientation, position, superposition, non-superposition, alignment, partial alignment, lapping, non-lapping, and partial lapping. Superposed main-body pathway 80, may, for example include a pairing of physically opposing and oppositely orientated main-body pathways 80 that are any one of, or any combination of, electrically null, electrically complementary, electrically differential, or electrically opposite.

A pathway arrangement may include at least a shield at least partially shielding at least one energy pathway, or a group of shields forming a shield structure that at least partially shielding, via a conductive shielding, at least a conductively isolated pairing of at least two energy pathways, such as vias, apertures or complementary paired pathways.

An exemplary embodiment may allow energy propagation on a conductively isolated pairing, such as complementary paired pathways, causing energy propagation on common shields, or at least one grouping of shields, serving an isolated circuit. This embodiment may allow a low inductance pathway to form among at least a single pair of isolated and separate parallel pathways serving at least one separate and distinct isolated circuit system. An exemplary embodiment may allow for the development of at least a low inductance pathway for utilization of energy propagating on at least one parallel pathway of at least two sets of isolated and separate parallel pathways and the development along at least one parallel pathway of at least one other low inductance pathway for utilization of energy propagating along at least one other separate and distinct isolated circuit system.

An exemplary embodiment utilized as part of a circuit assembly may have at least one pathway of relatively lower inductance, while other pathways may be electrically coupled to an energy source or an energy load. A pathway of a second plurality of pathways may have a lower impedance operable for portions of energy to be taken away from either of the same at least one energy source or at least one energy load of the circuit assembly. This same pathway of low impedance may not be electrically directly coupled to either the same at least one energy source or at least one energy load of the circuit assembly as the one pathway of lower inductance. A system may have both a pathway of least inductance and a pathway of least impedance which are not the same pathway.

In contrast to capacitors found in the industry wherein an equivalent series inductance (ESL) of a capacitor device is normally size dependant, in the present invention the pathway of least impedance and the pathway of least inductance for a circuit for energy conditioning may be achieved independent of the physical size of the device. These aspects depend on a predetermined capacitance developed by a predetermined layers in the present invention.

Arranging the pathways allows the resistance of the conductive material of the pathways to primarily determine the energy delivery, or relative efficiency or effect between at least one source of energy and one energy utilizing load of an integrated circuit, for example.

The ESL may be a negligible factor, rather than a primary factor for delivery outcome or decoupling void of debilitating inductances.

In an illustrative pathway arrangement illustrated in FIGS. 1A, 1B, 1C, 5A and 5B, wherein the various propagating energies may be complementary, the pathway arrangement, upon placement into a circuit arrangement, may allow for energy propagation within or along certain energy pathways of the pathway arrangement, thereby allowing for the mutual interaction of opposite portions of pathway-sourced magnetic fields produced by the propagation of energy field currents emanating outwardly from each set of the complementary conductors. This mutual interaction may be a mutual cancellation in embodiments wherein certain pathways may be partially or totally physically shielded from other complementary pathways, and may be placed within an influencing distance of those other complementary pathways. Further, a substantial similarity in size and shape of the respective complementary pathways, including the spaced-apart relationship and the interpositioning of a shielding between pathways, and the conductively isolated relationship of the pathways, may contribute to this mutual cancellation effect. Additionally, the shielding operations may be predicated on a relative positioning of a mating of the paired pathways relative to the conductive electrostatic shielding. At least the complementary energy conditioning functions and electrostatic shielding dynamics discussed herein may operate on various energy propagating in various directions along various predetermined pathways, and may operate on circuits having dynamic operation utilizing the pathway arrangement.

A sub-combination of electromagnetically/electrostatically actuated impedance states may develop along or within a pathway arrangement, or along or within a closely coupled external conductive portion conductively coupled to separate or multiple groupings of shields, to thereby form an energy conditioning circuit. These electromagnetically/electrostatically actuated impedance states may develop, for example, because of the energization of one paired set of pathways of one circuit portion, but not necessarily develop on another paired set of pathways from another circuit portion, for example.

According to an aspect of the present invention, each shield may include a main-body 81. Main-bodies 81 may collectively and conductively couple to one another and at the same time may substantially immure and shield the main-body 80 of the energy pathways. In other embodiments of the present invention, the collective shielding main-body 81 may only partially immure or shield the pathway main-body 80s in at least one portion of the shielding.

According to an aspect of the present invention, a balanced, symmetrical, pathway arrangement may result from the symmetry of certain superposed shields, from complementary pathway sizing and shaping, and/or from reciprocal positioning and pairing of the complementary pathways. Manufacturable balanced or symmetrical physical arrangements of pathways, wherein dynamic energy propagation, interactions, pairings or match-ups of various dynamic quantities occur, may operate at less than a fundamental limit of accuracy of testing equipment. Thus, when portions of these complementary energy quantities interact simultaneously, the energy may be beyond the quantifiable range of the typical testing equipment. Thus, the extent to which the measurement may be obtained may employ increased controllability, and thereby the electrical characteristics and the effect on electrical characteristics may be controlled, such as by predetermining the desired measurability, behavior or enhancement to be provided, and by a correspondent arrangement of the elements, such as specifically by an arrangement of the elements to provide the desired measurability or effect. For example, a desired electrical characteristic may be predetermined for a desired enhancement by varying at least a portion of the complementary balance, size, shape, and symmetry of at least one pathway pairing, as set forth herein below and as illustrated in FIGS. 1A, 1B, 1C, 5A and 5B, for example.

Thus, the extent of energy interactions, mutual energy propagation timings and interferences, for example, may be controlled by tolerances within the pathway arrangement.

A manufacturing process, or computer tolerance control, such as semiconductor process control, may control these tolerances, for example. Thus, the pathways of an embodiment may be formed using manufacturing processes, such as passive device processes, apparent to those skilled in the art. Mutual energy propagation measurements may thereby be cancelled or suppressed by the formation, and process of formation, of the pathway arrangement.

A pathway arrangement may, as set forth hereinabove, include a sequentially positioned grouping of pathways in an amalgamated electronic structure having balanced groupings of pathways. The balanced grouping may include a predetermined pathway architecture having a stacked hierarchy of pathways that are symmetrical and complementary in number, and that are positioned complementary to one another, thereby forming pairs, each of which pair is substantially equidistant from each side of a centrally positioned shield, wherein each shield may provide a symmetrical balancing point for both each pair pathway and the overall pathway hierarchy as depicted in FIGS. 1A to 4I, for example. Thus, predetermined identically sized, shaped and complementary positioned pathways may be present on either side of a centrally positioned shield for each separate circuit portion. A total circuit may have its complementary portions symmetrically divided into a complementary physical format including a reverse-mirror image positioning of paired shielded, complementary sized and shaped pathways, sandwiching at least one interposing shield.

According to an aspect of the present invention, each pathway may be, for example, a first interconnect substrate wrapping around, or holding, an integrated circuit wafer, a deposit, an etching, or a resultant of a doping process, and the shield may be, for example, a pathway substrate, an energy conditioning embodiment or energy conditioning substrate, a deposit, an etching, a resultant of a doping process, and may have, for example, resistive properties.

Additional elements may be utilized, including conductive and nonconductive elements, between the various pathways. These additional elements may take the form of ferromagnetic materials or ferromagnetic-like dielectric layers, and/or inductive-ferrite dielectric derivative materials. Additional pathway structural elements may be utilized, including conductive and nonconductive multiple pathways of different conductive material compositions, conductive magnetic field-influencing material hybrids and conductive polymer sheets, various processed conductive and nonconductive laminates, straight conductive deposits, multiple shielding pathways utilizing various types of magnetic material shields and selective shielding, and conductively doped and conductively deposited on the materials and termination solder, for example, in addition to various combinations of material and structural elements, to provide a host of energy conditioning options.

Non-conductor materials may also provide structural support of the various pathways, and these non-conductor materials may aid the overall energized circuit in maintaining the simultaneous, constant and uninterrupted energy propagation moving along the pathways.

Dielectric materials for example, may include one or more layers of material elements compatible with available processing technology. These dielectric materials may be a semiconductor material such as silicon, germanium, gallium arsenide, or a semi-insulating and insulating material such as, but not limited to any K, high K and low K dielectrics.

Pathway and conductor materials may be selected from a group consisting of Ag, Ag/Pd, Cu, Ni, Pt, Au, Pd and other such conductive materials and metals. Combinations of these metal materials are suitable for the purposes discussed herein, and may include appropriate metal oxides, such as ruthenium oxide, which, depending on the exigencies of a particular application, may be diluted with a suitable metal. Other pathways may be formed of a substantially non-resistive conductive material. Any substances and processes that may create pathways from conductive, non-conductive, semi-conductive material, and/or Mylar films printed circuit board materials, or any substances or processes that may create conductive areas such as doped polysilicons, sintered polycrystallines, metals, polysilicon silicates, or polysilicon silicide may be used within or with the pathway arrangement.

An exemplary embodiment of the present invention may utilize an internal shield structural architecture to insure energy balancing configurations within the various arrangements, rather than a specific external circuit balance. This balancing configuration is dependent upon the relative positioning of all the shields in relationship to the shared and centrally positioned shield, and the actual paired shields positioned in specific quantities, to simultaneously provide shielding for the electrically opposing shielded paired pathways utilized by propagating energy. This allows these electrically opposing complementary pathways to be located both electrically and physically on the opposite sides of the centrally positioned and shared common conductive shield. This interposition of the central and shared shields may create a voltage divider that divides various circuit voltages in half and that provides, to each of the oppositely paired shielded conductors, one half of the voltage energy normally expected. The energized circuitry, including shielded conductors, may be balanced electrically or in a charge-opposing manner and with respect to a centrally positioned shield, to a common and shared pathway, or to each respective, isolated circuit system portion.

Each common circuit member of an isolated circuit system may be attached or coupled to a common area or common pathway, thereby providing an external common zero voltage.

Thus, the embodiment may have multiple sets of shields electrically or physically located between at least one of the various electrically or charge opposing, shielded pairs or grouped complementary pairs of pathways in an interposed shielding relationship, supported with additional outer sandwiching shields, designated herein as -IM that are additionally coupled and, in part, form the shielding structure.

An exemplary embodiment may also be placed into one or more energy circuits that utilize different energy sources and that may supply one or more separate and distinct energy-utilizing loads. When energized for multiple energy conditioning operations and for providing simultaneous and effective energy conditioning functions, such as electromagnetic interference filtering, suppression, energy decoupling and energy surge protection, each separate and distinct circuit is utilizing the multiple commonly shared universal shield structure and circuit reference image, or node.

According to an aspect of the present invention, energy-conditioning functions may maintain an apparent balanced energy voltage reference and energy supply for each respective energy-utilizing load within a circuit. This energized arrangement may allow for specific energy propagation utilizing a single, or multiple, isolated pathway arrangement, and may not require balancing on a single, centralized shield. A shield may be physically and electrically located between one or multiple energy sources and one or multiple energy utilizing loads, depending upon the number of separate and isolated pathways. Thus shielding relative, centralized pathways may be in both co-planar and stacked variants of exemplary embodiment.

When the internally positioned paired shielded pathways are subsequently attached, or conductively coupled, to externally manufactured pathways, the internally positioned paired shields may be substantially enveloped within the cage-like shield structure, thereby minimizing internally generated energy strays and parasitics that may normally escape or couple to an adjacent shielded pathway. These shielding modes utilize propagating energy to the various pathways and may be separate of the electrostatic shield effect created by the energization of the shield structure. The propagating energy propagating in a complementary manner provides energy fields of mutually opposed, mutually cancelled fields as a result of the close proximity of opposite propagation. The complementary and paired pathways may provide an internally balanced opposing resistance load function.

A device according to an aspect of the present invention may mimic the functionality of at least one electrostatically shielded transformer. Transformers may be widely used to provide common mode isolation dependent upon a differential mode transfer across the inputs in order to magnetically link the primary windings to the secondary windings to transfer energy. As a result, common mode voltage across the primary winding is rejected. One flaw inherent in the manufacturing of transformers is the propagating energy source capacitance between the primary and secondary windings. As the frequency of the circuit increases, so does capacitive coupling, until circuit isolation may be compromised. If enough parasitic capacitance exists, high frequency RF energy may pass through the transformer and cause an upset in the circuits on the other side of the isolation gap subjected to the transient event.

A shield may be provided between the primary and secondary windings by coupling to a common pathway reference source designed to prevent capacitive coupling between the multiple sets of windings. A device according to an aspect of the present invention improves upon, and reduces the need for, transformers in circuits. The device may use a physical and relative, common pathway shield to suppress parasitics and also may use relative positioning of common pathway shields, a complementary paired pathway layering, the various couplings of the pathway layering, and an external conductive coupling to a conductive area per isolated circuit system, in combination with the various external circuitry, to effectively function as a transformer. If an isolated circuit system is upset by transients, the electrostatically shielded, transformer function of the device discussed herein may be effective for transient suppression and protection, and may simultaneously operate as a combined differential mode and common mode filter. Each set of relative shields and relative conductors may be conductively coupled to at least the same external pathway to provide a transformer functionality for example.

Propagated electromagnetic interference may be the product of both electric and magnetic fields. A device according to an aspect of the present invention may be capable of conditioning energy that uses DC, AC, and AC/DC hybrid-type propagation, including conditioning energy in systems that may contain different types of energy propagation formats and in systems that may contain more than one circuit propagation characteristic.

In an exemplary embodiment, perimeter conductive coupling material for coupling or connecting, by conductive joining, of external portions of a typical embodiment into an assembly may be accomplished by conductive or non-conductive attachments to various types of angled, parallel or perpendicular, as those terms apply relative to at least another pathway, conductors known as apertures or blind or non-blind VIAs, passing through, or almost through, portions respectively of an exemplary embodiment. Couplings to at least one or more load (s), such as a portion of an integrated circuit, for one aspect of the invention may involve a selective coupling, or not, to these various types of conductors, such as apertures and VIAs.

Fabricating a pathway may include forming one or more plated through hole (PTH) via(s) through one or more levels of a pathway. Electronic packages commonly include multiple interconnect levels. In such a package, the invention may include layering of patterned conductive material on one interconnect level that may be electrically insulated from patterned conductive material on another interconnect level, such as by dielectric material layers.

Connections or couplings between the conductive material at the various interconnect levels may be made by forming openings, referred to herein as vias or apertures, in the insulating portions or layers, that in turn can provide an electrically conductive structure such that the patterned or shaped conductive material portions or pathways from different levels are brought into electrical contact with each other. These structures can extend through one or more of the interconnect levels. Use of conductive, non-conductive or conductively-filled apertures and VIAs allows propagating energy to transverse an exemplary embodiment as if utilizing a by-pass or feed-through pathway configuration of an embodiment. An embodiment may serve as a support, a system or a subsystem platform that may contain both or either active and passive components layered to provide the benefits described for conditioning propagated energy between at least one source and at least one load.

An aspect of the present invention may provide a conductive architecture or structure suitable for inclusion in a packaging or an integrated circuit package having other elements.

Other elements may be directly coupled to the device for simultaneous physical and electrical shielding by allowing simultaneous energy interactions to take place between grouped and energized complementary conductors that are fed by other pathways. Typical capacitive balances found between at least one shielding pathway may be found when measuring opposite sides of the shared shield structure per isolated circuit, and may be maintained at measured capacitive levels within this isolated circuit portion, even with the use of common non-specialized dielectrics or pathway conductive materials. Thus, complementary capacitive balancing, or tolerance balancing characteristics, of this type of electrical circuit due to element positioning, size, separations and attachment positioning allow an exemplary embodiment having an isolated circuit system manufactured at 3% capacitive tolerance, internally, to pass to a conductively coupled and energized isolated circuit system a maintained and correlated 3% capacitive tolerance between electrically opposing and paired complementary pathways of each respective isolated circuit system, with respect to the dividing shield structures placed into the isolated circuit system.

An exemplary embodiment may allow utilization of relatively inexpensive dielectrics, conductive materials and various other material elements in a wide variety of ways. Due to the nature of the architecture, the physical and electrical dividing structure created may allow the voltage dividing and balancing among the grouped, adjacent elements, and may allow for the minimization of the effect of material hysteresis and piezoelectric phenomenon to such a degree that propagating energy normally disrupted or lost to these effects may be essentially retained in the form of active component switching response time, as well as instantaneous ability to appear to the various energy-utilizing loads as an apparent open energy flow simultaneously on both electrical sides of a pathway connecting or coupling from an energy source to a respective load, and from the load back to the source.

A structured layer may be shaped, buried within, enveloped by, or inserted into various electrical systems and sub-systems to perform line conditioning or decoupling, for example, and to aid in or to allow for a modifying of an electrical transmission of energy to a desired or predetermined electrical characteristic. Expensive, specialized, dielectric materials that attempt to maintain specific or narrow energy conditioning or voltage balancing may no longer be needed for bypass, feed through, or energy decoupling operations for a circuit.

A device according to an aspect of the present invention may, as set forth hereinabove, be placed between each isolated circuit and a paired plurality of pathways or differential pathways. This exemplary device may operate effectively across a broad frequency range, as compared to a single discrete capacitor or inductor component, and may continue to perform effectively within an isolated circuit system operating beyond, for example, a GHz.

As set forth hereinabove, the exemplary device may perform shielding functions in this broad frequency range. A physical shielding of paired, electrically opposing and adjacent complementary pathways may result from the size of the common pathways in relationship to the size of the complementary pathways, and from the energized, electrostatic suppression or minimization of parasitics originating from the sandwiched complementary conductors and preventing external parasitics. Further, the positioning of the shielding, relative to shielding that is more conductive, may be used to protect against inductive energy and “H-Field” coupling. This technique is known as mutual inductive cancellation.

Parasitic coupling is known as electric field coupling. The shielding function discussed hereinabove provides primary shielding of the various shielded pathways electrostatically against electric field parasitics. Parasitic coupling involving the passage of interfering propagating energy because of mutual or stray parasitic energy originating from the complementary conductor pathways may be thereby suppressed. A device according to an aspect of the present invention may, for example, block capacitive coupling by enveloping oppositely phased conductors in the universal shield architecture with stacked conductive hierarchical progression, thereby providing an electrostatic or Faraday shield effect with respect to the pathway positioning as to the respective layering and position, both vertically and horizontally, of the pathways. The shielding pathway architecture may be used to suppress and prevent internal and external parasitic coupling between potentially noisy conductors and victim conductors, such as by an imposition of a number of common pathway layers that are larger than the smaller paired complementary pathways, but that are positioned between each of the complementary pathway conductor pairs to suppress and to contain the stray parasitics.

Further, as set forth hereinabove, positioning of the shielding, relative to shielding that is more conductive, may be used against inductive energy and “H-Field” coupling. This cancellation is accomplished by physically shielding energy, while simultaneously using a complementary and paired pathway positioned to allow for the insetting of the contained and paired complementary pathways within an area size correspondent to the shield size. A device according to an aspect of the present invention is adapted to use shields separately as internal shields or groupings, thereby substantially isolating and sandwiching pairs of electrically opposing complementary pathways, and thereby providing a physically tight or minimized energy and circuit loop propagation path between each shield and the active load.

Close proximity of shields and non-shields may allow energy along shields even if a direct electrical isolation exists because of 801 material type or the spacing.

Flux cancellation of propagating energy along paired and electrically opposing or differential pathways may result from spacing of pathways apart by a very small distance for oppositely phased electrically complementary operations, thereby resulting in a simultaneous stray parasitic suppression and containment function attributable to tandem shielding, and thereby enhancing energy conditioning.

In attaining minimum areas for various current loops in an isolated circuit system, additional shielding energy currents may be distributed around component shielding architectures. A plurality of shields as described hereinabove may be electrically coupled as either an isolated circuit's reference node, or chassis ground, and may be relied on as a commonly used reference pathway for a circuit. Thus, the various groups of internally paired, complementary pathways may include propagating energy originating from one or more energy sources propagating along external pathways coupled to the circuit by a conductive material. Energy may thus enter the device, undergo conditioning, and continue to each respective load.

The shielding structure may allow for a portion of a shield to operate as the pathway of low impedance for dumping and suppressing, as well as at least partially blocking return of unwanted electromagnetic interference noise and energy into each of the respective energized circuits. In an embodiment, internally located shields may be conductively coupled to a conductive area, thereby adaptively utilizing shielding structure for low impedance dumping and suppressing and at least partially blocking return blocking of unwanted electromagnetic interference noise and energy. Additionally, another set of internally located shields may be conductively coupled to a second conductive area, thereby utilizing shields for low impedance dumping, suppressing and at least partially blocking the return of unwanted electromagnetic interference noise and energy. The conductive areas may be electrically or conductively isolated from one another.

Simultaneous suppression of energy parasitics may be attributed to the enveloping shielding pathway structure, in combination with the cancellation of mutually opposing energy fields, and may be further attributed to the electrically opposing shielded pathways and propagating energy along the various circuit pathways interacting within the various isolated circuits to undergo a conditioning effect taking place upon the propagating energy.

This conditioning may include minimizing effects of H-field energy and E-field energy through simultaneous functions, such as through isolated circuits that contain and maintain a defined electrical area adjacent to dynamic simultaneous low and high impedance pathways of shielding in which various paired pathways have their respective potentials respectively switching as a result of a given potential located on a shielding and used instantaneously and oppositely by these pairings with respect to the utilization by energy found along paired routings of the low and high impedance shields.

The various distance relationships created by the positional overlapping of energy routings within the isolated circuits combine with the various dynamic energy movements to enhance and cancel the various degrees of detrimental energy disruptions normally occurring within active components or loads. The efficient energy conditioning functions occurring within the passive layering architecture allow for development of a dynamic “0” impedance energy “black hole”, or energy drain, along a third pathway coupled common to both complementary pathways and adapted to allow energy to be contained and dissipated upon the shielding, within the various isolated circuits and attached or conductively coupled circuits. Thus, electrically opposing energies may be separated by dielectric material and/or by an interposition shield structure, thereby allowing dynamic and close distance relationship within a specific circuit architecture, and thereby taking advantage of propagating energy and relative distances to allow for exploitation of mutual enhancing cancellation phenomenon and an electrostatic suppression phenomenon to exponentially allow layered conductive and dielectric elements to become highly efficient in energy handling ability.

According to an aspect of the present invention, a device may utilize a single low impedance pathway or a common low impedance pathway as a voltage reference, while utilizing a circuit maintained and balanced within a relative electrical reference point, thereby maintaining minimal parasitic contribution and disruptive energy parasitics in the isolated circuit system. The various attachment schemes described herein may allow a “0” voltage reference, as discussed hereinabove, to develop with respect to each pair or plurality of paired complementary conductors located on opposite sides of the shared central shield, thereby allowing a voltage to be maintained and balanced, even with multiple Simultaneous Switching Operations states among transistor gates located within an active integrated circuit, with minimal disruptive energy parasitics in an isolated circuit.

Shields may be joined using principals of a cage-like conductive shield structure to create one or more shieldings. The conductive coupling of shields together with a larger external conductive area may suppress radiated electromagnetic emissions and as a larger area provides a greater conductive area in which dissipation of voltages and surges may occur. One or more of a plurality of conductive or dielectric materials having different electrical characteristics may be maintained between shields. A specific complementary pathway may include a plurality of commonly conductive structures performing differentially phased conditioning with respect to a “mate”, or paired, plurality of oppositely phased or charged structures forming half of the total sum of manufactured complementary pathways, wherein one half of the complementary pathways forms a first plurality of pathways, and wherein the second half forms a second plurality of pathways. The sum of the complementary pathways of the first and the second plurality of pathways may be evenly separated electrically, with an equal number of pathways used simultaneously, but with half the total sum of the individual complementary pathways operating from, for example, a range of 1 degree to approximately 180 degrees electrically out of phase from the oppositely positioned groupings. Small amounts of dielectric material, such as microns or less, may be used as the conductive material separation between pathways, in addition to the interposing shield, which dielectric may not directly physically or conductively couple to any of the complementarily operating shielded pathways.

An external ground area may couple or conductively connect as an alternative common pathway. Additional numbers of paired external pathways may be attached to lower the circuit impedance. This low impedance phenomenon may occur using alternative or auxiliary circuit return pathways.

A shield architecture may allow shields to be joined together, thereby facilitating energy propagation along a newly developed low impedance pathway, and thereby allowing unwanted electromagnetic interference or noise to move to this created low impedance pathway.

Referring now to FIG. 1A through FIG. 5B, which generally show various common principals of both common and individual variants of an exemplary embodiment configured in a co-planar variant (FIGS. 1A-4I) and a stacked variant (FIGS. 5A and 5B).

In FIG. 1A, there are shown relative locations of the various pathway extensions disclosed according to an aspect of the present invention. A portion of a relative balanced and complementary-symmetrical arrangement utilizing a center shielding pathway designated 8“XX”-“X”M is adapted in the arrangement as the fulcrum of balanced conductive portions in a co-planar variant. A pathway arrangement including at least a first and a second plurality of pathways, wherein the first plurality has at least one pair of pathways arranged electrically isolated from each other and orientated in a first complementary relationship, is illustrated.

Additionally, at least a first half of the second plurality is arranged electrically isolated from a second half of the second plurality, wherein at least two pathways of the second plurality are electrically isolated from the pathways of first plurality. The pathway arrangement may also include a material having properties, such as dielectric, ferromagnetic, or varistor for example, spacing apart pathways of the pathway arrangement. The pathways of the first half of the second plurality are electrically coupled to one another, and the pathways of the second half of the second plurality are electrically coupled to one another. A total number of pathways of the first half of the second plurality may be an odd number greater than one, and a total number of pathways of a second half of the second plurality may also be an odd number greater than one. According to an aspect of the present invention, the pathways of the first half of the second plurality are positioned in a first superposed alignment, while the pathways of the second half of the second plurality are positioned in a second superposed alignment, with the first and second superposed alignments in a mutual superposed alignment herein defined as a co-planar arrangement.

In a non co-planar arrangement, the pathways of the first half of the second plurality may be positioned in a first superposed alignment, and the pathways of the second half of the second plurality may be positioned in a second superposed alignment, with the first and second superposed alignments in arrangement one atop the other. In one arrangement, at least four pathways are electrically isolated.

An illustrative embodiment of the present invention may include at least three pluralities of pathways, including a first plurality of pathways and a second plurality of pathways. The first and second pluralities of pathways may include pathway members of the first plurality having an equal and opposite pathway member found in the second plurality of pathways. Members of the first and second pluralities of pathways may be substantially the same size and shape, and may be positioned complementary, and may also operate in an electrically complementary manner. Thus, the pairings of the first and second pluralities of pathways may result in identical numbers of members of the first and second pluralities of pathways. An exemplary embodiment may provide at least a first and a second shield allowing for development of individual isolated low circuit impedance pathways. Structurally, the shields may be accomplished by a third plurality of pathways and a fourth plurality of pathways. Each shielding plurality may include shields of equal size and shape. Each of the third and fourth plurality of pathways may be conductively coupled. Conductive coupling may be accomplished by a variety of methods and materials known to those possessing an ordinary skill in the pertinent arts. Thus, when the third and a fourth plurality are grouped as two sets of shields utilizing the first and second plurality receiving shielding, the third and fourth pluralities may be coupled to a common pathway to develop a low circuit impedance pathway for energy propagation for conditioning of the circuit energy.

Pathways may additionally be arranged in a bypass arrangement, such that when placed face to face, main-body pathways 80 may be aligned superposed, with the exception of any pathway extensions such as 812NNE, 811NNE, 812SSW and 811SSW of the lower sub-circuit portion, for example, shown as mirror images depicted in FIG. 5A and FIG. 5B, for example.

Within the pluralities, individual pathway members may be of substantially the same size and shape and may be conductively coupled. However, individual pathway members of one plurality may not be conductively coupled to members of a different plurality of pathways.

There may be situations wherein members of one plurality may be connected to members of a different plurality, such as wherein a first plurality of shields and a second plurality of shields are externally coupled to the same conductor.

Common elements may include energy flow in accordance with conceptual energy indicators 600, 601, 602, 603 depicting the dynamic energy movements in co-planar shielded by-pass pathways, such as those shown in FIG. 1A-1C. An embodiment may provide for at least multiple shields for development of multiple isolated low circuit impedance pathways for multiple circuits.

Referring still to FIG. 1A, pathways may be shielded by the relative, common pathways, and may include a main-body pathway 80 with at least one pathway extension 812“X”. The shields shown include a main-body shield pathway 81 with at least one pathway extension designated 99“X”/79“X”. The shields may sandwich and envelope the main-body 799, including a conductive inner pathway formed of conductive materials from the family of noble or base metals traditionally used in co-fired electronic components or conductive material, such as Ag, Ag/Pd, Cu, Ni, Pt, Au, Pd, or combination materials such as metal oxide and glass frit. A capacitance and a resistance value may be achieved in one family of pathways, as described hereinabove, such as by use of ruthenium oxide as the resistive material and Ag/Pd as the conductive material. Further, variations in pathway geometry may yield different resistance and capacitance values. Variations may be achieved by altering the materials from which the pathways are made. For example, a conductive metal, such as silver, may be selectively added to the metal oxide/glass frit material to lower the resistance of the material.

A plurality of pathways, 865-1 and 865-2, are shown positioned co-planar and spaced apart on a same portion of material 801. Each pathway of the co-planar pathways 865-1 and 865-2, may be formed of conductive material 799, or a hybrid of conductive material and another material, herein designated as 799“x”. Each co planar pathway 865-1 and 865-2 may also be formed as a bypass pathway, wherein each pathway includes a main-body pathway 80 having a corresponding main-body edge and perimeter, 803A and 803B, respectively and at least one pathway contiguous extension 812“X”. Each co-planar pathway 865-1 and 865-2, may include at least one pathway contiguous extension 812SSW and 811SSW with a portion of the main-body edge 803A and 803B extending therefrom. Extension 812“X” is a portion of the pathway material formed in conjunction with a main-body pathway 80 from which it extends. Main-body pathway 80, an 812“X” may be found as an extension of material 799 or 799“x” extending beyond an accepted average perimeter edge 803“X”. Extensions 812“X” and 79“X” may be found respectively positioned as a contiguous portion of the pathway from which it is formed. Each main-body pathway may have edge 803A, 803B positioned relative and spaced apart a distance 814F from the embodiment edge 817. Embodiment edge 817 may include a material 801. Co-planar main-body pathway's edge 803“x” may be positioned and spaced apart a distance 814J. Pathway extensions 812SSW and 811SSW may conductively couple a respective pathway main-body 80 to an outer pathway 890SSW and 891 SSW, which may be positioned at edge 817. The co-planar arranged, main-body pathway 80 may be positioned “sandwiched” between the area of registered coverage of two layering of co-planar, main-body pathway 81s.

Combining mutually opposing fields causes a cancellation or minimization effect. The closer the complementary, symmetrically oriented shields, the better the resulting mutually opposing cancellation effect on opposing energy propagation. The more superposed the orientation of the complementary, symmetrically oriented shields is, the better the resulting suppression of parasitics and cancellation effect.

Referring still to FIG. 1A, the edges of the plurality of co-planar shields may be represented by dotted lines 805A and 805B. Main-body pathways 81 of each of the plurality of shields are larger than a sandwiching main-body pathway 80 of any corresponding sandwiched pathway. This may create an inset area 806 relative to the positions of the shields and remaining pathways. The size of main-bodies 80 and 81 may be substantially similar, and thus the insetting positioning relationships may be minimal in certain embodiments. Increased parasitic suppression may be obtained by insetting pathways, including a main-body 80, to be shielded by larger pathway main-body 81s. For example, an inset of a main-body 80 of pathways 865-1 inset may be separated a distance of 1 to 20+ times the spacing provided by the thickness of the material 801 separating pathway 865-1 and adjacent center co-planar pathway 800-1-IM, as illustrated in FIG. 1B.

Plurality of co-planar shield edges 805A and 805B may be positioned and spaced apart a distance 814K, and may be a distance 814 relative to edges 805A and 805B and the edge 817. Other distances 814J relative from either edges 803A and 803B may be provided.

Further, distance 814F may be present between one 803“X” and an edge 817. Each co-planar shield may include a plurality of contiguous pathway extension portions, such as, for example, portions 79NNE, 79SSE, 99NNE and 99SSE, extending from the plurality of co-planar shield edges 805A and 805B. Plurality of co-planar shields may include a plurality of outer pathway material 901 NNE, 901 SSE, 902NNE and 902SSE positioned at the edge 817.

Conceptual energy indicators 602 represent the various dynamic energy movements within the co-planar pathways 865-1 and 865-2. Unwanted energy may be transferred to the co-planar shields in accordance with the provision by the shields providing for a low impedance pathway, which shields may additionally be electrically coupled to another pathway or conductive area.

Referring now to FIGS. 1B and 1C, layer sequences are illustrated for a first plurality of co-planar pathways 865-1, 865-2, a second plurality of co-planar pathways 855-1, 855-2, and a third plurality of co-planar pathways 825-1-IM, 825-2-IM, 815-1, 815-2, 800-1-IM, 800-2-IM, 810-1, 810-2, and 820-1-IM, 820-2-IM. The first, second, and third pluralities may be stacked to form an embodiment 3199, 3200, 3201. The third plurality of co-planar pathways may provide shielding. Main-bodies 81 of the plurality of co-planer shields 825-1-IM, 825-2-IM; 815-1, 815-2; 800-1-IM, 800-2-IM; 810-1, 810-2; and 820-1-IM, 820-2-IM may be substantially similar in size and shape, and may be spaced apart in co-planar locations on different layers of material 801. The first plurality of co-planar pathways 865-1 and 865-2 may have at least the corresponding, opposing, and complementary second plurality of co-planar pathways 855-1 and 855-2. These first and second pluralities of co-planar pathways, when oriented face to face, may have main-body pathways 80s co-registered and aligned except for the various contiguous pathway extensions 812“X”, 811“X”. As shown in FIGS. 1B and 1C, a pair of outer co-planar pathways 820-1-IM, 825-1-IM may serve as pathway shields, thereby improving the shielding effectiveness of the other conductively coupled pluralities of pathways with a main-body 81s.

As illustrated in the varied embodiments 3199, 3200, 3201, the location of extensions 79NNE, 79SSE, of shields 825-1-IM, 815-1, 800-1-IM, 810-1, and 820-1-IM and extensions 99NNE, 99SSE of the shields 825-2-IM, 815-2, 800-2-IM, 810-2, and 820-2-IM, may be varied. In FIG. 1B, for example, extensions 79NNE and 99NNE may be arranged spaced apart, diagonally from extensions 79SSE and 99SSE and on opposite sides of shield main-body 81. In FIG. 1C, for example, extensions 79NNE and 99NNE may be arranged spaced apart in line with extensions 79SSE and 99SSE on opposite sides of shield main-body 81. In FIG. 1B, extensions 812NNE and 811NNE may be arranged spaced apart, extending toward the same edge 812 of layer of material 801, and extensions 812SSW and 811 SSW may be arranged spaced apart, each extending toward the opposite edge 812 of layer of material 801. In FIG. 1C, pathways 865-1 and 865-2 may be mirror images, as discussed hereinabove. Comparably to FIG. 1B, extensions 812NNE and 811NNE may be arranged spaced apart, extending toward opposite edges 817 of layer of material 801. Extensions 812SSW and 811SSW may be arranged spaced apart, extending toward the opposite edge of layer of material 801, such that extensions 812NNE and 811 SSW extend toward opposite edges 812“X” of the respective layer of material 801.

Referring now to FIGS. 2A and 2B, FIG. 2A illustrates a schematic plan view of an embodiment of FIG. 2B according to an aspect of the present invention. FIG. 2B depicts a pathway arrangement including a layout of a first, a second, a third, a fourth, a fifth, a sixth, a seventh, a eighth, a ninth and a tenth pathway, wherein at least the third and the fourth pathway, for example, may be co-planar and arranged spaced apart from each other. FIG. 2B illustrates the first and the second pathway arranged below the third and the fourth pathway, and the fifth and the sixth pathway arranged above the third and the fourth pathway, and the seventh and the eighth pathway arranged above the fifth and the sixth pathway, and the ninth and the tenth pathway, arranged above the seventh and the eighth pathway. These pathways have various respective internal contiguous pathway extensions 812“X”, 811“X”, 79“X” and 99“X”, and may be discrete components having the same minimal numbers of layering.

Internal contiguous pathway extensions 812“X”, 811“X”, 79“X” and 99“X”, and conductively coupled external pathways 890“X”, 891“X” 802“X” and 902“X”, may be coupled to the inner pathway of the plurality of co-planar pathways of the main-body pathway 80 and 81.

Referring now to FIGS. 3A and 3B, in FIG. 3A there is shown a schematic plan view of an embodiment of FIG. 3B, wherein outer pathways may be selectively conductively coupled in at least two isolated circuit portions. FIG. 3B depicts an pathway arrangement including a minimal layout of a first, a second, a third, a fourth, a fifth, a sixth, a seventh, a eighth, a ninth and a tenth pathway, wherein at least the third and the fourth pathway, for example, are co-planar and arranged spaced apart from each other. The device shown in FIG. 3B may have the first and the second pathway arranged below the third and the fourth pathway, and the fifth and the sixth pathway arranged above the third and the fourth pathway, and the seventh and the eighth pathway arranged above the fifth and the sixth pathway, and the ninth and the tenth pathway arranged above the seventh and the eighth pathway. These pathways have various respective internal contiguous pathway extensions 812“X”, 811“X”, 79“X” and 99“X”, and may be discrete components having the same minimal number of layering.

Referring now to FIG. 3C, a plan view of a shield according to an aspect of the present invention is illustrated. The embodiment depicted in FIG. 3C includes at least one additional pathway, as compared to the device of FIG. 3B. This additional pathway 1100-IM“X” may be one of at least a plurality of shields in the stack of pathways, which shields may span across the two circuit portions. Pathway 1100-IM“X” may be one of at least two outer sandwiching shields in the stack of pathways. Shields may span across the two circuits by adding a centrally arranged 1100-IM“X” pathway electrically coupled to the outer 1100-IM“X” shields.

Pathways 1100-IM“X” may have at least one extension, and are illustrated with two extensions 1099E and 1099W, and may allow for sandwiching shields for all of the pathways within the present invention. At least three shields may be coupled together and may include a centering shield dividing an energy load or energy source of an isolated circuit or dividing two isolated circuits.

A shield 00GS may be electrically isolated from other shields and may be arranged to effect an energy propagation of an isolated circuit. An isolated circuit may be sandwiched by a shield. A shield may be electrically coupled to a conductive area that is isolated from any other conductive areas thereby effecting an energy propagation.

FIGS. 4A-4I depict assembled components of various embodiments according to aspects of the present invention. The arrangements of FIG. 4A to FIG. 4I may include minimal layouts of a first, a second, a third, a fourth, a fifth, a sixth, a seventh, a eighth, a ninth and a tenth pathway, wherein at least the third and the fourth pathway, for example, are co-planar and arranged spaced apart from each other. The first and the second pathway may be arranged below the third and the fourth pathway, and the fifth and the sixth pathway may be arranged above the third and the fourth pathway, and the seventh and the eighth pathway may be arranged above the fifth and the sixth pathway, and the ninth and the tenth pathway may be arranged above the seventh and the eighth pathway. These pathways have various respective internal contiguous pathway extensions 812“X”, 811“X”, 79“X” and 99“X”, and may be an assembled final discrete component, for example.

Referring to FIG. 5A, there is shown a stacking of multiple, non-shared circuits including groups of pathways according to an aspect of the present invention. Included in FIG. 5A is a marker 1000 showing a continuation of the stacking arrangement to the next column of FIG. 5A. Conceptual energy indicators 600,601, 602,603 indicate energy flow.

Material 799 may be deposited on material 801 for component 6900 shields designated 815-1, 800-1-IM, 810-1, 815-2, 800-2-IM, and 810-2. Shields 810-A and 810-B are separated shields of at least part of an isolated circuit system. Shields 815-A and 815-B are separated shields of at least part of an isolated circuit system. Shields 800-A and 800-B are separated shields of at least part of an isolated circuit system. Shields 835-A and 835-B are separated shields of at least part of an isolated circuit system. Conductors 855-1 and 855-2 are separated and shielded pathways in bypass configuration. Conductors 865-1 and 865-2 are separated and shielded pathways in bypass configuration. In FIG. 5A, a pathway arrangement is depicted including at least six orientations of pathways of two types of pathways, wherein each orientation of the pathways of the at least six orientations of pathways provides conductive isolation from the remaining orientations of pathways.

Referring to FIG. 5B, there is shown a stacked shield structure according to an aspect of the present invention. FIG. 5B depicts an embodiment similar to that of FIG. 5A, wherein two sets of 855“X” and 865“X” pathways are omitted for purposes of clarity, and wherein the shields of FIG. 5A are oriented in flip-flop for each relative set of 855“X” and 865“X” pathways. The 79“X” pathway extensions may be rotated 90 degrees relative to the various pathway extensions 811“x” and 812“X”. A dynamic result of this configuration, as illustrated by the conceptual energy indicators, may be enhanced by nulling the extensions of the two sets of 855“X” and 865“X” pathways of the two isolated circuits, and by relatively positioning the shield of each isolated circuit pairing 855A and 865A approximately 90 degrees null to the various pathway extensions of 855B and 865B.

Referring to FIG. 5B, there is shown a stacked shield structure according to an aspect of the present invention. FIG. 5B depicts an embodiment similar to that of FIG. 5A, wherein two sets of 855“X” and 865“X” pathways are omitted for purposes of clarity, and wherein the shields of FIG. 5A are oriented in flip-flop for each relative set of 855“X” and 865“X” pathways. The 79“X” pathway extensions may be rotated 90 degrees relative to the various pathway extensions 811“x” and 812“X”. A dynamic result of this configuration, as illustrated by the conceptual energy indicators, may be enhanced by nulling the extensions of the two sets of 855“X” and 865“X” pathways of the two isolated circuits, and by relatively positioning the shield of each isolated circuit pairing 865B and 865A approximately 90 degrees null to the various pathway extensions of 865B and 865A.

As discussed hereinabove, in an embodiment of the present invention, multiple complementary or paired shielded pathways may include the first and second pluralities of pathways. Energy may utilize the various paired, feed-through or bypass pathway layers in a generally parallel and even manner, for example. Pathway elements may include non-insulated and conductive apertures, and conductive through-VIAs, to provide propagating energy and maintain a generally non-parallel or perpendicular relationship, and additionally maintain a separate electrical relationship with an adjoining circuit. These pathways may maintain balance internally, and may facilitate an electrical opposition along opposing complementary pairings. This relationship among complementary pairs of pathways may occur while the pathways and the energy are undergoing an opposite operational usage within the shielding structure attached externally.

Referring now to FIG. 5C, there is shown a relative plan view of a stacked multiple, non-shared circuit network having VIAs and including groups of pathways according to an aspect of the present invention. The device according to an aspect of the present invention depicted in FIG. 5C includes a hole-through energy conditioner. Hole-through energy conditioners may be formed such that many of the energy propagation principals disclosed herein are retained, including the use of multiple sets of shields for energy conditioning possessing. FIG. 5C, further depicts null pathway sets with pathway arrangement 6969.

Pathway arrangement 6969 is similar to FIG. 5B, with the absence of pathway extensions 79“X”, 811“x” and 812“X”, and with the substitution of 8879“X”, 8811“X” and 8812“X” VIAs functioning from a different direction relative to the main-body 80 and 81.

Referring still to FIG. 5C, during the manufacturing process, conductive holes 912, VIAS or conductive apertures may be used to interconnect 8806 an integrated circuit, and may be formed through one or more pathway layers using mechanical drilling, laser drilling, etching, punching, or other hole formation techniques. Each specific interconnection 8806 may enable various pathways to be electrically connected or insulated. Each specific interconnection 8806 may extend through all layers of pathway arrangement 6969, or may be bounded above or below by one or more layers. Pathway arrangement 6969 may include an organic substrate, such as an epoxy material, or patterned conductive material. If an organic substrate is used, for example, standard printed circuit board materials such as FR-4 epoxy-glass, polymide-glass, benzocyclobutene, Teflon, other epoxy resins, or the like could be used in various embodiments. In alternate embodiments, a pathway arrangement could include an inorganic substance, such as ceramic, for example. In various embodiments, the thickness of the levels may be approximately 10-1000 microns. Interconnections 8806 between the various conductive layers may also be formed by selectively removing dielectric and conductive materials, thereby exposing the conductive material of the lower conductive layers 904 (not shown), and by filling the holes so formed by the removal with a conductive paste 799A or electrolytic plating 799B, for example.

Interconnections 8806 may couple exposed conductive layers to a relative side of the pathway arrangement 6969. Interconnections 8806 may take the form of pads or lands to which an integrated circuit may be attached, for example. Interconnections 8806 may be formed using known techniques, such as by filling the selectively removed portions of dielectric with conductive paste, electrolytic plating, photolithography, or screen printing, for example. The resulting pathway arrangement 6969 includes one or more layers of patterned conductive material 799, separated by non-conducting layers, and interconnected by interconnects 8806. Different techniques may be used to interconnect and isolate the various layers of patterned conductive material 799. For example, rather than forming and selectively removing portions of the various conducting 799 and non-conducting layers 801, openings between the various layers may be included by selectively adding the desired portions of the conducting 799 and non-conducting layers 801. Removal techniques, such as chemical mechanical planarization, may be used to physically abrade away multiple layers of different types of conducting and non-conducting materials, resulting in the desired openings for various interconnects.

Pathway arrangement 6969 may be configured using a multi-aperture, multilayer energy conditioning pathway set, with a substrate format adapted to condition propagating energy. Pathway arrangement 6969 may condition propagating energy by utilizing a combined energy conditioning methodology of conductively filled apertures, known in the art as VIAs 8879“X”, 8811“X” and 8812“X”, in combination with a multi-layer common conductive Faraday cage-like shielding technology with immured propagational pathways.

Interconnecting pathway arrangement and an IC may be achieved with wire bonding interconnection, flip-chip ball-grid array interconnections, microBall-grid interconnections, combinations thereof, or any other standard industry accepted methodologies. For example, a “flip chip” type of integrated circuit, meaning that the input/output terminations as well as any other pathways on the chip may occur at any point on its surface. After the IC chip is prepared for attachment to pathway arrangement 6969, the chip may be flipped over and attached, by solder bumps or balls to matching pads on the top surface of pathway arrangement 6969. Alternatively, an integrated circuit may be wire bonded by connecting input/output terminations to pathway arrangement 6969 using bond wires to pads on the top surface of pathway arrangement 6969.

The circuits within pathway arrangement 6969 may act as a source to load pathway arrangement requiring capacitance, noise suppression, and/or voltage dampening. This capacitance may be provided by formation of the capacitance developed and embedded within pathway arrangement 6969. This capacitance may be coupled to the integrated circuit loads using a paired pathway and the shield, as described above. Additional capacitance may be provided to a circuit electrically coupled to an integrated circuit to provide voltage dampening and noise suppression. Close proximity of off-chip energy sources may provide a capacitance each along the low inductance path to the load. Common shielding pathways may be utilized as the “0” voltage circuit reference node for both off-chip energy sources the common conductive interposer energy pathway configurations.

Pathway arrangement 6969 may be connected to an integrated circuit by commonly accepted industry connection methods and couplings 799A and 799B, including Bumpless Build-Up Layer (BBUL) packaging. This technology enables higher performance, thinner and lighter packages, and lowers power consumption. In a BBUL package, the silicon die or IC is embedded in a package with a pathway arrangement operable as a first level interconnect.

Thus, the BBUL package as a whole is not just attached to one surface of the IC. For example, electrical connections between the die and one or more of the various shields and the package may be made with copper lines, not necessarily C4 solder bumps. These features combine to make the package thinner and lighter than other IC packages, while delivering higher performance and reducing power consumption. BBUL may enhance the ability of a manufacturer to couple multiple silicon components to pathway arrangement 6969.

Shielded pathways 8811, 8812, and 8879 may be electrically connected between respective energy sources and respective load of the IC by common industry methodologies, thereby allowing for conditioning of propagating energy. Shields 8879 may conductively coupled to a shield including 1055-2. A shield and its other conductive portions including 8811 and 8812 may be electrically coupled to a respective complementary pathway which poses no polarity charge of significance before hook-up, thereby preventing each layer 8811 and 8812 from changing energy propagation direction functions, such preventing layer 8811 and 8812 from changing from input and output to output and input, respectively, as is understood by those possessing an ordinary skill in the pertinent arts.

For stacked variants depicted in FIGS. 5A, 5B and 5C, adding three pathways 110000-IM-“X”, including one between 810-1 and 815-2, designated as 1100-IM-“C”, may bisect a balanced symmetry of the total number of pathways located into equal numbers on opposite sides of 1100-IM-“C”. The addition of 1100-IM-1 and 1100-IM-2, electrically coupled to 1100-IM-C, creates a common or a shield structure (not all shown). Shields of a shield structure may be of substantially the same size or not. Shields may or may not be physically isolated from any other shields for any one or more embodiments of the present invention. Thus, shields may or may not be electrically or conductively isolated from any other shields for any one or more embodiments of the present invention.

An odd number of shields may be coupled together thereby allowing formation of a common reference or node utilizing all other shields. The number of shields 1100-IM-“X” is not confined to using extensions 1099E and 1099W such as shield 00GS, as any number of extensions in almost any direction may be used to facilitate a coupling. A relative balanced and complementary-symmetrical arrangement may be formed with respect to a center shield 8“XX” or shield 800/800-IM for a arrangement fulcrum of balanced conductive portions. At least a partial flux field cancellation of energy propagating along or between paired and electrically opposing complementary pathways occurs in this balanced but shifted embodiment. Further, simultaneous stray energy parasitics, complementary charged suppression, physical and electrical shielding containment and a faraday effect may also occur. This result is achieved because the magnetic flux energies travel at least partially along the shield wherein the RF return path is parallel and adjacent to a corresponding pathway. Thus, the magnetic flux energy may be measured or observed relative to a return. Shifted pathways may be in relative balance and complementarily and symmetrically positioned with respect to center shields, such as shields 800/800-“X”-IM, and may include a relatively shifted, balanced, complementary, and symmetrical arrangement of predetermined shields and pathways complementarily sandwiched around a centrally positioned shield, such as 800/800-IM, for example.

The exemplary embodiments of FIGS. 1A, 1B, 1C, through FIG. 4I, for example may include these ‘shifted’ embodiments. These shifted embodiments may include a multiplicity of layers having a shielding, a pathway, a shielding, a pathway, and a shielding. Each of these multiplicity of layers may be centered and complementary about a center shield 800/800-“X”-IM, such as for co-planar variants, and the entire multiplicity of layers may be centered about a main center shield. Complementarity and balance may be maintained about the center shield, and the main center shield, although individual shields may be shifted to create discrete imbalances as between a given matched pathway pair, for example. Shifting may expose a portion of at least one pathway outside the perimeter of the superposed shielding, thereby allowing for parasitics and thereby varying, for example, impedance characteristics.

For example, a given pathway may be shifted 5 points to the left. This shifting may be accounted for in the matched pairs about a center shield, and, consequently, either an adjacent matched pair pathway of opposing polarity may be shifted 5 points, or 5 adjacent pathways of opposite polarity may each shift 1 point, thereby maintaining complementarity and balance. Further, pathways may remain within the perimeter of the superposed shielding, and nonetheless be shifted thereunder. Such a shifting under the shielding may, nonetheless, make desirable a balancing. However, certain exemplary embodiments not shown may include situations wherein pathways are pulled toward the center of a shield, and remain under the shield evidencing differing electrical characteristics, such as inductive behavior, in a balanced or unbalanced state.

Referring now to FIG. 6, there is shown a stacked multiple circuit including embodiment 6900, conductive energy pathways, isolated energy sources, isolated energy-utilizing loads, and isolated common conductive pathways. The conductive energy pathways may be conductively coupled to embodiment 6900 by a conductive coupling material, such as, for example, by a solder or industry equivalent. Vias 315, conductive pathways continuing below the surface of the substrate, may couple to the conductive pathways, and may include conductive material that serves as a contiguous conductive pathway for propagating energies. The isolated common conductive pathways may not be directly coupled to the isolated energy sources or the isolated energy-utilizing loads. As discussed hereinabove, embodiment 6900 may include four pluralities of pathways including electrodes and shields, with each plurality electrically isolated. The shields may be conductively coupled. The conductively coupled shields may be externally coupled to an isolated common conductive pathway, which is not directly conductively coupled to the electrodes, using a conductive coupling material. As shown in FIG. 6 an electrode, 815-1, 800-1-IM and 810-1, may be conductively coupled to 802GA, 802GB. A shield, 815-2, 800-2-IM, and 810-2, may be conductively coupled to 902GA and 902 GB. These couplings may not be conductively coupled to the first plurality of electrodes or the second plurality of electrodes. In this configuration, both isolated circuits may be utilizing the isolated and separate voltage references and an isolated common impedance path such as REF 1 and REF 2 in FIG. 6.

Referring now to FIG. 7, there is shown a stacked co-planar multiple circuit including embodiment 3210, conductive energy pathways, isolated energy sources, isolated energy-utilizing loads, and isolated common conductive pathways. The conductive energy pathways may be conductively coupled to embodiment 3210 by a conductive coupling material. Vias 315, conductive pathways continuing below the surface of the substrate, may couple to the conductive pathways and may include conductive material that serves as a contiguous conductive pathway for propagating energies. The isolated common conductive pathways may not be directly coupled to the isolated energy sources or the isolated energy-utilizing loads. As discussed hereinabove, embodiment 3210 may include four pluralities of pathways including electrodes and shields, with each plurality electrically isolated. The conductively coupled shields may be externally coupled to an isolated common energy pathway, which is not directly conductively coupled to the first or the second plurality of electrodes in this co-planar arrangement. A third plurality of electrodes, 815-1, 800-1-IM and 810-1 may be conductively coupled to 802GA, 802 GB, 815-2 and 800-2-IM, and also, may be conductively coupled to 902GA, 902 GB, and may not be conductively coupled to the first plurality or the second plurality. In this configuration, both isolated circuits may be utilizing a separate and a respective isolated and separate voltage reference and a separate and a respective isolated impedance path, a separate and a respective isolated common impedance path and at least one separate and respective low inductance pathway such as REF 1 and REF 2 in FIG. 7.

Referring now to FIG. 4A thru to FIG. 7, the termination electrodes 890A, 890B, and 891A, 891 B, 802GA, 802GB, and 902GA, 902GB, may be monolithic or multi-layered.

Termination electrodes 802GA, 802GB, 902GA, 902GB, may be located at other respective portions of a sintered body. Each main body electrode layers 81 or 80, and the associate electrode extensions 99/79G“X” or 812“X”, may define an electrode which extends to, and conductively couples to, the associated termination electrodes 802GA, 802GB, 902GA, 902GB and 890A, 890B, and 891A, 891B.

The present invention may be utilized for many energy conditioning functions that utilize commonly coupled shielding structure element for emulating a center tap of resistor/voltage divider network. This resistor/voltage divider network may be normally constructed using a ratio of various integrated circuit resistors. However, various integrated circuit resistors may be replaced by a device according to an aspect of the present invention, the device utilizing, for example, specific conductive/resistive materials 799A or naturally occurring resistance properties of pathway material 799, or utilizing a varied physical layout.

A voltage dividing function may be present as portions of a common and shared pathway shield structure are utilized to define a common voltage reference located at both respective sides of the common pathway shield structure.

In embodiments, whether initially stacked vertically during a manufacturing process, or in combination with a co-planar pairings as described hereinabove, the number of complementary pathways pairings may be multiplied in a predetermined manner to create a number of pathway element combinations of a generally physically or electrically parallel nature.

Further, although not shown, a device of the present invention may be fabricated in silicon and directly incorporated into integrated circuit microprocessor circuitry or microprocessor chip packaging. Any suitable method for depositing electrically conductive materials may be used, such as plating, sputtering, vapor, electrical, screening, stenciling, vacuum, and chemical including chemical vapor deposition (CVD).

While certain embodiments have been herein described in position as “upper” or “above”, or “lower” or “below”, or any other positional or directional description, it will be understood that these descriptions are merely relative and are not intended to be limiting.

The present invention may be implemented in a number of different embodiments, including a energy conditioning embodiment as an energy conditioner for an electronic assembly, an energy conditioning substrate, an integrated circuit package, an electronic assembly or an electronic system in the form of a energy conditioning system, and may be fabricated using various methods. Other embodiments will be readily apparent to those of ordinary skill in the art.

Claims

1. A conductive architecture comprising:

1.] a substrate;
2.] three conductor plates including: (1) a first conductor plate, (2) a second conductor plate that is spaced apart from the first conductor plate, and (3) a third conductor plate that is spaced apart from both the first and second conductor plates, and wherein the three conductor plates are (a.) parallel to one another, (b.) conductively connected to one another, (c.) together vertically stacked such that the second conductor plate is located 1) below the first conductor plate, 2) above the third conductor plate, and 3) between the first and third conductor plates, (4) each at least partially embedded within the substrate;
3.] a first grouping of four individual structurally aligned conductors, and wherein the four individual structurally aligned conductors of the first grouping are (1) each physically aligned in close proximity to at least one of the other individual structurally aligned conductors of the first grouping, (2) each physically positioned in a side by side arrangement to at least one of the other individual structurally aligned conductors of the first grouping within the space between the first and second conductor plates;
4.] a second grouping of four individual structurally aligned conductors, and wherein the four individual structurally aligned conductors of the second grouping are (1) each physically aligned in close proximity to at least one of the other individual structurally aligned conductors of the second grouping, (2) each physically positioned in the side by side arrangement to at least one of the other individual structurally aligned conductors of the second grouping within the space between the second and third conductor plates;
5.] a third grouping of four individual structurally aligned conductors, and wherein the four individual structurally aligned conductors of the third grouping are (1) each physically aligned in close proximity to at least one of the other individual structurally aligned conductors of the third grouping, (2) each physically positioned in a side by side arrangement to at least one of the other individual structurally aligned conductors of the third grouping within the space between the first and second conductor plates;
6.] a fourth grouping of four individual structurally aligned conductors, and wherein the four individual structurally aligned conductors of the fourth grouping are (1) each physically aligned in close proximity to at least one of the other individual structurally aligned conductors of the fourth grouping, (2) each physically positioned in the side by side arrangement to at least one of the other individual structurally aligned conductors of the fourth grouping within the space between the second and third conductor plates; [A the three conductor plates are each parallel to all of the individual structurally aligned conductors, [B the three conductor plates are each larger in size than any one of the individual structurally aligned conductors, [C the individual structurally aligned conductors are embedded within the substrate, [D each individual structurally aligned conductor belongs to only one of the first, second, third, and fourth groupings, [E each of the individual structurally aligned conductors of the first, second, third and fourth groupings is a respective structurally straight elongated conductor portion of a respective larger, individual structurally elongated conductor of the conductive architecture, [F each of the individual structurally aligned conductors of the first, second, third and fourth groupings belongs to a different respective larger, individual structurally elongated conductor of the conductive architecture, [G none of the three conductor plates are conductively attached to any of the respective larger, individual structurally elongated conductors, [H the respective larger, individual structurally elongated conductors are each at least partially embedded within the substrate such that within the substrate, the respective larger, individual structurally elongated conductors are each conductively isolated from one another, [I the individual structurally aligned conductors of the first and second groupings are aligned parallel to one another such that all of the individual structurally aligned conductors of the first and second groupings are arranged together in the same physically longitudinal structure orientation, [J each of the individual structurally aligned conductors of the first grouping is vertically aligned to only one corresponding individual structurally aligned conductor of the second grouping and each of the individual structurally aligned conductors of the second grouping is vertically aligned to only one corresponding individual structurally aligned conductor of the first grouping, such that the first and second groupings both include [1] a respective first individual structurally aligned conductor such that both respective first individual structurally aligned conductors of the first and second groupings together are [a] physically shielded one another by the second conductor plate located therebetween, and [b] in a first superposed structurally aligned conductor arrangement, [2] a respective second individual structurally aligned conductor such that both respective second individual structurally aligned conductors of the first and second groupings together are [a] physically shielded one another by the second conductor plate located therebetween, and [b] in a second superposed structurally aligned conductor arrangement, [3] a respective third individual structurally aligned conductor such that both respective third individual structurally aligned conductors of the first and second groupings together are [a] physically shielded one another by the second conductor plate located therebetween, and [b] in a third superposed structurally aligned conductor arrangement, [4] a respective fourth individual structurally aligned conductor such that both respective fourth individual structurally aligned conductors of the first and second groupings together are [a] physically shielded one another by the second conductor plate located therebetween, and [b] in a fourth superposed structurally aligned conductor arrangement, [K the individual structurally aligned conductors of the third and fourth groupings are aligned parallel to one another such that all of the individual structurally aligned conductors of the third and fourth groupings are arranged together in the same physically longitudinal structure orientation, [L each of the individual structurally aligned conductors of the third grouping is vertically aligned to only one corresponding individual structurally aligned conductor of the fourth grouping and each of the individual structurally aligned conductors of the fourth grouping is vertically aligned to only one corresponding individual structurally aligned conductor of the third grouping, such that the third and fourth groupings both include [1] a respective first individual structurally aligned conductor such that both respective first individual structurally aligned conductors of the third and fourth groupings together are [a] physically shielded one another by the second conductor plate located therebetween, and [b] in a fifth superposed structurally aligned conductor arrangement, [2] a respective second individual structurally aligned conductor such that both respective second individual structurally aligned conductors of the third and fourth groupings together are [a] physically shielded one another by the second conductor plate located therebetween, and [b] in a sixth superposed structurally aligned conductor arrangement, [3] a respective third individual structurally aligned conductor such that both respective third individual structurally aligned conductors of the third and fourth groupings together are [a] physically shielded one another by the second conductor plate located therebetween, and [b] in a seventh superposed structurally aligned conductor arrangement, [4] a respective fourth individual structurally aligned conductor such that both respective fourth individual structurally aligned conductors of the third and fourth groupings together are [a] physically shielded one another by the second conductor plate located therebetween, and [b] in an eighth superposed structurally aligned conductor arrangement.
Referenced Cited
U.S. Patent Documents
676185 June 1901 Gattinger
3104363 September 1963 Butler
3240621 March 1966 Flower, Jr. et al.
3273027 September 1966 Bourgault et al.
3343034 September 1967 Ovshinsky
3379943 April 1968 Breedlove
3381244 April 1968 Dalley
3488528 January 1970 Emond
3496434 February 1970 Prokopowicz
3519959 July 1970 Bewley et al.
3534301 October 1970 Golembeski
3568000 March 1971 Martre et al.
3573677 April 1971 Detar
3652941 March 1972 Neuf
3680005 July 1972 Bewley et al.
3681612 August 1972 Vogl
3688361 September 1972 Bonini
3691563 September 1972 Shelton
3701958 October 1972 Herbert
3736471 May 1973 Donze et al.
3740678 June 1973 Hill
3742420 June 1973 Harnden, Jr.
3764727 October 1973 Balde
3790858 February 1974 Brancaleone et al.
3842374 October 1974 Schlicke
3880493 April 1975 Lockhart, Jr.
3896354 July 1975 Coleman et al.
3898541 August 1975 Weller
3921041 November 1975 Stockman
4023071 May 10, 1977 Fussell
4030190 June 21, 1977 Varker
4071878 January 31, 1978 Stynes
4081770 March 28, 1978 Mayer
4119084 October 10, 1978 Eckels
4135132 January 16, 1979 Tafjord
4139783 February 13, 1979 Engeler
4148003 April 3, 1979 Colburn et al.
4160220 July 3, 1979 Stachejko
4191986 March 4, 1980 ta Huang et al.
4198613 April 15, 1980 Whitley
4237522 December 2, 1980 Thompson
4259604 March 31, 1981 Aoki
4262317 April 14, 1981 Baumbach
4275945 June 30, 1981 Krantz et al.
4290041 September 15, 1981 Utsumi et al.
4292558 September 29, 1981 Flick et al.
4308509 December 29, 1981 Tsuchiya et al.
4312023 January 19, 1982 Frappart et al.
4312026 January 19, 1982 Iwaya et al.
4320364 March 16, 1982 Sakamoto et al.
4322698 March 30, 1982 Takahashi et al.
4328530 May 4, 1982 Bajorek et al.
4328531 May 4, 1982 Nagashima et al.
4335417 June 15, 1982 Sakshaug et al.
4342143 August 3, 1982 Jennings
4349862 September 14, 1982 Bajorek et al.
4353040 October 5, 1982 Krumm et al.
4353044 October 5, 1982 Nossek
4366456 December 28, 1982 Ueno et al.
4374368 February 15, 1983 Viola et al.
4375053 February 22, 1983 Viola et al.
4384263 May 17, 1983 Neuman et al.
4394639 July 19, 1983 McGalliard
4412146 October 25, 1983 Futterer et al.
4424552 January 3, 1984 Saint Marcoux
4441088 April 3, 1984 Anderson
4494083 January 15, 1985 Josefsson et al.
4494092 January 15, 1985 Griffin et al.
4498122 February 5, 1985 Rainal
4533931 August 6, 1985 Mandai et al.
4541035 September 10, 1985 Carlson et al.
4551746 November 5, 1985 Gilbert et al.
4551747 November 5, 1985 Gilbert et al.
4553114 November 12, 1985 English et al.
4556929 December 3, 1985 Tanaka et al.
4560962 December 24, 1985 Barrow
4563659 January 7, 1986 Sakamoto
4577214 March 18, 1986 Schaper
4586104 April 29, 1986 Standler
4587589 May 6, 1986 Marek
4590537 May 20, 1986 Sakamoto
4592606 June 3, 1986 Mudra
4597029 June 24, 1986 Kucharek et al.
4612140 September 16, 1986 Mandai
4612497 September 16, 1986 Ulmer
4626958 December 2, 1986 Lockard et al.
4628411 December 9, 1986 Balderes et al.
4633368 December 30, 1986 Frederick
4636752 January 13, 1987 Saito
4639826 January 27, 1987 Val et al.
4654694 March 31, 1987 Val
4658334 April 14, 1987 McSparran et al.
4665465 May 12, 1987 Tanabe
4667267 May 19, 1987 Hernandez et al.
4675644 June 23, 1987 Ott et al.
4682129 July 21, 1987 Bakermans et al.
4685025 August 4, 1987 Carlomagno
4688151 August 18, 1987 Kraus et al.
4694265 September 15, 1987 Kupper
4698721 October 6, 1987 Warren
4703386 October 27, 1987 Speet et al.
4706162 November 10, 1987 Hernandez et al.
4707671 November 17, 1987 Suzuki et al.
4710854 December 1, 1987 Yamada et al.
4712062 December 8, 1987 Takamine
4712540 December 15, 1987 Tucker et al.
4713540 December 15, 1987 Gilby et al.
4720690 January 19, 1988 Popek et al.
4720760 January 19, 1988 Starr
4725878 February 16, 1988 Miyauchi et al.
4729058 March 1, 1988 Gupta et al.
4734818 March 29, 1988 Hernandez et al.
4734819 March 29, 1988 Hernandez et al.
4739448 April 19, 1988 Rowe et al.
4746557 May 24, 1988 Sakamoto et al.
4752752 June 21, 1988 Okubo
4755910 July 5, 1988 Val
4760485 July 26, 1988 Ari et al.
4772225 September 20, 1988 Ulery
4777460 October 11, 1988 Okubo
4780598 October 25, 1988 Fahey et al.
4782311 November 1, 1988 Ookubo
4785135 November 15, 1988 Ecker et al.
4785271 November 15, 1988 Higgins
4789847 December 6, 1988 Sakamoto et al.
4793058 December 27, 1988 Venaleck
4794485 December 27, 1988 Bennett
4794499 December 27, 1988 Ott
4795658 January 3, 1989 Kano et al.
4799070 January 17, 1989 Nishikawa
4799128 January 17, 1989 Chen
4801904 January 31, 1989 Sakamoto et al.
4814295 March 21, 1989 Mehta
4814938 March 21, 1989 Arakawa et al.
4814941 March 21, 1989 Speet et al.
4819126 April 4, 1989 Kornrumpf et al.
4827327 May 2, 1989 Miyauchi et al.
4845606 July 4, 1989 Herbert
4847730 July 11, 1989 Konno et al.
4856102 August 8, 1989 Insetta et al.
4864465 September 5, 1989 Robbins
4875087 October 17, 1989 Miyauchi et al.
4884170 November 28, 1989 Ohki et al.
4891616 January 2, 1990 Renken et al.
4891686 January 2, 1990 Krausse
4901039 February 13, 1990 Corzine et al.
4904967 February 27, 1990 Morii et al.
4908586 March 13, 1990 Kling et al.
4908590 March 13, 1990 Sakamoto et al.
4909909 March 20, 1990 Florjancic et al.
4916576 April 10, 1990 Herbert et al.
4924340 May 8, 1990 Sweet
4942353 July 17, 1990 Herbert et al.
4945399 July 31, 1990 Brown et al.
4947286 August 7, 1990 Kaneko et al.
4949217 August 14, 1990 Ngo
4954929 September 4, 1990 Baran
4967315 October 30, 1990 Schelhorn
4975761 December 4, 1990 Chu
4978906 December 18, 1990 Herbert et al.
4982311 January 1, 1991 Dehaine et al.
4989117 January 29, 1991 Hernandez
4990202 February 5, 1991 Murata et al.
4994936 February 19, 1991 Hernandez
4999595 March 12, 1991 Azumi et al.
5012386 April 30, 1991 McShane et al.
5018047 May 21, 1991 Insetta et al.
5027253 June 25, 1991 Lauffer et al.
5029062 July 2, 1991 Capel
5034709 July 23, 1991 Azumi et al.
5034710 July 23, 1991 Kawaguchi
5034850 July 23, 1991 Hernandez et al.
5034851 July 23, 1991 Monsorno et al.
5040092 August 13, 1991 Katho et al.
5040093 August 13, 1991 Greuel
5041899 August 20, 1991 Oku et al.
5051712 September 24, 1991 Naito et al.
5059140 October 22, 1991 Philippson et al.
5065284 November 12, 1991 Hernandez
5073523 December 17, 1991 Yamada et al.
5075665 December 24, 1991 Taira et al.
5079069 January 7, 1992 Howard et al.
5079223 January 7, 1992 Maroni
5079669 January 7, 1992 Williams
5083101 January 21, 1992 Frederick
5089688 February 18, 1992 Fang et al.
5089880 February 18, 1992 Meyer et al.
5089881 February 18, 1992 Panicker
5095402 March 10, 1992 Hernandez et al.
5099387 March 24, 1992 Kato et al.
5105333 April 14, 1992 Yamano et al.
5107394 April 21, 1992 Naito et al.
5109206 April 28, 1992 Carlile
5115221 May 19, 1992 Cowman
5119062 June 2, 1992 Nakamura et al.
5140297 August 18, 1992 Jacobs et al.
5140496 August 18, 1992 Heinks et al.
5140497 August 18, 1992 Kato et al.
5142352 August 25, 1992 Chambers et al.
5142430 August 25, 1992 Anthony
5146191 September 8, 1992 Mandai et al.
5148005 September 15, 1992 Fang et al.
5150088 September 22, 1992 Virga et al.
5151770 September 29, 1992 Inoue
5153379 October 6, 1992 Guzuk et al.
5155464 October 13, 1992 Cowman et al.
5155655 October 13, 1992 Howard et al.
5159750 November 3, 1992 Dutta et al.
5161086 November 3, 1992 Howard et al.
5162977 November 10, 1992 Paurus et al.
5165055 November 17, 1992 Metsler
5166772 November 24, 1992 Soldner et al.
5167483 December 1, 1992 Gardiner
5170317 December 8, 1992 Yamada et al.
5172299 December 15, 1992 Yamada et al.
5173670 December 22, 1992 Naito et al.
5173767 December 22, 1992 Lange et al.
5177594 January 5, 1993 Chance et al.
5177663 January 5, 1993 Ingleson et al.
5177670 January 5, 1993 Shinohara et al.
5179362 January 12, 1993 Okochi et al.
5181859 January 26, 1993 Foreman et al.
5184210 February 2, 1993 Westbrook
5186647 February 16, 1993 Denkmann et al.
5187455 February 16, 1993 Mandai et al.
5206786 April 27, 1993 Lee
5208502 May 4, 1993 Yamashita et al.
5212402 May 18, 1993 Higgins, III
5216278 June 1, 1993 Lin et al.
5218230 June 8, 1993 Tamamura et al.
5219812 June 15, 1993 Doi et al.
5220480 June 15, 1993 Kershaw, Jr. et al.
5220483 June 15, 1993 Scott
5223741 June 29, 1993 Bechtel et al.
5225709 July 6, 1993 Nishiuma et al.
5227951 July 13, 1993 deNeuf et al.
5235208 August 10, 1993 Katoh
5236376 August 17, 1993 Cohen
5237204 August 17, 1993 Val
5243308 September 7, 1993 Shusterman et al.
5251092 October 5, 1993 Brady et al.
5257950 November 2, 1993 Lenker et al.
5261153 November 16, 1993 Lucas
5262611 November 16, 1993 Danysh et al.
5264983 November 23, 1993 Petrinec
5268810 December 7, 1993 DiMarco et al.
5272590 December 21, 1993 Hernandez
5278524 January 11, 1994 Mullen
5283717 February 1, 1994 Hundt
5290191 March 1, 1994 Foreman et al.
5294751 March 15, 1994 Kamada
5294826 March 15, 1994 Marcantonio et al.
5299956 April 5, 1994 Brownell et al.
5300760 April 5, 1994 Batliwalla et al.
5303419 April 12, 1994 Ittipiboon et al.
5309024 May 3, 1994 Hirano
5309121 May 3, 1994 Kobayashi et al.
5310363 May 10, 1994 Brownell et al.
5311408 May 10, 1994 Ferchau et al.
5313176 May 17, 1994 Upadhyay
5319525 June 7, 1994 Lightfoot
5321373 June 14, 1994 Shusterman et al.
5321573 June 14, 1994 Person et al.
5326284 July 5, 1994 Bohbot et al.
5331505 July 19, 1994 Wilheim
5333095 July 26, 1994 Stevenson et al.
5337028 August 9, 1994 White
5338970 August 16, 1994 Boyle et al.
5349314 September 20, 1994 Shimizu et al.
5353189 October 4, 1994 Tomlinson
5353202 October 4, 1994 Ansell et al.
5355016 October 11, 1994 Swirbel et al.
5357568 October 18, 1994 Pelegris
5362249 November 8, 1994 Carter
5362254 November 8, 1994 Siemon et al.
5365203 November 15, 1994 Nakamura et al.
5367430 November 22, 1994 DeVoe et al.
5369379 November 29, 1994 Fujiki
5369390 November 29, 1994 Lin et al.
5369545 November 29, 1994 Bhattacharyya et al.
5371653 December 6, 1994 Kametani et al.
5374909 December 20, 1994 Hirai et al.
5376759 December 27, 1994 Marx et al.
5378407 January 3, 1995 Chandler et al.
5382928 January 17, 1995 Davis et al.
5382938 January 17, 1995 Hansson et al.
5386335 January 31, 1995 Amano et al.
5386627 February 7, 1995 Booth et al.
5396201 March 7, 1995 Ishizaki et al.
5396397 March 7, 1995 McClanahan et al.
5399898 March 21, 1995 Rostoker
5401952 March 28, 1995 Sugawa
5402318 March 28, 1995 Otsuka et al.
5404044 April 4, 1995 Booth et al.
5405466 April 11, 1995 Naito et al.
5414299 May 9, 1995 Wang et al.
5414393 May 9, 1995 Rose et al.
5414587 May 9, 1995 Kiser et al.
5420553 May 30, 1995 Sakamoto et al.
5426560 June 20, 1995 Amaya et al.
5428885 July 4, 1995 Takaya et al.
5430605 July 4, 1995 deNeuf et al.
5432484 July 11, 1995 Klas et al.
5446625 August 29, 1995 Urbish et al.
5448445 September 5, 1995 Yamate et al.
5450278 September 12, 1995 Lee et al.
5451919 September 19, 1995 Chu et al.
RE35064 October 17, 1995 Hernandez
5455734 October 3, 1995 Foreman et al.
5457340 October 10, 1995 Templeton et al.
5461351 October 24, 1995 Shusterman
5463232 October 31, 1995 Yamashita et al.
5467064 November 14, 1995 Gu
5468997 November 21, 1995 Imai et al.
5471027 November 28, 1995 Call et al.
5471035 November 28, 1995 Holmes
5471181 November 28, 1995 Park
5473813 December 12, 1995 Chobot et al.
5474458 December 12, 1995 Vafi et al.
5475262 December 12, 1995 Wang et al.
5475565 December 12, 1995 Bhattacharyya et al.
5475606 December 12, 1995 Muyshondt et al.
5477933 December 26, 1995 Nguyen
5481238 January 2, 1996 Carsten et al.
5483407 January 9, 1996 Anastasio et al.
5483413 January 9, 1996 Babb
5488540 January 30, 1996 Hatta
5489882 February 6, 1996 Ueno
5491299 February 13, 1996 Naylor et al.
5491301 February 13, 1996 Akiba et al.
5493259 February 20, 1996 Blalock et al.
5493260 February 20, 1996 Park
5495180 February 27, 1996 Huang et al.
5499445 March 19, 1996 Boyle et al.
5500629 March 19, 1996 Meyer
5500785 March 19, 1996 Funada
5500789 March 19, 1996 Miller et al.
5506755 April 9, 1996 Miyagi et al.
5508938 April 16, 1996 Wheeler
5512196 April 30, 1996 Mantese et al.
5519650 May 21, 1996 Ichimura et al.
5528083 June 18, 1996 Malladi et al.
5530288 June 25, 1996 Stone
5531003 July 2, 1996 Seifried et al.
5534837 July 9, 1996 Brandt
5535101 July 9, 1996 Miles et al.
5536978 July 16, 1996 Cooper et al.
5541482 July 30, 1996 Siao
5544002 August 6, 1996 Iwaya et al.
5546058 August 13, 1996 Azuma et al.
5548255 August 20, 1996 Spielman
5555150 September 10, 1996 Newman, Jr.
5556811 September 17, 1996 Agatstein et al.
5557142 September 17, 1996 Gilmore et al.
5566040 October 15, 1996 Cosquer et al.
5568348 October 22, 1996 Foreman et al.
5570278 October 29, 1996 Cross
5574630 November 12, 1996 Kresge et al.
5583359 December 10, 1996 Ng et al.
5583470 December 10, 1996 Okubo
5583738 December 10, 1996 Kohno et al.
5583739 December 10, 1996 Vu et al.
5586007 December 17, 1996 Funada
5586011 December 17, 1996 Alexander
5587333 December 24, 1996 Johansson et al.
5587920 December 24, 1996 Muyshondt et al.
5590016 December 31, 1996 Fujishiro
5590030 December 31, 1996 Kametani et al.
5592391 January 7, 1997 Muyshondt et al.
5604668 February 18, 1997 Wohrstein et al.
5610796 March 11, 1997 Lavene
5612657 March 18, 1997 Kledzik
5614111 March 25, 1997 Lavene
5614881 March 25, 1997 Duggal et al.
5618185 April 8, 1997 Aekins
5619079 April 8, 1997 Wiggins et al.
5623160 April 22, 1997 Liberkowski
5624592 April 29, 1997 Paustian
5625166 April 29, 1997 Natarajan
5625225 April 29, 1997 Huang et al.
5633479 May 27, 1997 Hirano
5634268 June 3, 1997 Dalal et al.
5635669 June 3, 1997 Kubota et al.
5635767 June 3, 1997 Wenzel et al.
5635775 June 3, 1997 Colburn et al.
5640048 June 17, 1997 Selna
5641988 June 24, 1997 Huang et al.
5644468 July 1, 1997 Wink et al.
5645746 July 8, 1997 Walsh
5647766 July 15, 1997 Nguyen
5647767 July 15, 1997 Scheer et al.
5659455 August 19, 1997 Herbert
5668511 September 16, 1997 Furutani et al.
5672911 September 30, 1997 Patil et al.
5682303 October 28, 1997 Goad
5692298 December 2, 1997 Goetz et al.
5700167 December 23, 1997 Pharney et al.
5708296 January 13, 1998 Bhansali
5708553 January 13, 1998 Hung
5717249 February 10, 1998 Yoshikawa et al.
5719440 February 17, 1998 Moden
5719450 February 17, 1998 Vora
5719477 February 17, 1998 Tomihari
5719750 February 17, 1998 Iwane
5726612 March 10, 1998 Mandai et al.
5731960 March 24, 1998 Fung
5734198 March 31, 1998 Stave
5741729 April 21, 1998 Selna
5742210 April 21, 1998 Chaturvedi et al.
5742470 April 21, 1998 Raets
5745333 April 28, 1998 Frankeny et al.
5751539 May 12, 1998 Stevenson et al.
5756380 May 26, 1998 Berg et al.
5757252 May 26, 1998 Cho et al.
5761049 June 2, 1998 Yoshidome et al.
5764489 June 9, 1998 Leigh et al.
5767446 June 16, 1998 Ha et al.
5770476 June 23, 1998 Stone
5777383 July 7, 1998 Stager et al.
5786238 July 28, 1998 Pai et al.
5786630 July 28, 1998 Bhansali et al.
5789999 August 4, 1998 Barnett et al.
5790368 August 4, 1998 Naito et al.
5796170 August 18, 1998 Marcantonio
5796568 August 18, 1998 Baiatu
5796595 August 18, 1998 Cross
5797770 August 25, 1998 Davis et al.
5801579 September 1, 1998 Le et al.
5801597 September 1, 1998 Carter et al.
5808873 September 15, 1998 Celaya et al.
5812380 September 22, 1998 Frech et al.
5815050 September 29, 1998 Brooks et al.
5815051 September 29, 1998 Hamasaki et al.
5815373 September 29, 1998 Johnsen et al.
5817130 October 6, 1998 Cox et al.
5818313 October 6, 1998 Estes et al.
5822174 October 13, 1998 Yamate et al.
5825084 October 20, 1998 Lau et al.
5825628 October 20, 1998 Garbelli et al.
5827382 October 27, 1998 Ogawa et al.
5828093 October 27, 1998 Naito et al.
5828272 October 27, 1998 Romerein et al.
5828555 October 27, 1998 Itoh
5831489 November 3, 1998 Wire
5834992 November 10, 1998 Kato et al.
5835338 November 10, 1998 Suzuki et al.
5838216 November 17, 1998 White et al.
5838551 November 17, 1998 Chan
5847936 December 8, 1998 Forehand et al.
5854534 December 29, 1998 Beilin et al.
5864089 January 26, 1999 Rainal
5867361 February 2, 1999 Wolf et al.
5870272 February 9, 1999 Seifried et al.
5870273 February 9, 1999 Sogabe et al.
5872695 February 16, 1999 Fasano et al.
5875099 February 23, 1999 Maesaka et al.
5880925 March 9, 1999 DuPre et al.
5889445 March 30, 1999 Ritter et al.
5892415 April 6, 1999 Okamura
5894252 April 13, 1999 Oida
5895990 April 20, 1999 Lau
5898403 April 27, 1999 Saitoh et al.
5898562 April 27, 1999 Cain et al.
5898576 April 27, 1999 Lockwood et al.
5900350 May 4, 1999 Provost et al.
5905627 May 18, 1999 Brendel et al.
5907265 May 25, 1999 Sakuragawa et al.
5908151 June 1, 1999 Elias
5909155 June 1, 1999 Anderson et al.
5909350 June 1, 1999 Anthony
5910755 June 8, 1999 Mishiro et al.
5910879 June 8, 1999 Herbert
5912809 June 15, 1999 Steigerwald et al.
5917388 June 29, 1999 Tronche et al.
5923523 July 13, 1999 Herbert
5923540 July 13, 1999 Asada et al.
5925925 July 20, 1999 Dehaine et al.
5926377 July 20, 1999 Nakao et al.
5928076 July 27, 1999 Clements et al.
5929729 July 27, 1999 Swarup
5955930 September 21, 1999 Anderson et al.
5959829 September 28, 1999 Stevenson et al.
5959846 September 28, 1999 Noguchi et al.
5969461 October 19, 1999 Anderson et al.
5969583 October 19, 1999 Hutchison
5973906 October 26, 1999 Stevenson et al.
5973928 October 26, 1999 Blasi et al.
5977845 November 2, 1999 Kitahara
5978231 November 2, 1999 Tohya et al.
5980718 November 9, 1999 Van Konynenburg et al.
5982018 November 9, 1999 Wark et al.
5986340 November 16, 1999 Mostafazadeh et al.
5995352 November 30, 1999 Gumley
5995591 November 30, 1999 Halim
5999067 December 7, 1999 D'Ostilio
5999398 December 7, 1999 Makl et al.
6004752 December 21, 1999 Loewy et al.
6013957 January 11, 2000 Puzo et al.
6016095 January 18, 2000 Herbert
6018448 January 25, 2000 Anthony
6021564 February 8, 2000 Hanson
6023210 February 8, 2000 Tulintseff
6023406 February 8, 2000 Kinoshita et al.
6031710 February 29, 2000 Wolf et al.
6034576 March 7, 2000 Kuth
6034864 March 7, 2000 Naito et al.
6037846 March 14, 2000 Oberhammer
6038121 March 14, 2000 Naito et al.
6042685 March 28, 2000 Shinada et al.
6046898 April 4, 2000 Seymour et al.
6052038 April 18, 2000 Savicki
6052272 April 18, 2000 Kuroda et al.
6054754 April 25, 2000 Bissey
6054758 April 25, 2000 Lamson
6061227 May 9, 2000 Nogi
6061228 May 9, 2000 Palmer et al.
6064286 May 16, 2000 Ziegner et al.
6069786 May 30, 2000 Horie et al.
6072687 June 6, 2000 Naito et al.
6072690 June 6, 2000 Farooq et al.
6075211 June 13, 2000 Tohya et al.
6075285 June 13, 2000 Taylor et al.
6078117 June 20, 2000 Perrin et al.
6078229 June 20, 2000 Funada et al.
6084779 July 4, 2000 Fang
6088235 July 11, 2000 Chiao et al.
6091310 July 18, 2000 Utsumi et al.
6092269 July 25, 2000 Yializis et al.
6094112 July 25, 2000 Goldberger et al.
6094339 July 25, 2000 Evans
6097260 August 1, 2000 Whybrew et al.
6097581 August 1, 2000 Anthony
6104258 August 15, 2000 Novak
6104599 August 15, 2000 Ahiko et al.
6108448 August 22, 2000 Song et al.
6111479 August 29, 2000 Myohga et al.
6120326 September 19, 2000 Brooks
6121761 September 19, 2000 Herbert
6125044 September 26, 2000 Cherniski
6130585 October 10, 2000 Whybrew et al.
6133805 October 17, 2000 Jain et al.
6137161 October 24, 2000 Gilliland et al.
6137392 October 24, 2000 Herbert
6142831 November 7, 2000 Ashman et al.
6144547 November 7, 2000 Retseptor
6147587 November 14, 2000 Hadano et al.
6150895 November 21, 2000 Steigerwald et al.
6157528 December 5, 2000 Anthony
6157547 December 5, 2000 Brown et al.
6160705 December 12, 2000 Stearns et al.
6163454 December 19, 2000 Strickler
6163456 December 19, 2000 Suzuki et al.
6165814 December 26, 2000 Wark et al.
6175287 January 16, 2001 Lampen et al.
6180588 January 30, 2001 Walters
6181004 January 30, 2001 Koontz et al.
6181231 January 30, 2001 Bartilson
6183685 February 6, 2001 Cowman et al.
6184477 February 6, 2001 Tanahashi
6184769 February 6, 2001 Nakamura et al.
6185091 February 6, 2001 Tanahashi et al.
6188565 February 13, 2001 Naito et al.
6191472 February 20, 2001 Mazumder
6191475 February 20, 2001 Skinner et al.
6191479 February 20, 2001 Herrell et al.
6191669 February 20, 2001 Shigemura
6191932 February 20, 2001 Kuroda et al.
6191933 February 20, 2001 Ishigaki et al.
6195269 February 27, 2001 Hino
6198123 March 6, 2001 Linder et al.
6198362 March 6, 2001 Harada et al.
6200400 March 13, 2001 Farooq et al.
6204448 March 20, 2001 Garland et al.
6205014 March 20, 2001 Inomata et al.
6207081 March 27, 2001 Sasaki et al.
6208063 March 27, 2001 Horikawa
6208225 March 27, 2001 Miller
6208226 March 27, 2001 Chen et al.
6208494 March 27, 2001 Nakura et al.
6208495 March 27, 2001 Wieloch et al.
6208501 March 27, 2001 Ingalls et al.
6208502 March 27, 2001 Hudis et al.
6208503 March 27, 2001 Shimada et al.
6208521 March 27, 2001 Nakatsuka
6208525 March 27, 2001 Imasu et al.
6211754 April 3, 2001 Nishida et al.
6212060 April 3, 2001 Liu
6212078 April 3, 2001 Hunt et al.
6215373 April 10, 2001 Novak et al.
6215647 April 10, 2001 Naito et al.
6215649 April 10, 2001 Appelt et al.
6218631 April 17, 2001 Hetzel et al.
6219240 April 17, 2001 Sasov
6222427 April 24, 2001 Kato et al.
6222431 April 24, 2001 Ishizaki et al.
6225876 May 1, 2001 Akino et al.
6226169 May 1, 2001 Naito et al.
6226182 May 1, 2001 Maehara
6229226 May 8, 2001 Kramer et al.
6236572 May 22, 2001 Teshome et al.
6240621 June 5, 2001 Nellissen et al.
6243253 June 5, 2001 DuPre et al.
6249047 June 19, 2001 Corisis
6249439 June 19, 2001 DeMore et al.
6252161 June 26, 2001 Hailey et al.
6252761 June 26, 2001 Branchevsky
6262895 July 17, 2001 Forthun
6266228 July 24, 2001 Naito et al.
6266229 July 24, 2001 Naito et al.
6272003 August 7, 2001 Schaper
6281704 August 28, 2001 Ngai et al.
6282074 August 28, 2001 Anthony
6282079 August 28, 2001 Nagakari et al.
6285109 September 4, 2001 Katagiri et al.
6285542 September 4, 2001 Kennedy, III et al.
6288344 September 11, 2001 Youker et al.
6288906 September 11, 2001 Sprietsma et al.
6292350 September 18, 2001 Naito et al.
6292351 September 18, 2001 Ahiko et al.
6300846 October 9, 2001 Brunker
6307450 October 23, 2001 Takahashi et al.
6309245 October 30, 2001 Sweeney
6310286 October 30, 2001 Troxel et al.
6310759 October 30, 2001 Ishigaki et al.
6313584 November 6, 2001 Johnson et al.
6320547 November 20, 2001 Fathy et al.
6323116 November 27, 2001 Lamson
6324047 November 27, 2001 Hayworth
6324048 November 27, 2001 Liu
6325672 December 4, 2001 Belopolsky et al.
6327134 December 4, 2001 Kuroda et al.
6327137 December 4, 2001 Yamamoto et al.
6331808 December 18, 2001 Mikami et al.
6331926 December 18, 2001 Anthony
6331930 December 18, 2001 Kuroda
6342681 January 29, 2002 Goldberger et al.
6344961 February 5, 2002 Naito et al.
6346743 February 12, 2002 Figueroa et al.
6351120 February 26, 2002 Goldfine et al.
6351194 February 26, 2002 Takahashi et al.
6351369 February 26, 2002 Kuroda et al.
6352914 March 5, 2002 Ball et al.
6353375 March 5, 2002 Kurata
6353540 March 5, 2002 Akiba et al.
6365828 April 2, 2002 Kinoshita et al.
6367133 April 9, 2002 Ikada et al.
6370010 April 9, 2002 Kuroda et al.
6370011 April 9, 2002 Naito et al.
6370937 April 16, 2002 Hsu
6373349 April 16, 2002 Gilbert
6373673 April 16, 2002 Anthony
6373711 April 16, 2002 Yamauchi et al.
6377439 April 23, 2002 Sekidou et al.
6381153 April 30, 2002 Brussels
6388207 May 14, 2002 Figueroa et al.
6388856 May 14, 2002 Anthony
6388865 May 14, 2002 Honda et al.
6392502 May 21, 2002 Sweeney et al.
6392868 May 21, 2002 Ohya et al.
6395996 May 28, 2002 Tsai et al.
6396088 May 28, 2002 Kitsukawa et al.
6407906 June 18, 2002 Ahiko et al.
6414572 July 2, 2002 Satoh et al.
6420941 July 16, 2002 Okada et al.
6430025 August 6, 2002 Naito et al.
6430030 August 6, 2002 Farooq et al.
6437240 August 20, 2002 Smith
6437409 August 20, 2002 Fujii
6448873 September 10, 2002 Mostov
6449828 September 17, 2002 Pahl et al.
6456481 September 24, 2002 Stevenson
6462628 October 8, 2002 Kondo et al.
6462932 October 8, 2002 Naito et al.
6466107 October 15, 2002 Yamamoto
6469595 October 22, 2002 Anthony et al.
6473292 October 29, 2002 Yoshida et al.
6475854 November 5, 2002 Narwankar et al.
6477034 November 5, 2002 Chakravorty et al.
6480425 November 12, 2002 Yanagisawa et al.
6483394 November 19, 2002 Kim
6493202 December 10, 2002 Kappel et al.
6496354 December 17, 2002 Naito et al.
6498710 December 24, 2002 Anthony
6501344 December 31, 2002 Ikata et al.
6504451 January 7, 2003 Yamaguchi
6507200 January 14, 2003 Brandelik et al.
6509640 January 21, 2003 Li et al.
6509807 January 21, 2003 Anthony et al.
6510038 January 21, 2003 Satou et al.
6522182 February 18, 2003 Tomita et al.
6522516 February 18, 2003 Anthony
6525628 February 25, 2003 Ritter et al.
6525635 February 25, 2003 Murata et al.
6532143 March 11, 2003 Figueroa et al.
6534787 March 18, 2003 Hsu
6538527 March 25, 2003 Hidaka
6549389 April 15, 2003 Anthony et al.
6549395 April 15, 2003 Naito et al.
6559484 May 6, 2003 Li et al.
6563688 May 13, 2003 Anthony et al.
6567257 May 20, 2003 Brown
6573805 June 3, 2003 Hidaka et al.
6577493 June 10, 2003 Honda et al.
6580595 June 17, 2003 Anthony et al.
6587016 July 1, 2003 Kadota
6587327 July 1, 2003 Devoe et al.
6594128 July 15, 2003 Anthony
6594136 July 15, 2003 Kuroda et al.
6603372 August 5, 2003 Ishizaki et al.
6603646 August 5, 2003 Anthony et al.
6606011 August 12, 2003 Anthony et al.
6606237 August 12, 2003 Naito et al.
6608538 August 19, 2003 Wang
6611419 August 26, 2003 Chakravorty
6618268 September 9, 2003 Dibene, II et al.
6618943 September 16, 2003 Ashe et al.
6624692 September 23, 2003 Suzuki et al.
6633528 October 14, 2003 Watanabe
6636406 October 21, 2003 Anthony
6638686 October 28, 2003 Sawada et al.
6643903 November 11, 2003 Stevenson et al.
6650203 November 18, 2003 Gerstenberg et al.
6650525 November 18, 2003 Anthony
6665053 December 16, 2003 Korenaga
6674343 January 6, 2004 Gould et al.
6687108 February 3, 2004 Anthony et al.
6696952 February 24, 2004 Zirbes
6700181 March 2, 2004 Coccioli
6704190 March 9, 2004 Honda et al.
6707685 March 16, 2004 Kabumoto et al.
6710263 March 23, 2004 Kobayashi et al.
6710997 March 23, 2004 Honda et al.
6717301 April 6, 2004 De Daran et al.
6738249 May 18, 2004 Anthony et al.
6750739 June 15, 2004 Enokihara et al.
6767787 July 27, 2004 Koh et al.
6768630 July 27, 2004 Togashi
6794961 September 21, 2004 Nagaishi et al.
6801422 October 5, 2004 Mosley
6806806 October 19, 2004 Anthony
6812411 November 2, 2004 Belau et al.
6823730 November 30, 2004 Buck et al.
6828666 December 7, 2004 Herrell et al.
6849945 February 1, 2005 Horiuchi et al.
6873513 March 29, 2005 Anthony
6879481 April 12, 2005 Honda et al.
6894884 May 17, 2005 Anthony, Jr. et al.
6909593 June 21, 2005 Kuroda et al.
6942469 September 13, 2005 Seale et al.
6950293 September 27, 2005 Anthony
6954346 October 11, 2005 Anthony
6956174 October 18, 2005 Khandros et al.
6980414 December 27, 2005 Sutardja
6995983 February 7, 2006 Anthony et al.
7042303 May 9, 2006 Anthony et al.
7042703 May 9, 2006 Anthony et al.
7050284 May 23, 2006 Anthony
7106570 September 12, 2006 Anthony, Jr. et al.
7109569 September 19, 2006 Breisch et al.
7110227 September 19, 2006 Anthony et al.
7110235 September 19, 2006 Anthony, Jr. et al.
7113383 September 26, 2006 Anthony et al.
7141899 November 28, 2006 Anthony et al.
7180718 February 20, 2007 Anthony et al.
7193831 March 20, 2007 Anthony
7224564 May 29, 2007 Anthony
7262949 August 28, 2007 Anthony
7274549 September 25, 2007 Anthony
7301748 November 27, 2007 Anthony et al.
7321485 January 22, 2008 Anthony et al.
7336467 February 26, 2008 Anthony et al.
7336468 February 26, 2008 Anthony et al.
7423860 September 9, 2008 Anthony et al.
7428134 September 23, 2008 Anthony
7433168 October 7, 2008 Anthony
7440252 October 21, 2008 Anthony
7443647 October 28, 2008 Anthony
7586728 September 8, 2009 Anthony
7593208 September 22, 2009 Anthony et al.
7609500 October 27, 2009 Anthony et al.
7609501 October 27, 2009 Anthony et al.
7630188 December 8, 2009 Anthony
7675729 March 9, 2010 Anthony et al.
7688565 March 30, 2010 Anthony et al.
7733621 June 8, 2010 Anthony et al.
7768763 August 3, 2010 Anthony et al.
7782587 August 24, 2010 Anthony et al.
7817397 October 19, 2010 Anthony
7894176 February 22, 2011 Anthony
7916444 March 29, 2011 Anthony et al.
7920367 April 5, 2011 Anthony et al.
7974062 July 5, 2011 Anthony et al.
8004812 August 23, 2011 Anthony et al.
8014119 September 6, 2011 Anthony
8018706 September 13, 2011 Anthony et al.
8023241 September 20, 2011 Anthony et al.
8026777 September 27, 2011 Anthony
8547677 October 1, 2013 Anthony et al.
8587915 November 19, 2013 Anthony et al.
20010001989 May 31, 2001 Smith
20010002105 May 31, 2001 Brandelik et al.
20010002624 June 7, 2001 Khandros et al.
20010008288 July 19, 2001 Kimura et al.
20010008302 July 19, 2001 Murakami et al.
20010008478 July 19, 2001 McIntosh et al.
20010008509 July 19, 2001 Watanabe
20010009496 July 26, 2001 Kappel et al.
20010010444 August 2, 2001 Pahl et al.
20010011763 August 9, 2001 Ushijima et al.
20010011934 August 9, 2001 Yamamoto
20010011937 August 9, 2001 Satoh et al.
20010013626 August 16, 2001 Fujii
20010015643 August 23, 2001 Goldfine et al.
20010015683 August 23, 2001 Mikami et al.
20010017576 August 30, 2001 Kondo et al.
20010017579 August 30, 2001 Kurata
20010019869 September 6, 2001 Hsu
20010020879 September 13, 2001 Takahashi et al.
20010021097 September 13, 2001 Ohya et al.
20010022547 September 20, 2001 Murata et al.
20010023983 September 27, 2001 Kobayashi et al.
20010024148 September 27, 2001 Gerstenberg et al.
20010028581 October 11, 2001 Yanagisawa et al.
20010029648 October 18, 2001 Ikada et al.
20010031191 October 18, 2001 Korenaga
20010033664 October 25, 2001 Poux et al.
20010035801 November 1, 2001 Gilbert
20010035802 November 1, 2001 Kadota
20010035805 November 1, 2001 Suzuki et al.
20010037680 November 8, 2001 Buck et al.
20010039834 November 15, 2001 Hsu
20010040484 November 15, 2001 Kim
20010040487 November 15, 2001 Ikata et al.
20010040488 November 15, 2001 Gould et al.
20010041305 November 15, 2001 Sawada et al.
20010043100 November 22, 2001 Tomita et al.
20010043129 November 22, 2001 Hidaka et al.
20010043450 November 22, 2001 Seale et al.
20010043453 November 22, 2001 Narwankar et al.
20010045810 November 29, 2001 Poon et al.
20010048581 December 6, 2001 Anthony et al.
20010048593 December 6, 2001 Yamauchi et al.
20010048906 December 6, 2001 Lau et al.
20010050550 December 13, 2001 Yoshida et al.
20010050600 December 13, 2001 Anthony et al.
20010050837 December 13, 2001 Stevenson et al.
20010052833 December 20, 2001 Enokihara et al.
20010054512 December 27, 2001 Belau et al.
20010054734 December 27, 2001 Koh et al.
20010054756 December 27, 2001 Horiuchi et al.
20010054936 December 27, 2001 Okada et al.
20020000521 January 3, 2002 Brown
20020000583 January 3, 2002 Kitsukawa et al.
20020000821 January 3, 2002 Haga et al.
20020000893 January 3, 2002 Hidaka et al.
20020000895 January 3, 2002 Takahashi et al.
20020003454 January 10, 2002 Sweeney et al.
20020005880 January 17, 2002 Ashe et al.
20020024787 February 28, 2002 Anthony
20020027263 March 7, 2002 Anthony et al.
20020027760 March 7, 2002 Anthony
20020044401 April 18, 2002 Anthony et al.
20020075096 June 20, 2002 Anthony
20020079116 June 27, 2002 Anthony
20020089812 July 11, 2002 Anthony et al.
20020113663 August 22, 2002 Anthony et al.
20020122286 September 5, 2002 Anthony
20020131231 September 19, 2002 Anthony
20020149900 October 17, 2002 Anthony
20020158515 October 31, 2002 Anthony, Jr. et al.
20020186100 December 12, 2002 Anthony et al.
20030029632 February 13, 2003 Anthony, Jr. et al.
20030029635 February 13, 2003 Anthony, Jr. et al.
20030048029 March 13, 2003 DeDaran et al.
20030067730 April 10, 2003 Anthony et al.
20030161086 August 28, 2003 Anthony
20030202312 October 30, 2003 Anthony et al.
20030206388 November 6, 2003 Anthony et al.
20030210125 November 13, 2003 Anthony
20030231451 December 18, 2003 Anthony
20030231456 December 18, 2003 Anthony et al.
20040004802 January 8, 2004 Anthony et al.
20040008466 January 15, 2004 Anthony et al.
20040027771 February 12, 2004 Anthony
20040032304 February 19, 2004 Anthony et al.
20040054426 March 18, 2004 Anthony
20040085699 May 6, 2004 Anthony
20040105205 June 3, 2004 Anthony et al.
20040124949 July 1, 2004 Anthony et al.
20040130840 July 8, 2004 Anthony
20040218332 November 4, 2004 Anthony et al.
20040226733 November 18, 2004 Anthony et al.
20050016761 January 27, 2005 Anthony, Jr. et al.
20050018374 January 27, 2005 Anthony
20050063127 March 24, 2005 Anthony
20050248900 November 10, 2005 Anthony
20050286198 December 29, 2005 Anthony et al.
20060023385 February 2, 2006 Anthony et al.
20060139836 June 29, 2006 Anthony
20060139837 June 29, 2006 Anthony et al.
20060193051 August 31, 2006 Anthony et al.
20060202414 September 14, 2006 Chen
20060203414 September 14, 2006 Anthony
20070019352 January 25, 2007 Anthony
20070047177 March 1, 2007 Anthony
20070057359 March 15, 2007 Anthony et al.
20070103839 May 10, 2007 Anthony et al.
20070109709 May 17, 2007 Anthony et al.
20080160681 July 3, 2008 Anthony et al.
20090321127 December 31, 2009 Anthony et al.
20100078199 April 1, 2010 Anthony et al.
20100180438 July 22, 2010 Anthony et al.
20100294555 November 25, 2010 Anthony et al.
20100307810 December 9, 2010 Anthony et al.
20100319978 December 23, 2010 Anthony et al.
20110032657 February 10, 2011 Anthony
20110141653 June 16, 2011 Anthony
20110174523 July 21, 2011 Anthony et al.
20110192642 August 11, 2011 Anthony et al.
20120000045 January 5, 2012 Anthony et al.
20120023741 February 2, 2012 Anthony et al.
20120023742 February 2, 2012 Anthony et al.
20120034774 February 9, 2012 Anthony et al.
Foreign Patent Documents
747079 November 1966 CA
1237534 May 1988 CA
197 28 692 January 1999 DE
198 57 043 March 2000 DE
295948 December 1988 EP
563873 October 1993 EP
279769 September 1994 EP
0623363 November 1994 EP
98915364 November 1994 EP
763867 March 1997 EP
0776016 May 1997 EP
872888 October 1998 EP
0933871 August 1999 EP
1022751 July 2000 EP
1024507 August 2000 EP
1061535 December 2000 EP
1128434 August 2001 EP
735606 January 2002 EP
1873872 December 2008 EP
2496970 June 1982 FR
2606207 May 1988 FR
2765417 December 1998 FR
2808135 October 2001 FR
2217136 April 1988 GB
2310967 March 2000 GB
2341980 March 2000 GB
06-053078 February 1994 JO
57-172130 October 1982 JP
63-269509 November 1988 JP
1-27251 January 1989 JP
01-120805 May 1989 JP
01-212415 August 1989 JP
02-267879 November 1990 JP
03-018112 January 1991 JP
03-071614 March 1991 JP
05-205966 August 1993 JP
5-283284 October 1993 JP
05-299292 November 1993 JP
06-020870 January 1994 JP
06-053048 February 1994 JP
06-053049 February 1994 JP
06-053075 February 1994 JP
06-053077 February 1994 JP
06-053078 February 1994 JP
06-084695 March 1994 JP
06-120704 April 1994 JP
06-151014 May 1994 JP
06-151244 May 1994 JP
06-151245 May 1994 JP
06-231995 August 1994 JP
06-251981 September 1994 JP
06-275463 September 1994 JP
6-302471 October 1994 JP
06-325977 November 1994 JP
11-214244 November 1994 JP
06-267790 December 1994 JP
07-022757 January 1995 JP
07-122757 May 1995 JP
07 161568 June 1995 JP
07-201651 August 1995 JP
07-202477 August 1995 JP
07-235406 September 1995 JP
07-235852 September 1995 JP
07-235862 September 1995 JP
07-240651 September 1995 JP
07-263871 October 1995 JP
07-263280 November 1995 JP
08-97328 April 1996 JP
08-124795 May 1996 JP
08-163122 June 1996 JP
08-172025 July 1996 JP
08-181035 July 1996 JP
8172025 July 1996 JP
08-273973 October 1996 JP
09-232185 September 1997 JP
9-266130 October 1997 JP
09-275145 October 1997 JP
09-284076 October 1997 JP
09-284077 October 1997 JP
09-284078 October 1997 JP
9-284078 October 1997 JP
09-293987 November 1997 JP
9-294041 November 1997 JP
10-12490 January 1998 JP
10-41637 February 1998 JP
10-41677 February 1998 JP
10-223470 August 1998 JP
11-21456 April 1999 JP
11-97291 April 1999 JP
11-102839 April 1999 JP
11-214256 August 1999 JP
11-215256 August 1999 JP
11-223396 August 1999 JP
11-219824 October 1999 JP
11-294908 October 1999 JP
11-305302 November 1999 JP
11-319222 November 1999 JP
11-345273 December 1999 JP
2000-188218 April 2000 JP
00-188218 July 2000 JP
2000-243646 August 2000 JP
00-261235 September 2000 JP
00-299249 October 2000 JP
2000-286665 October 2000 JP
WO9007785 July 1990 WO
WO 91/15046 October 1991 WO
WO9622008 July 1996 WO
WO9641376 December 1996 WO
WO 97/20332 June 1997 WO
WO 97/43786 November 1997 WO
WO 98/45921 October 1998 WO
WO 99/04457 January 1999 WO
WO 99/19982 April 1999 WO
WO 99/37008 July 1999 WO
WO 99/52210 October 1999 WO
WO 00/16446 March 2000 WO
WO 00/65740 November 2000 WO
WO 00/74197 December 2000 WO
WO 00/77907 December 2000 WO
01/06631 January 2001 WO
WO 01/10000 February 2001 WO
WO 01/41232 June 2001 WO
WO 01/41233 June 2001 WO
WO 01/45119 June 2001 WO
WO 01/71908 September 2001 WO
WO 01/75916 October 2001 WO
WO 01/84581 November 2001 WO
WO 01/86774 November 2001 WO
WO 02/59401 January 2002 WO
WO 02/11160 February 2002 WO
WO 02/15360 February 2002 WO
WO 02/27794 April 2002 WO
WO 02/33798 April 2002 WO
WO 02/45233 June 2002 WO
WO 02/065606 August 2002 WO
WO 02/080330 October 2002 WO
WO 03/005541 January 2003 WO
WO 2004/070905 August 2004 WO
WO 2005/002018 January 2005 WO
WO 2005/015719 February 2005 WO
WO 2005/065097 July 2005 WO
WO 2006/093830 September 2006 WO
WO 2006/093831 September 2006 WO
WO 2006/099297 September 2006 WO
WO 2006/104613 October 2006 WO
WO 2007/103965 September 2007 WO
Other references
  • Oct. 1, 2002, PCT International Search Report for PCT/US01/48861.
  • Jan. 2, 2003, PCT International Search Report for PCT/US01/44681.
  • Greb, “An Intuitive Approach to EM Fields,” EMC Test & Design, Jan. 1, 1994, pp. 30-33.
  • Greb, “An Intuitive Approach to EM Coupling,” EMC Test & Design, Dec. 1, 1993, pp. 20-25.
  • Sakamoto, “Noiseproof Power Supplies: What's Important in EMI Reomoval Filters?” JEE, Jun. 1, 1986, pp. 80-85.
  • Jan. 1, 1999, Montrose, “Analysis on Loop Area Trace Radiated Emmissions from Decoupling Capacitor Placement on Printed Circuit Boards,” IEEE, 1999, pp. 423-428.
  • Jan. 1, 1999, Miyoshi, “Surface Mounted Distributed Constant Type Noise Filter,” 1999, pp. 157-160.
  • Jan. 1, 1999, Shigeta et al., “Improved EMI Performance by Use of a Three-Terminal-Capacitor Applied to an IC Power Line,” IEEE, 1999, pp. 161-164.
  • Jul. 19, 1999, PCT International Search Report for PCT/US99/07653.
  • Oct. 13, 1999, IPER for PCT/US99/07653.
  • U.S. Appl. No. 10/479,506, filed Dec. 10, 2003.
  • U.S. Appl. No. 10/189,339, filed Oct. 28, 2003.
  • U.S. Appl. No. 10/443,792, filed Oct. 28, 2003.
  • Aug. 19, 1998, PCT International Search Report for PCT/US98/06962.
  • Apr. 19, 1999, PCT International Search Report for PCT/US99/01040.
  • Sep. 18, 2000, PCT International Search Report for PCT/US00/11409.
  • Sep. 13, 2000, PCT International Search Report for PCT/US00/14626.
  • Nov. 8, 2000, PCT International Search Report for PCT/US00/16518.
  • Dec. 28, 2000, PCT International Search Report for PCT/US00/21178.
  • Sep. 1, 1996, Carpenter, Jr. et al., “A New Approach to TVSS Design,” Power Quality Assurance, Sep./Oct. 1996 p. 60-63.
  • Raychem, “Polyswitch Resettable Fuses,” Circuit Protection Databook, Jan. 1, 1996, pp. 11-18.
  • Dec. 28, 2001, PCT International Search Report for PCT/US01/41720.
  • Jun. 13, 2001, PCT International Search Report for PCT/US01/09185.
  • Jul. 1, 2000, Polka et al., “Package-Level Interconnect Design for Optimum Electrical Performance,” Intel Technology Journal Q3, 2000, pp. 1-17.
  • May 10, 2002, PCT International Search Report for PCT/US01/43418.
  • Mar. 13, 2002, PCT International Search Report for PCT/US01/32480.
  • Aug. 19, 2002, PCT International Search Report for PCT/US02/10302.
  • Feb. 28, 2003, PCT International Search Report for PCT/US02/21238.
  • Mar. 18, 2002, PCT International Search Report for PCT/US01/13911.
  • Jul. 16, 1991, PCT International Search Report for PCT/US91/02150.
  • Jun. 28, 2001, PCT International Search Report for PCT/US01/03792.
  • “Johanson Dielectrics, Inc. Licenses X2Y Circuit Conditioning Technology,” Press Release, Dec. 16, 1998, 1 page.
  • Beyne et al., “PSGA—an innovative IC package for single and multichip designs,” Components, Mar. 1, 1997, pp. 6-9.
  • “EMC Design for Brush Commutated DC Electric Motors,” Sep. 15, 1997, pp. 1-2.
  • Apr. 1, 1996, “Tomorrow's Capacitors,” Components, 1996, No. 4, p. 3.
  • Mason, “Valor—Understanding Common Mode Noise,” Mar. 30, 1998, pp. 1-7.
  • Anthony Anthony et al., U.S Appl. No. 10/237,079, filed Sep. 9, 2002.
  • David Anthony et al., U.S. Appl. No. 10/766,000, filed Jan. 29, 2004.
  • William Anthony, U.S. Appl. No. 10/399,630, filed Aug. 27, 2003.
  • Anthony Anthony et al., U.S Appl. No. 10/432,840, filed May 28, 2003.
  • William Anthony, U.S. Appl. No. 10/443,482,filed Jun. 12, 2003.
  • Anthony Anthony et al., U.S. Appl. No. 10/435,199, filed May 12, 2003.
  • Anthony Anthony et al., U.S. Appl. No. 10/115,159, filed Apr. 2, 2002.
  • Anthony Anthony et al., U.S. Appl. No. 10/189,338, filed Jul. 2, 2002.
  • Anthony Anthony et al., U.S. Appl. No. 10/189,339, filed Jul. 2, 2002.
  • Anthony Anthony et al., U.S. Appl. No. 10/479,506, filed Dec. 10, 2003.
  • Anthony Anthony, U.S. Appl. No. 10/443,764, filed Sep. 16, 2003.
  • Anthony Anthony, U.S. Appl. No. 10/443,792, May 23, 2003.
  • Anthony Anthony, U.S. Appl. No. 10/443,788, filed May 23, 2003.
  • Anthony Anthony et al., U.S. Appl. No. 10/443,778, filed May 23, 2003.
  • Anthony Anthony et al., U.S. Appl. No. 10/460,361, filed Jun. 13, 2003.
  • Anthony Anthony et al., U.S. Appl. No. 10/705,962, filed May 25, 2005.
  • Anthony Anthony, U.S. Appl. No. 10/369,335, Feb. 18, 2003.
  • Anthony Anthony et al., U.S. Appl. No. 09/647,648, filed Nov. 17, 2000.
  • Anthony Anthony, U.S. Appl. No. 10/328,942, filed Dec. 23, 2002.
  • Anthony Anthony et al., U.S. Appl. No. 09/632,048, filed Aug. 3, 2000.
  • Anthony Anthony et al., U.S. Appl. No. 09/996,355, filed Nov. 29, 2001.
  • Willian Anthony, U.S. Appl. No. 10/023,467, filed Dec. 17, 2001.
  • Jan. 1, 2005, Weir, et al., “DesignCon 2005, High Performance FPGA Bypass Networks”.
  • Apr. 25, 2002, U.S. Appl. No. 10/399,590, filed Apr. 23, 2004.
  • Feb. 11, 2005, PCT International Search Report for PCT/US04/00218.
  • Feb. 18, 2005, PCT International Search Report for PCT/US04/14539.
  • Mar. 24, 2005, Australian Patent Office Examination Report for SG 200303041-8.
  • Apr. 11, 2005, PCT International Search Report for PCT/US04/18938.
  • Nov. 2000, Muccioli, “EMC Society Seattle and Oregon Chapters—New X2Y Filter Technology Emerges as Singles Component Solution for Noise Suppression”.
  • Sep. 27, 2005, PCT Corrected IPER for PCT/US04/00218.
  • Nov. 8, 2005, Supplementary Partial European Search Report EP 99916477.
  • Oct. 27, 2005, Supplementary European Search Report EP 98915364.
  • Dec. 9, 2005, PCT ISR for PCT/US04/39777.
  • May 8, 2006, EP Examination Report for 99916477.5-2215.
  • PCT Written Opinion of the International Search Authority, PCT/US2007/063463.
  • PCT International Search Report, PCT/US2007/063463.
  • Oct. 31, 2007, PCT International Search Report PCT/US06/06609.
  • Oct. 31, 2007, PCT Written Opinion of the International Search Authority PCT/US06/06609.
  • Jun. 12, 2008, PCT International Search Report PCT/US06/06608.
  • Jun. 12, 2008, PCT Written Opinion of the International Search Authority PCT/US06/06608.
  • Jun. 12, 2008, PCT International Search Report PCT/US06/06607.
  • Jun. 12, 2008, PCT Written Opinion of the International Search Authority PCT/US06/06607.
  • Jun. 17, 2008, PCT International Search Report PCT/US06/08901.
  • Jun. 17, 2008, PCT Written Opinion of the International Search Authority PCT/US06/08901.
  • Jun. 6, 2008, European Search Report EP 07 01 9451.
  • Sep. 25, 2008, European Search Report EP 01 99 4116.
  • Sep. 25, 2008, European Search Report EP 01 99 9170.
  • Sep. 25, 2008 European Search Report EP 01 99 0677.
  • Sep. 18, 2008, PCT Written Opinion of the International Search Authority PCT/US07/063463.
  • Sep. 25, 2008, European Search Report EP 01 90 8876.
  • Sep. 25, 2008, European Search Report EP 01 92 2559.
  • Sep. 25, 2008, European Search Report EP 01 98 1731.
  • Jan. 24, 1995, Patent Abstracts of Japan, English translation of abstract for JP 07-022757.
  • Oct. 13, 2000, Patent Abstracts of Japan, English translation of abstract for JP 2000-28665.
  • Nov. 1, 1960, Cohn, “Characteristic Impedances of Broadside-Coupled Strip Transmission Lines”, IRE Transactions on Microwave Theory and Techniques, vol. 8.6, 633-637.
  • May 1, 1969, Goldmann, “Geometric Optimization of Controlled Collapse Interconnections”, IBM Journal of Research and Development, vol. 13.3, pp. 251-265.
  • Jan. 1, 1974, Howe, Stripline Circuit Design, pp. 1-308.
  • May 1, 1971, Hines, “Reciprocal and Nonreciprocal Modes of Propagation in Ferrite Stripline and Microstrip Devices”, IEEE Transactions on Mircowave Theory and Techniques, vol. MTT-19.5, pp. 442-451.
  • Sep. 1, 1976, Coda et al. “Design Considerations for High-Frequency Ceramic Chip Capacitors”, IEEE, vol. PHP-12.3, pp. 206-212.
  • Apr. 1, 1985, King, Texas Instruments Design Group Electromagnetic Compatibility Design Guide, pp. 1-98.
  • Sep. 1, 1987, Robinson et al., “A Midrange VLSI Hewlett-Packard Precision Architecture Computer”, Hewlett-Packard Journal, vol. 38.9, pp. 26-37.
  • Jan. 1, 1988, Chao et al., “Multilayer Thin-Film Substrate for Multichip Packaging”, Electronic Components Conference, Proceedings of the 38th, pp. 276-281.
  • Jan. 1, 1989, Quint et al., “Electrical Design Methodology of a 407 Pin Multi-Layer Ceramic Package”, Electronic Components Conference, Proceedings of the 39th, pp. 392-397.
  • Jan. 1, 1989, Bhat et al., Stripline-Like Transmission Lines for Microwave Integrated Circuits, pp. 1-695.
  • May 1, 1989, Paul, “A Comparison of the of Record Contributions of Common-mode and Differential Mode Currents in Radiated Emissions”, IEEE Transactions on Electromagnetic Compatability, vol. 31.2, pp. 189-193.
  • Aug. 1, 1989, King et al., Michael King Lecture Notes, pp. 1-14.
  • May 1, 1982, Bonner et al., “Advanced Printed-Circuit Board Design for High Performance Computer Applications”, IBM Journal of Research and Development vol. 26.3, pp. 297-305.
  • Jan. 1, 1989, Hnatek et al., “Quality Issues of High Pin Count Fine Pitch VLSI Packages”, IEEE International Test Conference, pp. 397-421.
  • May 1, 1989, Jayaraj et al., “Performance of Low Loss, High Speed Interconnects for Multi-GHz Digital Systems”, IEEE Proceedings of the Aerospace and Electronics Conference, vol. 4, pp. 1674-1681.
  • Jan. 1, 1989, Liang et al., “High-Performance VLSI Through Package-Level Interconnects”, IEEE Proceedings 39th Electronic Components Conference, pp. 518-523.
  • Jun. 1, 1987, Palusinski et al., “Electrical Modeling of Interconnections in Multilayer Packaging Structures”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 10.2, pp. 217-223.
  • Sep. 1, 1987, Kwon et al., “Closely Packed Microstrip Lines as Very High Speed Chip-to-Chip Interconnects”, IEEE Transactions on Components, Hybrids and Manufacturing Technology, vol. 10.3, pp. 314-320.
  • Dec. 1, 1985, Watari et al., “Packing Technology for the NEC SX Supercomputer”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 8.4 pp. 462-467.
  • Jan. 1, 1989, Seraphim et al., “Principles of Electronic Packaging”, McGraw-Hill series in electrical engineering.
  • Nov. 1, 1989, Gisin, “Minimizing Electromagnetic Interference Through Proper Printed Circuit Board Layout Techniques”, Wescon/89 Conference Record, pp. 352-354.
  • Jan. 1, 1983, Wilson et al., “Theoretical and Experimental Analysis of Coupling Characteristics of Dual TEM Cells”, IEEE 1983 International Symposium on Electromagnetic Compatibility, pp. 513-517.
  • Jan. 1, 1985, Keenan, Decoupling and Layout of Digital Printed Circuits, 1.0 to A4-4.
  • Jan. 1, 1989, AMS International, Electronic Materials Handbook: Packaging, vol. 1, pp. 18-34; 76-88; 127-41; 597-610.
  • Sep. 1, 1987, Mangelsdorf et al., “A VLSI Processor for HP Precision Architecture”, Hewlett-Packard Journal, vol. 38.9, pp. 4-11.
  • Apr. 1, 1989, Jessen, “VXIbus Product Development Tools”, Hewlett-Packard Journal, vol. 40.2, 96-97.
  • Apr. 1, 1989, Jessen, “VXIbus: A New Interconnection Standard for Modular Instruments”, Hewlett-Packard Journal, vol. 40.2, pp. 91-95.
  • Jan. 1, 1990, Akihiro et al., “Packaging Technology for the NEC SX-3/SX Supercomputer”, IEEE Electronic Components and Technology Conference, pp. 525-533.
  • Jan. 1, 1990, Smith and Savara, “High-Speed Characteristics of Multilayer Ceramic Packages and Test Fixtures”, Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1990. Technical Digest 1990, 12th Annual, pp. 203-206.
  • Jan. 1, 1990, Shimada et al., “Large Scale Multilayer Glass-Ceramic Substrate for Supercomputer”, IEEE 40th Electronic Components and Technology Conference, 1990, vol. 1, pp. 76-83.
  • Jan. 1, 1990, Mielke et al., “High-Speed Fixture Interconnects for Mixed-Signal IC Testing”, IEEE International Test Conference, pp. 891-895.
  • Jan. 1, 1990, Walker, Capacitance, Inducatance, and Crosstalk Analysis, pp. 1-231.
  • May 1, 1990, Prymak, “Advanced Decoupling Using Ceramic MLC Capacitors”, 40th Electronic Components and Technology Conference, pp. 1014-1023.
  • Sep. 1, 1990, Moresco, “Electronic System Packaging: The Search for Manufacturing the Optimum in a Sea of Constraints”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 13.3, pp. 494-508.
  • Oct. 1, 1990, Quint et al., “Measurement of R, L, and C Parameters in VLSI Packages”, Hewlett-Packard Journal, vol. 41.5, pp. 73-77.
  • Feb. 1, 1991, Henke et al., “A Checklist for EMC-Controlled Printed Circuit Board Designs”, Printed Circuit Design, vol. 8.2.
  • Feb. 1, 1991, Tomlinson, “Bringing Board Layout Up to Speed”, Printed Circuit Design, vol. 8.2, pp. 6-10.
  • Aug. 1, 1991, Montrose, “Overview on Design Techniques for Printed Circuit Board Layout Used in High Technology Products”, IEEE International Symposium on Electromagnetic Compatibility 1991, pp. 61-66.
  • Sep. 1, 1991, Nghiem et al., “A General Analysis of Propagation Along Multi-Layer Superconducting Stripline and Microstrip Transmission Lines”, IEEE Transactions on Microwave Theory and Techniques, vol. 39.9, pp. 1553-1565.
  • Jan. 1, 1991, Tummala et al., “Packaging Technology for IBM's Latest Mainframe Computers (S/390/ES9000)”, IEEE, pp. 682-688.
  • Jan. 1, 1991, Institute for Interconnecting and Packaging Electronic Circuits, IPC-D-275: Design for Rigid Printed Boards and Rigid Printed Board Assemblies, pp. 1-97.
  • Jan. 1, 1991, Fluke, Controlling Conducted Emissions by Design, pp. 1-334.
  • Jan. 1, 1992, Becker et al., “Time Domain Electromagnetic Analysis of a Via in a Multilayer Computer Chip Package”, Microwave Symposium Digest, 1992, IEEE MTT-S International, pp. 1229-1232.
  • Jan. 1, 1992, Papsioannou et al., “Generic Design Rules for High Speed MCM'S”, IEMT 12th International Electronic Manufacturing Technology Symposium, 1992, pp. 237-244.
  • Jan. 1, 1992, Wu, “Resistance Computations for Multilayer Packaging Structures by Applying the Boundary Element Method”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 15.1, pp. 87-96.
  • Feb. 1, 1992, Teener, “A Bus on a Diet—The Serial Bus Alternative—An Introduction to the P1394 High Performance Serial Bus”, IEEE Digest of Papers of 37th Computer Society International Conference, Compcon Spring 1992, pp. 316-321.
  • Feb. 1, 1992, Wyatt, “EMC Design of the HP 54600 Series Oscilloscopes”, Hewlett-Packard Journal, vol. 43.1, pp. 41-45.
  • Apr. 1, 1992, Carey, “Trends in Low Cost High-Performance Substrate Technology”, IEEE Micro, pp. 19-27.
  • Apr. 1, 1992, DesJardin, “VXIbus: A Standard for Test and Measurement System Architecture”, Hewlett-Packard Journal, vol. 43.2, pp. 6-14.
  • May 1, 1992, Gravelle et al., “EMI/EMC in Printed Circuit Boards—a Literature Review”, IEEE Transactions on Electromagnetic Compatibility, vol. 34.2, pp. 109-116.
  • Jul. 1, 1992, de Vreede, et al., “A High Frequency Model Based on the Physical Structure of the Ceramic Multilayer Capacitor”, IEEE Transactions on Microwave Theory and Techniques, vol. 40.7, pp. 1584-1587.
  • Jan. 1, 1992, Murano et al., “Packaging Technology for the NEC SX-3 Supercomputer”, IEEE Transaction on Components, Hybrids, and Manufacturing Technology, pp. 411-417.
  • Aug. 1, 1992, Pan et al., “The Simulation of High-Speed, High-Density Digital Interconnects in Single Chip Packages and Multichip Modules”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 15, No. 4, pp. 465-477.
  • Aug. 1, 1992 Daijavad et al., “Methodology for Evaluating Practical EMI Design Guidelines Using EM Analysis Programs”, IEEE International Symposium on Electromagnetic Compatibility, 1992, pp. 30-34.
  • Aug. 1, 1992, Frink et al., “High-Performace Designs for the Low-cost PA-RISC Desktop”, Hewlett-Packard Journal, vol. 43.4, pp. 55-63.
  • Aug. 1, 1992, Gleason et al., “VLSI Circuits for Low-End and Midrange PA-RISC Computers”, Hewlett-Packard Journal, vol. 43.4, pp. 12-22.
  • Aug. 1, 1992, Lettang, “ECL Clocks for High-Performance RISC Workstations”, Hewlett-Packard Journal, vol. 43.4, pp. 23-25.
  • Sep. 1, 1992, Davidson et al., “Physical and electrical design features of the IBM Enterprise System/9000 circuit Module”, IBM J. Res. Develop. vol. 36, No. 5, pp. 877-888.
  • Oct. 1, 1992, Foss et al., “Fast Interfaces for DRAMs”, IEEE SPECTRUM, vol. 29.10.
  • Nov. 1, 1992, Bussmann, “Active Compensation of Interconnection Losses for Multi-GHz Clock Distribution Networks”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39.11, pp. 790-798.
  • Dec. 1, 1992, Matta, “Advances in Integrated Circuit Packaging: Demountable TAB”, Hewlett-Packard Journal, vol. 43.6, pp. 62-77.
  • Dec. 1, 1992, Thomas et al., “Software for the HP EISA SCSI Card”, Hewlett-Packard Journal, vol. 43.6, pp. 97-108.
  • Jan. 1, 1993, Rao et al., “Manufacture of Advanced Cu-PI Multi Chip Modules”, IEEE Proceedings 43rd Electronic Components and Technology Conference, pp. 920-934.
  • Jan. 1, 1993, “Finite-Difference Time-Domain Modeling of Noise in Computer Packages”, IEEE, pp. 123-127.
  • Feb. 1, 1993, Jouppi et al., “A 300MHz 115W 32b Bipolar ECL Microprocessor with On-Chip Caches”, IEEE 40th International Solid-State Circuits Conference, 1993 Digest of Papers, pp. 84-85.
  • Jan. 1, 1993, Iqbal et al., “Design Tradeoffs Among MCM-C, MCM-D and MCM- D/C Technologies”, Multi-Chip Module Conference, 1993. MCMC-93, Proceedings, 1993 IEEE, pp. 12-18.
  • Jan. 1, 1993, Becker et al., “Power Distribution Modelling of High Performance First Level Computer Packages”, IEEE Electrical Performance of Electronic Packaging, 1993, pp. 202-205.
  • Aug. 1, 1993, Downing et al., “Decoupling Capacitor Effects on Switching Noise”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 16.5, pp. 484-489.
  • Nov. 1, 1993, Blennemann et al., “High Aspect Ratio Lines as Low Distortion High Frequency Off-Chip Interconnects”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 16.7, pp. 692-698.
  • Oct. 1, 1993, Becker et al., “Finite-Difference Time-Domain Modeling of Currents in Multi-Layered Computer Chip Packages”, IEEE Electrical Performance of Electronic Packaging, 1993, pp. 181-184.
  • Oct. 1, 1993, Yamaguchi et al., “Packaging Technology for High-Speed Multichip Module Using Copper-Polyimide Thin Film Multilayer Substrate [for B-ISDN]”, Electronic Manufacturing Technology Symposium, 1993, Fifteenth IEEE/CHMT International, pp. 406-410.
  • Dec. 1, 1993, Intel, “AP-125: Designing Microcontroller Systems for Electrically Noisy Environments”, pp. 1-21.
  • Jan. 1, 1993, Institute for Interconneciting and Packaging Electronic Circuits, IPC-T-50: Terms and Definitions Interconnecting and Packaging Electronic Circuits, pp. 1-71.
  • Feb. 1, 1993, IEEE, IEEE Std 1155-1992: IEEE Standard for VMEbus Extentions for Instrumentation: VXIbus, pp. 1-199.
  • Jun. 1, 1993, Asprey et al., “Performance Features of the PA7100 Microprocessor”, IEEE Micro, vol. 13.3, pp. 22-35.
  • Jun. 1, 1993, McLellan, “The Alpha AXP Architecture and 21064 Processor”, IEEE Micro, vol. 13.3, pp. 36-47.
  • Jan. 1, 1994, Kambe et al., “MCM Substrate with of Record High Capacitance”, Proceedings of the 1994 International Conference on Multichip Modules, pp. 136-141.
  • Jan. 1, 1994, Center for Electronic Pacakaging Research, “Simulataneous Switching Noise: Influence of Plane-Plane and Plane-Signal Trace Coupling”, Electronic Components and Technology Conference, 1994. Proceedings, 44th, pp. 957-961.
  • Jan. 1, 1994, Dimos et al., “Thin Film Decoupling Capacitors for Multichip Modules”, Electronic Components and Technology Conference, 1994. Proceedings, 44th, pp. 894-899.
  • Jan. 1, 1994, Ida et al., “An L-Band Power Amplifier Multi-Chip-Module Using Multi-Layered Planar Circuits”, IEEE MTT-S International Microwave Symposium Digest 1994, vol. 3, pp. 1649-1652.
  • Jan. 1, 1994, Schaper et al., “Electrical Characterization of the Interconnected Mesh Power System (IMPS) MCM Topology”, IEEE Proceedings 44th Electronic Components and Technology Conference, 1994, pp. 791-795.
  • Jan. 1, 1994, Hirano et al., “Characterization and of Record Reduction of Simultaneous Switching Noise for a Multilayer Package”, IEEE Proceedings of 44th Electronic Components and Technology Conference, 1994, pp. 949-956.
  • Jan. 1, 1994, Huang et al., “CBGA Package Design for C4 PowerPC Microprocessor Chips: Trade-off Between Substrate Routability and Performance”, Electronic Components and Technology Conference, 1994. Proceedings, 44th, pp. 88-93.
  • Jan. 1, 1994, AT&T, Carrierless AM/PM (CAP) Host-DSL Transceiver Layout Guide, pp. 1-24.
  • May 1, 1994, Yamanak et al., “320 Gb/s High-Speed ATM Switching System Harware Technologies Based on Copper-Polyimide MCM”, IEEE 44th Electronic Components and Technology Confrerence, pp. 776-785.
  • Jan. 1, 1994, Iqbal et al., “Design Tradeoffs Among MCM-C, MCM-D and MCM-D/C Technologies”, IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B: Advanced Packaging, pp. 22-29.
  • Jul. 1, 1994, Schwab et al., “Multilayer Suspended Stripline and Coplanar Line Filters”, IEEE Transactions on Microwave Theory and Techniques, vol. 42.7, pp. 1403-1407.
  • Oct. 1, 1994, Garg et al., “Thermal Design of an Advanced Multichip Module for a RISC Processor”, IEEE International Conference on Computer Design: LVSI in Computers and Processors, 1994, pp. 608-611.
  • May 1, 1994, Light et al., “Process Considerations in the Fabrication of Teflon Printed Circuit Boards”, IEEE Proceedings of the Electronic Components and Technology Conference, 1994, pp. 542-549.
  • Jan. 1, 1994, Swaminathan et al., “Electrical Design of a MCM for a Multiprocessor Systems”, MCM '94 Proceedings, pp. 480-486.
  • May 1, 1994, Wu et al., “Modeling and Simulation of Integral Decoupling Capacitors in Single and Multichip Module Electronics Packaging”, IEEE Proceedings 44th Electronic Components and Technology Conference, 1994, pp. 945-948.
  • May 1, 1994, Panicker et al., “Low-Cost Ceramic Thin-Film Ball Grid Arrays”, IEEE Proceedings 44th Electronic Components and Technology Conference, 1994, pp. 29-31.
  • Jun. 1, 1994, Sudo, “Present and Future Directions for Multichip Module Technologies”, IEEE Symposium on VLSI Circuits, 1994. Digest of Technical Papers, pp. 51-54.
  • May 1, 1994, DeHaven and Dietz, “Controlled Collapse Chip Connection (C4)—an Enabling Technology”, IEEE Proceedings of 44th Electronic Components and Technology Conference, 1994, pp. 1-6.
  • Jan. 1, 1994, Fang et al., “Effects of Losses in Power Planes in the Simulation of Simultaneous Switching Noise”, Proceedings of the 3rd Topical Meeting on Electrical Performance of Electrical Packaging, pp. 110-112.
  • Apr. 1, 1994, Light et al., “Integrated Flex: Rigid-Flex Capability in a High Performance MCM”, MCM '94 Proceedings, pp. 430-442.
  • Jan. 1, 1994, Jastech, Advanced EMC Printed Circuit Board Design, pp. 1 to 8-15.
  • Jan. 1, 1994, Hannemann et al., Semiconductor Packaging a Multidisciplinary Approach, pp. 1-886.
  • Feb. 23, 2009, Intel Corp, Intel Corp Form 10-K of Record for period ending Dec. 17, 2008.
  • Feb. 20, 2008, Intel Corp, Intel Corp Form 10-K of Record for period ending Dec. 29, 2007.
  • Sep. 1, 1994, Ogasawara et al., “High Isolation Analog 4 X 4 Matrix Switch LSI for Centralized Control Microcell Radio Systems”, 5th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, 1994. Wireless Networks—Catching the Mobile Future, vol. 1, pp. 369-371.
  • Dec. 1, 1994, IEEE Standards Board, IEEE Standard for Medical Device Communications—Physical Layer Interface—Cable Connected.
  • Jan. 1, 1995, Vaidyanath et al., “Simultaneous Switching Noise: Influence of Plane-Plane and Plane-Signal Trace Coupling”, IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, vol. 18.3, pp. 496-502.
  • Jan. 1, 1995, Lester et al., “Low Cost Miniaturized EHF Satcom Transceiver Featuring HEMT MMICS and LTCC Multilayer Packaging”, IEEE 1995 Microwave and Millimeter-Wave Monolithic Circuits Symposium, pp. 35-38.
  • Jan. 1, 1995, Liaw, “Simulation and Modeling of Mode Conversion at Vias in Multilayer Interconnections”, IEEE Proceedings of the 45th Electronic Components and Technology Conference, 1995, pp. 361-367.
  • Jan. 1, 1996, Montrose, Printed Circuit Board Design Techniques for EMC Compliance, pp. 1-238.
  • Feb. 1, 1995, Yamanaka et al., “30 Gb/s High-speed ATM Switching System Hardware Technologies Based on Copper-Polymide MCM”, IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B: Advanced Packaging, vol. 18.1, pp. 83-91.
  • Apr. 1, 1995, Pearson, “A Low-Cost, High-Performance PA-RISC Workstation with Built-in Graphics Multimedia, and Networking Capabilities”, Hewlett-Packard Journal, vol. 46.2, pp. 6-11.
  • Feb. 1, 1995, Kambe, et al., “MCM Substrate with of Record High Capacitance”, IEEE Transactions on Components, Packaging, and Manufacturing Technology- Part B, vol. 18.1, pp. 23-27.
  • Oct. 1, 1995, Cohn, “Shielded Coupled-Strip Transmission Line”, IRE Transactions on Microwave Theory and Techniques, vol. 3.5, pp. 29-38.
  • Sep. 1, 1995, Murphy et al., “High Frequency Performance of Multilayer Capacitors”, IEEE Transactions on Microwave Theory and Techniques, vol. 43, No. 9, 2007-2015.
  • Mar. 1, 1995, Dimos et al., “Thin-Film Decoupling Capacitors for Multichip Modules”, IEEE Transactions on Components Packaging, and Manufactuing Technology, Part A, vol. 18.1, pp. 174-179.
  • Feb. 1, 1995, Sarfaraz et al., “Electrical Design of an MCM Package for a Multi-Processor Digital System”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B. vol. 18, No. 1, pp. 127-143.
  • Nov. 1, 1995, Lee et al., “Modeling and Analysis of Multichip Module Power Supply Planes”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, vol. 18.4, pp. 628-639.
  • May 1, 1995, Hussein, “FDTD Applications to Electromagnetic Interference and Shielding, WESCANEX 95. Communications, Power, and Computing”, Conference Proceedings. IEEE, pp. 478-482.
  • Feb. 1, 1995, Light et al., “Integrated Flex: Rigid-Flex Capability in a High Performance MCM”, IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, vol. 18.1, pp. 47-52.
  • Dec. 1, 1995, Huang et al., “A Packaging System for Built-in Microcircuits in Multilayer Substrates”, 1995 Japan IEMT Symposium: Proceedings of 1995 International Electronic Manufacturing Technology Symposium, pp. 460-463.
  • Jan. 1, 1995, Institute for Interconnecting and Pacakaging Electronic Circuits, IPC-D-137A: Design Guidelines for Electronic Packaging Utilizing High-Speed Techniques, pp. 1-70.
  • Nov. 6, 1995, Miskell, “Avoid EMI Woes in Power-Bus Layouts”, Electronic Design, vol. 43.23, pp. 147-150.
  • Jan. 1, 1995, Wu et al., “Precise CMOS Current Sample/Hold Circuits Using Differential Clock Feedthrough Attenuation Techniques”, IEEE Journal of Solid-State Circuitry, vol. 30.1, pp. 76-80.
  • Apr. 1, 1995, Lee, “Accelerating Multimedia with Enhanced Microprocessors”, IEEE Micro, vol. 15.2, p. 22-32.
  • Mar. 1, 1995, Hunt, “Advanced Performance Features of the 64-bit PA-8000”, Compcon '95, ‘Technologies for the Information Superhighway’, Digest of Papers, pp. 123-128.
  • Dec. 1, 1995, IEEE Standards Board, IEEE Standard for a High Performance Serial Bus.
  • Apr. 1, 1995, Edmondson et al., “Superscalar Instruction Execution in the 21164 Alpha Microprocessor”, IEEE Micro, vol. 15.2, 33-43.
  • Apr. 1, 1995, Bass et al., “The PA 7100LC Microprocessor: A Case Study of 1C Design Decisions in a Competitive Environment”, Hewlett-Packard Journal, vol. 46.2, 12-22.
  • Feb. 1, 1996, Fessler et al., “The Effectiveness of of Record an Image Plane in Reducing Radiated Emissions”, IEEE Transactions on Electromagnetic Compatibility, vol. 38.1, pp. 51-61.
  • Feb. 1, 1996, Kromann et al., “A Hi-Density C4/CBGA Interconnect Technology for a CMOS Microprocessor”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, vol. 19.1, pp. 166-173.
  • Feb. 1, 1996, Intel, AP-711: EMI Design Techniques for Microcontrollers in Automotive Applications, pp. 1-21.
  • Feb. 1, 1996, Wu et al., “1.2V CMOS Switched-Capacitor Circuits”, IEEE 42nd International Solid-State Circuits Conference, 1996, pp. 388-389, 479.
  • Feb. 1, 1996, Bryg et al., “A High-Performance, Low-Cost Multiprocessor Bus for Workstations and Midrange Servers”, Hewlett-Packard Journal, vol. 47.1, pp. 18-24.
  • Feb. 1, 1996, Chan et al., “Design of the HP PA 7200 CPU”, Hewlett-Packard Journal, vol. 47.1, pp. 25-33.
  • Feb. 1, 1996, Harline et al., “Symmetric Multiprocessing Workstations and Servers System-Designed for High Performance and Low Cost”, Hewlett-Packard Journal, vol. 47.1, pp. 8-17.
  • Feb. 1, 1996, Hotchkiss et al., “A New Memory System Design for Commercial and Technical Computing Products”, Hewlett-Packard Journal, vol. 47.1, pp. 44-51.
  • Mar. 1, 1996, Intel, AP-524 Pentium® Pro Processor GTL+ Guidelines, pp. 1-26.
  • Mar. 21, 1996, IEEE Standards Board, IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), pp. 1-29.
  • Apr. 26, 1996, Bauer, “BGA and Flip-Chip Technologies: A to Z”, SEMICON/Test, Assembly & Paclahing 96.
  • May 1, 1996, Aguirre et al., “Numerical Investigation of Radiated Emissions Mechanisms in Single-Chip Packages”, IEEE Proceedings of 46th Electronic Components and Technology Conference, 1996, pp. 996-1001.
  • May 1, 1996, Madhaven et al., “A Novel High Speed Low Skew Clock Distribution Scheme in 0.8 Micron CMOS”, 1996 IEEE International Symposium on Circuits and Systems, 1996. ISCAS '96., Connecting the World, vol. 4, pp. 149-152.
  • Jul. 1, 1996, Ommodt et al., “Vertical Interconnects for Phased Array Packaging”, IEEE Antennas and Propagation Society International Symposium, vol. 2, pp. 1334-1337.
  • Oct. 1, 1996, Fang et al., “Reduction of Power and Ground Noise Coupling in Mixed Signal Modules”, IEEE 5th Topical Meeting on Electrical Performance of Electronic Packaging, 1996, pp. 90-92.
  • Oct. 1, 1996, Lei et al., “Power Distrubution Noise Suppression Using Transmission Line Termination Techniques”, Proceedings of the 5th Topical Meeting on the Electrical Performance of Electrical Packaging, pp. 100-102.
  • Jan. 1, 1996, Libous et al., “Measurement, Modeling and Simulation of Flip-Chip CMOS ASIC Simultaneous Switching Noise on a Multi-Layer Ceramic BGA”, IEEE, pp. 120-122.
  • Jan. 1, 1996, Institute for Inerconnecting and Packaging Electronic Circuits, IPC-T-50: Terms and Definitions Interconnecting and Packaging Electronic Circuits, pp. 1-101.
  • Dec. 1, 1996, Slater, “The Microprocessor Today”, IEEE Micro, vol. 16.6, pp. 32-44.
  • Dec. 1, 1996, Yu, The Future of Microprocessors, IEEE Micro, vol. 16.6, pp. 46-53.
  • Jan. 1, 1997, Konsowski et al., Electronic Packaging of High Speed Circuitry, pp. 1-417.
  • Jan. 1, 1997, Allan et al., “A Low-Cost Workstation with Enhanced Performance and I/O Capabilities”, Hewlett-Packard Journal, vol. 48.3, pp. 82-88.
  • Oct. 1, 1997, Pillai, “Coax Via—A Technique to Reduce Crosstalk and Enhance Impedance Match at Vias in High-Frquency Multilayer Packages Verified by FDTD and MoM Modeling”, IEEE Transactions on Microwave Theory and Techniques, vol. 45, No. 10, pp. 1981-1985.
  • Nov. 1, 1997, Koike et al., “High-Speed Signal Transmission at the Front of a Bookshelf Packaging System”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B. vol. 20, No. 4, pp. 353-360.
  • Jan. 1, 1998, Petefish et al., “High Density Organic Flip Chip Package Substrate Technology”, IEEE 1998 Electronic Components and Technology Conference, pp. 1089-1097.
  • Feb. 1, 1998, Deutsch, “Electrical Characteristics of Interconnections for High-Performance Systems”, Proceedings of the IEEE, vol. 86.2, pp. 315-355.
  • Feb. 1, 1998, Vichot et al., “Numerical Modeling of a Clock Distribution Network for a Superconducting Multichip Module”, IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, vol. 21, No. 1, pp. 98-104.
  • Feb. 1, 1998, Institute for Interconnecting and Packaging Electronic Circuits, IPC-2221: Generic Standard on Printed Board Design, pp. 1-97.
  • Aug. 1, 1998, Karies, “Radiated Emissions from Printed Circuit Board Traces Including the Effect of Vias, as a Function of Source, Termination and Board Characteristics”, IEEE International Symposium on Electromagnetic Compatibility 1998, vol. 2, pp. 872-877.
  • Oct. 1, 1998, Brown, Advanced Electronic Packaging with Emphasis on Multichip Modules, pp. 1-791.
  • Jan. 1, 1998, Low et al., “Via Design Optimisation for High Speed Device Packaging”, IEEE/CPMT Electronics Packaging Technology Conference, pp. 112-118.
  • Jan. 1, 1998, Lau et al., Electronic Packaging Design, Materials, Process, and Reliability, pp. 1-482.
  • Jan. 1, 1998, Martens, High-Frequency Characterization of Electronic Packaging, pp. 1-155.
  • Jan. 1, 1999, Shigeta et al., “Improved EMI Performance by Use of a Three-Terminal-Capacitor Applied to an IC Power Line”, IEEE International Symposium on Electromagnetic Compatibility, 1999, vol. 1, pp. 161-164.
  • Feb. 1, 1999, Intel Corporatio, AP-589: Design for EMI, pp. 1-14.
  • Aug. 1, 1999, Erdin et al., “Mixed Circuit/Electromagnetic Analysis of Field Coupling to High Speed Interconnects in Inhomogenous Medium”, IEEE International Symposium on Electromagnetic Compatibility, 1999, vol. 1, pp. 446-449.
  • Aug. 1, 1999, Armstrong, “PCB Design Techniques for Lowest-Cost EMC Compliance: Part 1”, Electronics & Communication Engineering Journal, pp. 218-226.
  • Oct. 1, 1999, Armstrong, “PCB Design Techniques for Lowest-Cost EMC Compliance: Part 2”, Electronics & Communication Engineering Journal, pp. 185-194.
  • Jan. 1, 1999, Li et al., “Validation of Integrated Capacitor-Via-Planes Model”, IEEE, pp. 121-124.
  • Jan. 1, 1999, Yew et al., “Design and Performance Evaluation of Chip Capacitors on Microprocessor Packaging”, IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 175-178.
  • Jan. 1, 2000, Chen, “Effects of 20-H Rule and Sheilding Vias on Electromagnetic Radiation From Printed Circuit Boards”, IEEE, pp. 193-196.
  • Jan. 1, 2000, Ilavarasan et al., “Currect and Future EMI Challenges at Intel and How to Manage Them”, IEEE, pp. 281-283.
  • Jan. 1, 2000, Tadayon, “Thermal Challenges During Microprocessor Testing”, Intel Technology Journal.
  • Jan. 1, 2000, Dory et al., “Simultaneous Chip-Join and Underfill Assembly Technology for Flip-Chip Packaging”, Intel Technology Journal.
  • Jan. 1, 2000, Grayeli, “Microprocessor Packaging: Evolution and Future Challenges”, Intel Technology Journal.
  • Jan. 1, 2000, Viswanath et al., “Thermal Performance Challenges From Silicon to Systems”, Intel Technology Journal.
  • Jul. 1, 2000, Benedict, “PCB Design for EMI/EMC Compliance”, WEMPEC Seminar.
  • Aug. 1, 2000, Li et al., “Design and Performance Evaluation of Microprocessor Packaging Capcitors Using Integrated Capcitor-Via-Plane Model”, IEEE Transactions on Advanced Packaging, vol. 23.3, pp. 361-367.
  • Aug. 1, 2000, Mahajan et al., “The Evolution of Microprocessor Packaging”, Intel Technology Journal, vol. 4.3, pp. 1-10.
  • Aug. 1, 2000, Lii et al., “Flip-Chip Technology on Organic Pin Grid Array Packages”, Intel Technology Journal, vol. 4.3, pp. 1-9.
  • Aug. 1, 2000, Mencinger, “A Mechanism-Based Methodology for Processor Package Reliability Assessments”, Intel Technology Journal, vol. 4.3, pp. 1-8.
  • Jan. 1, 2001, Ye et al., “EMI Mitigation with Multilayer Power-Bus Stacks and Via Stitching of Reference Planes”, IEEE Transactions on Electromagnetic Compatibility, vol. 43.4, pp. 538-548.
  • Jan. 1, 2001, zilog.com, Product Update for Z86C02/E02/L02, Z86C04/E04/L04, Z86C08/E08/L08 to Clarify the Output Drive in Low-EMI Mode.
  • Aug. 1, 2001, Shim et al., “20-H Rule Modeling and Measurements”, IEEE International Symposium on Electromagnetic Compatibility 2001, vol. 2, pp. 939-942.
  • Sep. 1, 2001, Gisin et al., “Minimizing EMI Caused by Radially Propagating Waves Inside High Speed Digital Logic PCBs”, TELSIKS 2001, pp. 624-631.
  • Jan. 1, 2002, He et al., “Study of Package EMI Reduction for GHz Micropricessors”, IEEE, pp. 271-274.
  • Jan. 1, 2003, Muccioli et al., “A Microwave Test Fixture for Measuring Four-Terminal Passive Components from DC to 10 GHz”, Interference Technology.
  • Jan. 1, 2004, Sanders et al., “Comparison of MLCC and X2Y Technology for Use in Decoupling Circuits”, CARTS 2004: 24th Annual Capacitor and Resistor Technology Symposium, Mar. 29-Apr. 1.
  • Aug. 1, 2004, Sanders, A Better Approach to DC Power Filtering.
  • Mar. 21, 2005, Sanders et al., “The Quantitative Measurement of the Effectiveness of Decoupling Capacitors in Controlling Switching Transients from Microprocessors”, 25th Annual Passive Components Conference CARTS 2005 , pp. 1-16.
  • May 1, 2005, Montrose et al., “Analysis on the Effectiveness of the 20-H Rule for Printed-Circuit-Board Layout to Reduce Edge-Radiated Coupling”, IEEE Transactions on Electromagnetic Compatibility, vol. 47.2, pp. 227-233.
  • Nov. 9, 2005, Various, Various, Intel Technology Journal.
  • May 1, 2008, Ikami et al., “Practical Analysis on 20H Rule for PCB”, 2008 Asia-Pacific Symposium on Electromagnetic compatibility, pp. 180-183.
  • Apr. 26, 2012, Swigget of Prismark Partners LLC, “Product Teardown Report”, filed in ITC Investigation No. 33-TA-781.
  • Jan. 1, 1999, Montrose, EMC and the Printed of Record Circuit Board—Design, Theory, and Layout Made Simple, pp. 1-325.
  • Dec. 18, 1996, Lamson, U.S. Appl. No. 60/033,673.
  • Apr. 26, 2012, Stanley Shanfield, Expert Report on Stanley Shanfield, Ph.D Regarding Invalidity of U.S. Patent Nos, 6,738,249, 7,110,227, 7,609,500, 7,773,621, 7,916,444, and 8,023,241.
  • Apr. 26, 2012, Andreas Cangellaris, Expert Report of Andreas Cangellaris, Ph.D. Regarding Invalidity of U.S. Patent Nos. 6,738,249, 7,110,227, 7,609,500, 7,733,621, 7,916,777, and 8,023,241.
  • Apr. 26, 2012, Vivek Subramanian Initial Expert Report of Vivek Subramanian, Ph.D.
  • May 11, 2012, Vivek Subramanian, Rebuttal Expert Report of Vivek Subramanian, Ph.D.
  • Apr. 26, 2012, Dean P. Neikirk, Opening Expert Report of Dean P. Neikirk, PHD, Regarding X2Y's Patent Portfolio and Claim Construction, Infringement and Domestic Indusrty Technical Prong, for United States Patent Nos. 6,738,249, 7,110,227, 7,609,500, 7,733,621, 7,916,444, and 8,023,241, vol. 1.
  • May 11, 2012, Dean P. Neikirk, Rebuttal Expert Report of Dean P. Neikirk, PHD, Regarding Claim Construction, Validity, and Other Mtters Relating to United States Patent Nos. 6,738,249, 7,110,227, 7,609,500, 7,733,621, 7,916,444, and 8,023,241, vol. 1.
  • May 11, 2012, Dean P. Neikirk, Rebuttal Expert Report of Dean P. Neikirk, PHD, vol. 2.
  • May 11, 2012, Dean P. Neikirk, Rebuttal Expert Report of Dean P. Neikirk, PHD, vol. 8.
  • May 11, 2012, Dean P. Neikirk, Rebuttal Expert Report of Dean P. Neikirk, PHD, vol. 9.
  • May 11, 2012, Dean P. Neikirk, Rebuttal Expert Report of Dean P. Neikirk, PHD, vol. 10.
  • May 11, 2012, Dean P. Neikirk, Rebuttal Expert Report of Dean P. Neikirk, PHD, vol. 11.
  • May 11, 2012, Dean P. Neikirk, Rebuttal Expert Report of Dean P. Neikirk, PHD, vol. 12.
  • May 11, 2012, Dean P. Neikirk, Rebuttal Expert Report of Dean P. Neikirk, PHD, vol. 13.
  • May 11, 2012, Dean P. Neikirk, Rebuttal Expert Report of Dean P. Neikirk, PHD, vol. 14.
  • May 11, 2012, Dean P. Neikirk, Rebuttal Expert Report of Dean P. Neikirk, PHD, vol. 15.
  • May 21, 2012 Intel Corporation Apple Inc., and Hewlett-Packard Comapny, Respondents'Motion for Summary Determination of Indefiniteness of Asserted Claims of the '621, '444, and '241 Patents.
  • May 31, 2012, X2Y Attenuators, LLC, X2Y's Memorandum of Law in Oppositon to Respondents'Motion for Summary Determination of Indefiniteness of Asserted Claims of the 621, 444, and 241 Patents.
  • Feb. 22, 2012, X2Y Attenuators, LLC, Complainant X2Y Attenuators, LLC's Responses and Objesctions to Respondents'Eight Set of Interrogatories (No. 109-148).
Patent History
Patent number: 9019679
Type: Grant
Filed: Nov 15, 2013
Date of Patent: Apr 28, 2015
Patent Publication Number: 20140116770
Assignee: X2Y Attenuators, LLC (Erie, PA)
Inventors: Anthony A. Anthony (Erie, PA), William M. Anthony (Erie, PA)
Primary Examiner: Stephen W Jackson
Application Number: 14/082,082
Classifications
Current U.S. Class: Surge Prevention (e.g., Choke Coil) (361/118)
International Classification: H02H 9/00 (20060101); H05K 9/00 (20060101); H01L 23/50 (20060101); H01L 23/552 (20060101);