Specialized processing block with fixed- and floating-point structures

- Altera Corporation

Circuitry for performing arithmetic operations on a plurality of inputs efficiently performs both fixed-point operations and floating-point operations. Each of at least first and second respective operator circuits operates on a respective subplurality of the plurality of inputs. Other circuitry selectively interconnects the respective operator circuits so that they can operate together or separately, according to user selection, on selected ones of (a) the full plurality of inputs, (b) individual ones of the respective subpluralities of the plurality of inputs, or (c) combinations of portions of the respective subpluralities of the plurality of inputs. At least one of the respective operator circuits includes circuits for simultaneously computing multiple different results and for selecting among the multiple different results based on an output of another one of the respective operator circuits. One or more of the multiple different results are selectably usable to perform both fixed-point operations and floating-point operations.

Skip to: Description  ·  Claims  ·  References Cited  · Patent History  ·  Patent History
Description
FIELD OF THE INVENTION

This invention relates to a programmable integrated circuit device, and particularly to a specialized processing block in a programmable integrated circuit device.

BACKGROUND OF THE INVENTION

Considering a programmable logic device (PLD) as one example of an integrated circuit device, as applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.

One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.

For example, PLDs sold by Altera Corporation, of San Jose, Calif., as part of the STRATIX® and ARRIA® families include DSP blocks, each of which includes a plurality of multipliers. Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components of the block to be configured in different ways.

Typically, the arithmetic operators (adders and multipliers) in such specialized processing blocks have been fixed-point operators. If floating-point operators were needed, the user would construct them outside the specialized processing block using general-purpose programmable logic of the device, or using a combination of the fixed-point operators inside the specialized processing block with additional logic in the general-purpose programmable logic.

One impediment to incorporating floating-point operators directly into specialized processing blocks is the need for large addition operations as part of many floating-point operations. For example, floating-point multiplication may require two carry-propagate adders. The carry-propagate adder used in a multiplication operation is an expensive component of the multiplier in terms of both area and latency.

SUMMARY OF THE INVENTION

In accordance with embodiments of the present invention, specialized processing blocks such as the DSP blocks described above may be enhanced by including floating-point addition among the functions available in the DSP block, without increasing the number of carry-propagate adders. This is accomplished, in part, by simultaneously computing a sum, as well as that sum plus 1 (in its least significant bit) and that sum plus 2 (in its least significant bits), and then selecting the appropriate result based on the result of another part of the operation. The same structures, and, in particular, at least the sum and sum-plus-1 computations, may be used for both fixed-point operations and floating-point operations.

An adder circuit capable of both fixed-point addition and floating-point addition may be incorporated into the DSP block, and can be independently accessed, or used in combination with multipliers in the DSP block, or even multipliers in adjacent DSP blocks. A DSP block incorporating a fixed-and-floating-point-capable adder in accordance with the invention remains backward-compatible with fixed-point functionality of known DSP blocks.

Therefore, in accordance with embodiments of the present invention there is provided circuitry for performing arithmetic operations on a plurality of inputs. The circuitry includes at least first and second respective operator circuits. Each of the at least first and second respective operator circuits operates on a respective subplurality of the plurality of inputs. Other circuitry selectively interconnects the at least first and second respective operator circuits so that they can operate together or separately, according to user selection, on selected ones of (a) the full plurality of inputs, (b) individual ones of the respective subpluralities of the plurality of inputs, or (c) combinations of portions of the respective subpluralities of the plurality of inputs. At least one of the respective operator circuits includes circuits for simultaneously computing multiple different results and for selecting among the multiple different results based on an output of another one of the respective operator circuits. One or more of said multiple different results are selectably usable for both fixed-point operations and floating-point operations.

A specialized processing block incorporating the circuitry, and a programmable integrated circuit device incorporating the specialized processing block, are also provided.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features of the invention, its nature and various advantages will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

FIG. 1 shows a logical diagram of a multiplier structure of an exemplary DSP block according to an embodiment of the invention for performing either fixed-point or floating-point operations;

FIG. 2 shows an embodiment of a deconstructed adder in the structure of FIG. 1;

FIGS. 3A and 3B, hereinafter referred to collectively as FIG. 3, show details of one embodiment of one portion of a deconstructed adder such as that of FIG. 2; and

FIG. 4 is a simplified block diagram of an exemplary system employing a programmable logic device incorporating the present invention.

 DETAILED DESCRIPTION

In a specialized processing block—particularly a DSP block—in accordance with embodiments of the present invention, the adder is decomposed into a prefix structure aligned with both fixed-point and floating-point modes. In known floating-point structures, a carry-propagate adder is used, followed by normalization and then by rounding, which involves a second carry-propagate adder. But according to embodiments of the invention, three floating-point steps can be combined into a single level of carry-propagate adder by calculating different subsets of the carry propagate adder inputs as sum, sum-plus-1, and sum-plus-2. Other subsets of the larger carry-propagate adder are also calculated at the same time. The different subset results can be combined in multiple ways to implement either a floating-point adder or multiplier or multiple different types of fixed-point adder or multiplier combinations. The different subset results can be assembled into the required floating-point or fixed-point values by concatenation, thereby avoiding the need to propagate additional carry values over the subset results to obtain the correct output values.

FIG. 1 shows a logical diagram of the multiplier structure 100 according to an embodiment of the invention for performing either fixed-point or floating-point operations. In this logical representation, implementational details, such as registers and some programmable routing features—such as multiplexers that may allow the output of a particular structure to be routed around certain components or directly out of a DSP block (when implemented in a DSP block)—are omitted to simplify discussion.

In the logical representation of FIG. 1, the “left multiplier” 101 is a partial product generator such as an 18×18 partial product generator (which may be used, e.g., as two 9×18 partial product generators), which produce two dimensionless output vectors 111, 121. Similarly, the “right multiplier” 102 is a partial product generator such as an 18×18 partial product generator (which may be used, e.g., as a 18×9 partial product generator and a 27×9 partial product generator), which produce two dimensionless output vectors 112, 122. Together, partial product generators 101, 102 can be used as a 27×27 partial product generator, to support single-precision floating-point multiplication, which under the IEEE754-1985 standard has a mantissa size of 23 (exclusive of an implied leading ‘1’). Input multiplexer stage 103 combines and aligns between four and six inputs 113 according to the needs of a particular user logic design.

The four dimensionless output vectors 111, 112, 121, 122 are combined by 4:2 compressor 104 into two dimensionless output vectors 114, 124. Multiplexers 105, 106 can be used to align vectors 111, 121 and 121, 122, respectively, according to the type of operation being performed, as determined by the user logic design. Specifically, the vectors can be totally offset from one another (e.g., to perform two separate smaller multiplications, such as two 9×9 multiplications), totally aligned with one another (e.g., to perform one larger multiplication, such as one 18×18 multiplication), or partially aligned with one another (e.g., to perform a “rectangular” multiplication, such as a 9×18 multiplication). In one implementation, each of the input and output vectors of compressor 104 may be up to 74 bits wide.

Another vector 117 may be input from another similar block. Vector 117, along with vectors 114, 124 are input to a 3:2 compressor 108 to provide vectors 118, 128. A further multiplexer 109 selects between vectors 114, 124 and vectors 118, 128, allowing compressor 108 to be bypassed if cascade input 117 is not used. AND gate 107 allows input 117 to be zeroed when, for example, the structure is being used in an accumulator mode and the accumulator has to be reset. Output vectors 119, 129, each up to 74 bits wide, are input to adder 200 to provide the resultant product of the multiplication operation, which can be a fixed-point output 130 or a floating-point output 131. In a floating-point case, the exponent may be handled at 132.

When multiplying two floating-point numbers according to the IEEE754-1985 standard, the input multiplicands are normalized numbers between 1.010 and 1. 910. Therefore, the resultant product can be between 1.010 and 3. 910, and may be subject to normalization and rounding. To accommodate normalization and rounding, it may be necessary to add either zero, 1 or 210 to the least significant bit(s) of the result. Specifically, normalization involves a right-shift of 0 bits or 1 bit (if the result greater than or equal to 1.0 and less than 2.010, the right-shift is 0 bits; if the result is greater than or equal to 2.010 and less than 4.010 the right-shift is 1 bit). In cases where rounding is not applied, whether the normalization is 0 bits or 1 bit, the sum-plus-zero (i.e., the sum) may be used. In cases where rounding is applied, then if the normalization is 0 bits, the sum-plus-1 may be used, while if the normalization is 1 bit, the sum-plus-2 may be used. Therefore, in accordance with embodiments of the invention, and as described in more detail below, those three quantities (sum, sum-plus-1 and sum-plus-2) are generated simultaneously using different portions of the circuitry, and then selected using a carry signal from another portion of the calculation. This avoids the need to wait for that other portion of the calculation before generating the appropriate result (sum, sum-plus-1 or sum-plus-2).

In one embodiment, this is accomplished by decomposing adder 200 into three adders—a low adder 201, a middle adder 202 and a high adder 203. Adders 201, 202, 203 can be used together for a single large fixed-point addition (e.g., adding two 74-bit numbers). For other types of additions (which may result from different multiplication operations), adders 201, 202, 203 can be used in different combinations.

For example, in the example shown in FIG. 2, the inputs of low adder 201 are 23 bits wide, the inputs of adder 202 are 31 bits wide, and the inputs of adder 203 are 20 bits wide. At one extreme, as noted above, adders 201, 202, 203 can be used together to perform a single large fixed-point addition operation (e.g., any addition operation between 55 and 74 bits wide). At the other extreme, adders 201, 202, 203 can be used individually to perform three separate fixed-point addition operations. In between, adders 201, 202, 203 can be used to perform two additions, one or both of which, e.g., may come from separate multipliers. Thus, one addition operation may be performed in low adder 201 and the lower range of middle adder 202, while a second addition operation may be performed in high adder 203 and the upper range of middle adder 202.

When performing two addition operations as just described, each addition operation could be a fixed-point operation. Alternatively, one or both of the two addition operations could be floating-point operations. In the implementation depicted in FIG. 2, the upper addition operation—i.e., the addition operation performed in high adder 230 and the upper range of middle adder 202—would be a fixed-point operation, while the lower addition operation—i.e., the addition operation performed in low adder 201 and the lower range of middle adder 202—could be either a fixed-point operation or a floating-point operation.

Because an addition operation will be spanning the boundary between low adder 201 and middle adder 202, information must be carried across that boundary. As can be seen in FIG. 2, carry information 211 controls multiplexers 212, 222 which, as described in more detail below, are used for fixed-point operations.

In a floating-point context, the location of the least significant bit of the result could actually straddle the boundary—sometimes falling on one side and sometimes falling on the other—depending on the precision and on the particular input values. Information from low adder 201 is needed, along with other information, to establish the location of the least significant bit. Floating-point rounding logic 204 uses the carry information 211, along with the lowermost bits 232 from adder 202 and round-to-nearest-even signal 221 (which combines all but the highest bit from adder 201 in OR-gate 214 to determine the presence of a ‘1’ in any bit location, signifying, when the highest bit from adder 201 is a ‘1’, whether the result from adder 201 is exactly 0.510 or greater than 0.510) to generate selection signal 224 to select the correct floating-point output using multiplexer 242.

As discussed briefly above, depending on the particular inputs, the correct output from adder 202 may be either the sum of its inputs (205), the sum of its inputs with 1 added to the least significant bit (206), or the sum of its inputs with 210 added to the least significant bits (207). In one embodiment, the latter possibility is a possibility only in a floating-point addition, while the other two possibilities are possibilities for either fixed-point addition or floating-point addition. Moreover, where the middle adder 202 is being split between two operations, the upper range output 208 of sum 205 may be output separately.

As also discussed in part above, the selection of the appropriate output(s) from adder 202 is made by multiplexers 212, 222, 242. In the floating-point case, as discussed above, one of sum 205, sum-plus-1 206 and sum-plus-2 207 is selected by multiplexer 242 based on selection signal 224 from floating-point rounding logic 204. In a fixed-point case, multiplexers 212, 222 select between the respective ranges of sum 205 and sum-plus-1 206 based on carry signal 211 from low adder 201 (as noted above, sum plus-2 207 is used only in a floating-point case) or, for multiplexer 212 only, the upper range 208 of the sum.

One possible implementation of middle adder 202 is shown in FIG. 3. 31-bit portions 301, 302 of vectors 119, 129 to be added are input to a half-adder 303, which provides two 32-bit vector outputs, which may be referred to as half-add-sum 313 and half-add-carry 323. Half-add-sum vector 313 is the 31-bit result of the bitwise XOR of vector 301 and vector 302; the 32nd bit is not used. Half-add-carry vector 323 is a 32-bit vector resulting from a 1-bit left-shift of the bitwise AND of vector 301 and vector 302, with a ‘0’ inserted in its least-significant bit position (the most significant bit—i.e., bit 32—of vector 323 is used as carry information from adder 202 to adder 203). The output vectors are divided into lower halves 333, 343 and upper halves 353, 363. These half-adder output vectors are input to a parallel prefix network tree 304, which may include three prefix networks 314, 324, 334. Each prefix network may be, for example, a Kogge-Stone prefix network, which outputs respective generate and propagate vectors.

The lower vectors 333, 343 are input to prefix network 314 to provide generate and propagate vectors 315, 325. The upper vectors 353, 363 are input to prefix network 324 to provide generate and propagate vectors 335, 345. Vectors 335, 345 are input to prefix network 334 along with the prefix(g,p) output 305 of the highest node of network 314. Network 334 outputs generate and propagate vectors 355, 365, which are concatenated with generate and propagate vectors 315, 325 to provide generate and propagate vectors 375, 385.

In order to provide sum output 205, bits 31:2 of half-add vectors 313, 323 are XORed at 306 to provide vector 316, bits 31:3 of which are then XORed at 307 with bits 31:3 of concatenated generate vector 375 to provide vector 317. Vector 317 is then concatenated with the least significant bit 326 of vector 316, and then concatenated with the least significant bit of half-add-sum vector 313 to provide sum 205.

In order to provide sum-plus-1 output 206, bits 31:2 of half-add vectors 313, 323 are XORed at 306 to provide vector 316, bits 31:3 of which are then XORed at 308 with the result of ORing (309) bits 29:1 of concatenated generate vector 375, with the result of ANDing (310) bits 29:1 of concatenated propagate vector 385 and the least significant bit of half-add-sum vector 313, to provide vector 327. Vector 327 is then concatenated with the XOR 318 of the least significant bit of half-add-sum vector 313 and the least-significant bit 326 of vector 316, and then concatenated with the inverse 328 (where nodes 350 are controllable to selectably bypass, or not bypass, inverter 328) of the least significant bit of half-add-sum vector 313 to provide sum-plus-1 206.

Outputs 205 and 206 can be used for both fixed-point and floating-point calculations and therefore are computed to 31 bits of precision. However, in some embodiments sum-plus-2 output 207 might only be used for floating-point operations. Because the mantissa in IEEE754-1985 floating-point operations is 23 bits wide, in such an embodiment sum-plus-2 output 207 need only be 25 bits wide (although in other embodiments, output 207 might be 31 bits wide like the other sum outputs). In order to provide a 25-bit-wide sum-plus-2 output 207, bits 25:2 of half-add vectors 313, 323 are XORed at 306 to provide vector 316, bits 25:3 of which are then XORed at 308 with the result of ORing (309) bits 23:1 of concatenated generate vector 375 with bits 23:1 of concatenated propagate vector 385 to provide vector 327 (where nodes 360 are controllable to selectably bypass, or not bypass, adder 310). Vector 327 is then concatenated with inverse 338 (where nodes 370 are controllable to selectably bypass, or not bypass, inverter 338) of the XOR 318 of the least significant bit of half-add-sum vector 313 and the least-significant bit 326 of vector 316, and then concatenated with the least significant bit of half-add-sum vector 313 to provide sum-plus-2 207.

As discussed above, the upper range output 208 of middle adder 202 could be provided separately—e.g., for combining with the output of high adder 203. There are at least two ways to provide upper range output 208.

One way to provide upper range output 208 is to compute sum 205 as described above, but to partition it into upper and lower portions by disconnecting output 305 of prefix network 314 from prefix network 334 and zeroing bit 15 of half-add-carry 323. Upper range output 208 may then be read directly from the upper 17 bits 31:15 of sum 205.

A second way to provide upper range output 208 is to XOR (390) upper bits 31:17 only of upper portions 353, 363 (31:15) of vectors 313, 323 to produce 15-bit vector 391, then to XOR (392) vector 391 with generate vector 393 (which is the least significant bits of the 17 bits of generate vector 335) from prefix network 324 to provide 15-bit vector 394. Vector 394 may be concatenated with the XOR (395) of respective bits 16 of upper portions 353, 363, and that result may be concatenated with the lowest bit (bit 15) of upper portion 353 of half-add-sum 313 to provide 17-bit output 208.

As discussed above, low, middle and high adders 201, 202, 203 may be combined to perform a single fixed-point operation on their combined of inputs. Alternatively, each of low, middle and high adders 201, 202, 203 may perform a separate respective fixed-point operation on its respective inputs. Finally, portions of different ones of low, middle and high adders 201, 202, 203 may be used together to perform separate operations that are selectably fixed-point operations or floating-point operations. Therefore, as described, the decomposed adder structure of FIGS. 2 and 3 can be used to provide, in hardware, both fixed-point addition and floating-point addition, which in turn can support fixed-point and floating-point multiplication operations.

A PLD 90 incorporating specialized processing blocks according to the present invention may be used in many kinds of electronic devices. One possible use is in an exemplary data processing system 900 shown in FIG. 4. Data processing system 900 may include one or more of the following components: a processor 901; memory 902; I/O circuitry 903; and peripheral devices 904. These components are coupled together by a system bus 905 and are populated on a circuit board 906 which is contained in an end-user system 907.

System 900 can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD 90 can be used to perform a variety of different logic functions. For example, PLD 90 can be configured as a processor or controller that works in cooperation with processor 901. PLD 90 may also be used as an arbiter for arbitrating access to a shared resources in system 900. In yet another example, PLD 90 can be configured as an interface between processor 901 and one of the other components in system 900. It should be noted that system 900 is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims.

Various technologies can be used to implement PLDs 90 as described above and incorporating this invention.

It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the various elements of this invention can be provided on a PLD in any desired number and/or arrangement. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow.

Claims

1. Circuitry for performing arithmetic operations on a plurality of inputs, said circuit comprising:

at least first and second respective operator circuits, each of said at least first and second respective operator circuits operating on a respective subplurality of said plurality of inputs; and
circuitry for selectively interconnecting said at least first and second respective operator circuits so that they can operate together or separately, according to user selection, on selected ones of (a) said full plurality of inputs, (b) individual ones of said respective subpluralities of said plurality of inputs, or (c) combinations of portions of said respective subpluralities of said plurality of inputs; wherein:
at least one of said respective operator circuits includes circuits for simultaneously computing multiple different results and for selecting among said multiple different results based on an output of another one of said respective operator circuits;
said multiple different results comprise sum, sum-plus-1 and sum-plus-2 results; and
one or more of said multiple different results are selectably usable for both fixed-point operations and floating-point operations.

2. The circuitry for performing of claim 1 wherein:

each of said respective operator circuits comprises a fixed-point adder circuit; and
said circuitry for selectively interconnecting comprises control circuitry that receives inputs from two of said respective operator circuits, so that said two of said respective operator circuits provide a floating-point addition of portions of their respective subpluralities of said plurality of inputs.

3. The circuitry for performing of claim 2 further comprising at least one partial product generator; wherein:

outputs of said at least one partial product generator are input to said two of said respective operator circuits provide a floating-point multiplication of inputs of said at least one partial product generator.

4. The circuitry for performing of claim 1 wherein said circuits for simultaneously computing comprise a half-adder and a prefix network tree.

5. The circuitry for performing of claim 4 wherein:

said prefix network tree comprises first, second and third prefix networks;
said first prefix network receives, as inputs, a first subset of outputs of said half-adder;
said second prefix network receives, as inputs, a second subset of outputs of said half-adder; and
said third prefix network receives, as inputs, outputs of said second prefix network and an output of a most significant node of said first prefix network.

6. The circuitry for performing of claim 5 wherein:

input of said output of said most significant node of said first prefix network to said third prefix network is enabled; and
output of said third prefix network is used to provide a combined sum of said first subset of outputs of said half-adder and said second subset of outputs of said half-adder, as well as a combined sum-plus-1 and a combined sum-plus-2.

7. The circuitry for performing of claim 5 wherein:

input of said output of said most significant node of said first prefix network to said third prefix network is disabled; and
output of said third prefix network is used to provide separate sums of said first subset of outputs of said half-adder and said second subset of outputs of said half-adder.

8. A specialized processing block on a programmable integrated circuit device, said specialized processing block comprising:

at least one partial product generator providing a plurality of outputs;
at least first and second respective adder circuits, each of said at least first and second respective adder circuits operating on a respective subplurality of said plurality of outputs; and
circuitry for selectively interconnecting said at least first and second respective adder circuits so that they can operate together or separately, according to user selection, on selected ones of (a) said full plurality of outputs, (b) individual ones of said respective subpluralities of said plurality of outputs, or (c) combinations of portions of said respective subpluralities of said plurality of outputs; wherein:
at least one of said respective adder circuits includes circuits for simultaneously computing multiple different results and for selecting among said multiple different results based on an output of another one of said respective adder circuits; and
said multiple different results comprise sum, sum-plus-1 and sum-plus-2 results.

9. The specialized processing block of claim 8 wherein:

each of said respective adder circuits comprises a fixed-point adder circuit; and
said circuitry for selectively interconnecting comprises control circuitry that receives inputs from two of said respective adder circuits, so that said two of said respective operator circuits provide a floating-point addition of portions of their respective subpluralities of said plurality of outputs.

10. The specialized processing block of claim 8 wherein said circuits for simultaneously computing comprise a half-adder and a prefix network tree.

11. The specialized processing block of claim 10 wherein:

said prefix network tree comprises first, second and third prefix networks;
said first prefix network receives, as inputs, a first subset of outputs of said half-adder;
said second prefix network receives, as inputs, a second subset of outputs of said half-adder; and
said third prefix network receives, as inputs, outputs of said second prefix network and an output of a most significant node of said first prefix network.

12. The specialized processing block of claim 11 wherein:

input of said output of said most significant node of said first prefix network to said third prefix network is enabled; and
output of said third prefix network is used to provide a combined sum of said first subset of outputs of said half-adder and said second subset of outputs of said half-adder, as well as a combined sum-plus-1 and a combined sum-plus-2.

13. The specialized processing block of claim 11 wherein:

input of said output of said most significant node of said first prefix network to said third prefix network is disabled; and
output of said third prefix network is used to provide separate sums of said first subset of outputs of said half-adder and said second subset of outputs of said half-adder.

14. A programmable integrated circuit device comprising:

a plurality of specialized processing blocks, each of said specialized processing blocks comprising:
at least one partial product generator providing a plurality of outputs;
at least first and second respective adder circuits, each of said at least first and second respective adder circuits operating on a respective subplurality of said plurality of outputs; and
circuitry for selectively interconnecting said at least first and second respective adder circuits so that they can operate together or separately, according to user selection, on selected ones of (a) said full plurality of outputs, (b) individual ones of said respective subpluralities of said plurality of outputs, or (c) combinations of portions of said respective subpluralities of said plurality of outputs; wherein:
at least one of said respective adder circuits includes circuits for simultaneously computing multiple different results and for selecting among said multiple different results based on an output of another one of said respective adder circuits; and
said multiple different results comprise sum, sum-plus-1 and sum-plus-2 results.

15. The programmable integrated circuit device of claim 14 wherein:

each of said respective adder circuits comprises a fixed-point adder circuit; and
said circuitry for selectively interconnecting comprises control circuitry that receives inputs from two of said respective adder circuits, so that said two of said respective operator circuits provide a floating-point addition of portions of their respective subpluralities of said plurality of outputs.

16. The programmable integrated circuit device of claim 14 wherein said circuits for simultaneously computing comprise a half-adder and a prefix network tree.

17. The programmable integrated circuit device of claim 16 wherein:

said prefix network tree comprises first, second and third prefix networks;
said first prefix network receives, as inputs, a first subset of outputs of said half-adder;
said second prefix network receives, as inputs, a second subset of outputs of said half-adder; and
said third prefix network receives, as inputs, outputs of said second prefix network and an output of a most significant node of said first prefix network.

18. The programmable integrated circuit device of claim 17 wherein:

input of said output of said most significant node of said first prefix network to said third prefix network is enabled; and
output of said third prefix network is used to provide a combined sum of said first subset of outputs of said half-adder and said second subset of outputs of said half-adder, as well as a combined sum-plus-1 and a combined sum-plus-2.

19. The programmable integrated circuit device of claim 17 wherein:

input of said output of said most significant node of said first prefix network to said third prefix network is disabled; and
output of said third prefix network is used to provide separate sums of said first subset of outputs of said half-adder and said second subset of outputs of said half-adder.
Referenced Cited
U.S. Patent Documents
3473160 October 1969 Wahlstrom
3697734 October 1972 Booth et al.
3800130 March 1974 Martinson et al.
4156927 May 29, 1979 McElroy et al.
4179746 December 18, 1979 Tubbs
4212076 July 8, 1980 Conners
4215406 July 29, 1980 Gomola et al.
4215407 July 29, 1980 Gomola et al.
4422155 December 20, 1983 Amir et al.
4484259 November 20, 1984 Palmer et al.
4521907 June 4, 1985 Amir et al.
4575812 March 11, 1986 Kloker et al.
4597053 June 24, 1986 Chamberlin
4616330 October 7, 1986 Betz
4623961 November 18, 1986 Mackiewicz
4682302 July 21, 1987 Williams
4718057 January 5, 1988 Venkitakrishnan et al.
4727508 February 23, 1988 Williams
4736335 April 5, 1988 Barban
4754421 June 28, 1988 Bosshart
4791590 December 13, 1988 Ku et al.
4799004 January 17, 1989 Mori
4823260 April 18, 1989 Imel et al.
4823295 April 18, 1989 Mader
4839847 June 13, 1989 Laprade
4871930 October 3, 1989 Wong et al.
4893268 January 9, 1990 Denman et al.
4908788 March 13, 1990 Fujiyama
4912345 March 27, 1990 Steele et al.
4918637 April 17, 1990 Morton
4967160 October 30, 1990 Quievy et al.
4982354 January 1, 1991 Takeuchi et al.
4991010 February 5, 1991 Hailey et al.
4994997 February 19, 1991 Martin et al.
4999803 March 12, 1991 Turrini et al.
5073863 December 17, 1991 Zhang
5081604 January 14, 1992 Tanaka
5122685 June 16, 1992 Chan et al.
5128559 July 7, 1992 Steele
5175702 December 29, 1992 Beraud et al.
5208491 May 4, 1993 Ebeling et al.
RE34363 August 31, 1993 Freeman
5267187 November 30, 1993 Hsieh et al.
5296759 March 22, 1994 Sutherland et al.
5338983 August 16, 1994 Agarwala
5339263 August 16, 1994 White
5349250 September 20, 1994 New
5357152 October 18, 1994 Jennings, III et al.
5371422 December 6, 1994 Patel et al.
5373461 December 13, 1994 Bearden et al.
5375079 December 20, 1994 Uramoto et al.
5381357 January 10, 1995 Wedgwood et al.
5404324 April 4, 1995 Colon-Benet
5424589 June 13, 1995 Dobbelaere et al.
5446651 August 29, 1995 Moyse et al.
5451948 September 19, 1995 Jekel
5452231 September 19, 1995 Butts et al.
5452375 September 19, 1995 Rousseau et al.
5457644 October 10, 1995 McCollum
5465226 November 7, 1995 Goto
5465375 November 7, 1995 Thepaut et al.
5483178 January 9, 1996 Costello et al.
5497498 March 5, 1996 Taylor
5500812 March 19, 1996 Saishi et al.
5500828 March 19, 1996 Doddington et al.
5523963 June 4, 1996 Hsieh et al.
5528550 June 18, 1996 Pawate et al.
5537601 July 16, 1996 Kimura et al.
5541864 July 30, 1996 Van Bavel et al.
5546018 August 13, 1996 New et al.
5550993 August 27, 1996 Ehlig et al.
5559450 September 24, 1996 Ngai et al.
5563526 October 8, 1996 Hastings et al.
5563819 October 8, 1996 Nelson
5570039 October 29, 1996 Oswald et al.
5570040 October 29, 1996 Lytle et al.
5572148 November 5, 1996 Lytle et al.
5581501 December 3, 1996 Sansbury et al.
5590350 December 31, 1996 Guttag et al.
5594366 January 14, 1997 Khong et al.
5594912 January 14, 1997 Brueckmann et al.
5596763 January 21, 1997 Guttag et al.
5606266 February 25, 1997 Pedersen
5617058 April 1, 1997 Adrian et al.
5631848 May 20, 1997 Laczko et al.
5631859 May 20, 1997 Markstein et al.
5633601 May 27, 1997 Nagaraj
5636150 June 3, 1997 Okamoto
5636368 June 3, 1997 Harrison et al.
5640578 June 17, 1997 Balmer et al.
5644519 July 1, 1997 Yatim et al.
5644522 July 1, 1997 Moyse et al.
5646545 July 8, 1997 Trimberger et al.
5646875 July 8, 1997 Taborn et al.
5648732 July 15, 1997 Duncan
5652903 July 29, 1997 Weng et al.
5655069 August 5, 1997 Ogawara et al.
5664192 September 2, 1997 Lloyd et al.
5689195 November 18, 1997 Cliff et al.
5696708 December 9, 1997 Leung
5729495 March 17, 1998 Madurawe
5740404 April 14, 1998 Baji
5744980 April 28, 1998 McGowan et al.
5744991 April 28, 1998 Jefferson et al.
5754459 May 19, 1998 Telikepalli
5761483 June 2, 1998 Trimberger
5764555 June 9, 1998 McPherson et al.
5768613 June 16, 1998 Asghar
5771186 June 23, 1998 Kodali et al.
5777912 July 7, 1998 Leung et al.
5784636 July 21, 1998 Rupp
5790446 August 4, 1998 Yu et al.
5794067 August 11, 1998 Kadowaki
5801546 September 1, 1998 Pierce et al.
5805477 September 8, 1998 Perner
5805913 September 8, 1998 Guttag et al.
5808926 September 15, 1998 Gorshtein et al.
5812479 September 22, 1998 Cliff et al.
5812562 September 22, 1998 Baeg
5815422 September 29, 1998 Dockser
5821776 October 13, 1998 McGowan
5825202 October 20, 1998 Tavana et al.
5838165 November 17, 1998 Chatter
5841684 November 24, 1998 Dockser
5847579 December 8, 1998 Trimberger
5847978 December 8, 1998 Ogura et al.
5847981 December 8, 1998 Kelley et al.
5859878 January 12, 1999 Phillips et al.
5869979 February 9, 1999 Bocchino
5872380 February 16, 1999 Rostoker et al.
5874834 February 23, 1999 New
5878250 March 2, 1999 LeBlanc
5880981 March 9, 1999 Kojima et al.
5892962 April 6, 1999 Cloutier
5894228 April 13, 1999 Reddy et al.
5898602 April 27, 1999 Rothman et al.
5931898 August 3, 1999 Khoury
5942914 August 24, 1999 Reddy et al.
5944774 August 31, 1999 Dent
5949710 September 7, 1999 Pass et al.
5951673 September 14, 1999 Miyata
5956265 September 21, 1999 Lewis
5959871 September 28, 1999 Pierzchala et al.
5960193 September 28, 1999 Guttag et al.
5961635 October 5, 1999 Guttag et al.
5963048 October 5, 1999 Harrison et al.
5963050 October 5, 1999 Young et al.
5968196 October 19, 1999 Ramamurthy et al.
5970254 October 19, 1999 Cooke et al.
5978260 November 2, 1999 Trimberger et al.
5982195 November 9, 1999 Cliff et al.
5986465 November 16, 1999 Mendel
5991788 November 23, 1999 Mintzer
5991898 November 23, 1999 Rajski et al.
5995748 November 30, 1999 Guttag et al.
5999015 December 7, 1999 Cliff et al.
5999990 December 7, 1999 Sharrit et al.
6005806 December 21, 1999 Madurawe et al.
6006321 December 21, 1999 Abbott
6009451 December 28, 1999 Burns
6018755 January 25, 2000 Gonikberg et al.
6020759 February 1, 2000 Heile
6021423 February 1, 2000 Nag et al.
6029187 February 22, 2000 Verbauwhede
6031763 February 29, 2000 Sansbury
6041339 March 21, 2000 Yu et al.
6041340 March 21, 2000 Mintzer
6052327 April 18, 2000 Reddy et al.
6052755 April 18, 2000 Terrill et al.
6052773 April 18, 2000 DeHon et al.
6055555 April 25, 2000 Boswell et al.
6064614 May 16, 2000 Khoury
6065131 May 16, 2000 Andrews et al.
6066960 May 23, 2000 Pedersen
6069487 May 30, 2000 Lane et al.
6072994 June 6, 2000 Phillips et al.
6073154 June 6, 2000 Dick
6075381 June 13, 2000 LaBerge
6084429 July 4, 2000 Trimberger
6085317 July 4, 2000 Smith
6091261 July 18, 2000 De Lange
6091765 July 18, 2000 Pietzold, III et al.
6094726 July 25, 2000 Gonion et al.
6097988 August 1, 2000 Tobias
6098163 August 1, 2000 Guttag et al.
6107820 August 22, 2000 Jefferson et al.
6107821 August 22, 2000 Kelem et al.
6107824 August 22, 2000 Reddy et al.
6108772 August 22, 2000 Sharangpani
6130554 October 10, 2000 Kolze et al.
6140839 October 31, 2000 Kaviani et al.
6144980 November 7, 2000 Oberman
6154049 November 28, 2000 New
6157210 December 5, 2000 Zaveri et al.
6163788 December 19, 2000 Chen et al.
6167415 December 26, 2000 Fischer et al.
6175849 January 16, 2001 Smith
6215326 April 10, 2001 Jefferson et al.
6226735 May 1, 2001 Mirsky
6242947 June 5, 2001 Trimberger
6243729 June 5, 2001 Staszewski
6246258 June 12, 2001 Lesea
6260053 July 10, 2001 Maulik et al.
6279021 August 21, 2001 Takano et al.
6286024 September 4, 2001 Yano et al.
6314442 November 6, 2001 Suzuki
6314551 November 6, 2001 Borland
6321246 November 20, 2001 Page et al.
6323680 November 27, 2001 Pedersen et al.
6327605 December 4, 2001 Arakawa et al.
6346824 February 12, 2002 New
6351142 February 26, 2002 Abbott
6353843 March 5, 2002 Chehrazi et al.
6359468 March 19, 2002 Park et al.
6360240 March 19, 2002 Takano et al.
6362650 March 26, 2002 New et al.
6366944 April 2, 2002 Hossain et al.
6367003 April 2, 2002 Davis
6369610 April 9, 2002 Cheung et al.
6377970 April 23, 2002 Abdallah et al.
6407576 June 18, 2002 Ngai et al.
6407694 June 18, 2002 Cox et al.
6427157 July 30, 2002 Webb
6434587 August 13, 2002 Liao et al.
6438569 August 20, 2002 Abbott
6438570 August 20, 2002 Miller
6446107 September 3, 2002 Knowles
6453382 September 17, 2002 Heile
6467017 October 15, 2002 Ngai et al.
6480980 November 12, 2002 Koe
6483343 November 19, 2002 Faith et al.
6487575 November 26, 2002 Oberman
6523055 February 18, 2003 Yu et al.
6523057 February 18, 2003 Savo et al.
6531888 March 11, 2003 Abbott
6538470 March 25, 2003 Langhammer et al.
6542000 April 1, 2003 Black et al.
6556044 April 29, 2003 Langhammer et al.
6557092 April 29, 2003 Callen
6564238 May 13, 2003 Kim et al.
6571268 May 27, 2003 Giacalone et al.
6573749 June 3, 2003 New et al.
6574762 June 3, 2003 Karimi et al.
6578060 June 10, 2003 Chen et al.
6591283 July 8, 2003 Conway et al.
6591357 July 8, 2003 Mirsky
6600495 July 29, 2003 Boland et al.
6600788 July 29, 2003 Dick et al.
6628140 September 30, 2003 Langhammer et al.
6687722 February 3, 2004 Larsson et al.
6692534 February 17, 2004 Wang et al.
6700581 March 2, 2004 Baldwin et al.
6725441 April 20, 2004 Keller et al.
6728901 April 27, 2004 Rajski et al.
6731133 May 4, 2004 Feng et al.
6732134 May 4, 2004 Rosenberg et al.
6744278 June 1, 2004 Liu et al.
6745254 June 1, 2004 Boggs et al.
6763367 July 13, 2004 Kwon et al.
6771094 August 3, 2004 Langhammer et al.
6774669 August 10, 2004 Liu et al.
6781408 August 24, 2004 Langhammer
6781410 August 24, 2004 Pani et al.
6788104 September 7, 2004 Singh et al.
6801924 October 5, 2004 Green et al.
6836839 December 28, 2004 Master et al.
6874079 March 29, 2005 Hogenauer
6889238 May 3, 2005 Johnson
6904471 June 7, 2005 Boggs et al.
6915322 July 5, 2005 Hong
6924663 August 2, 2005 Masui et al.
6963890 November 8, 2005 Dutta et al.
6971083 November 29, 2005 Farrugia et al.
6978287 December 20, 2005 Langhammer
6983300 January 3, 2006 Ferroussat
7020673 March 28, 2006 Ozawa
7024446 April 4, 2006 Langhammer et al.
7047272 May 16, 2006 Giacalone et al.
7062526 June 13, 2006 Hoyle
7093204 August 15, 2006 Oktem et al.
7107305 September 12, 2006 Deng et al.
7113969 September 26, 2006 Green et al.
7181484 February 20, 2007 Stribaek et al.
7230451 June 12, 2007 Langhammer
7313585 December 25, 2007 Winterrowd
7343388 March 11, 2008 Burney et al.
7395298 July 1, 2008 Debes et al.
7401109 July 15, 2008 Koc et al.
7409417 August 5, 2008 Lou
7415542 August 19, 2008 Hennedy et al.
7421465 September 2, 2008 Rarick et al.
7428565 September 23, 2008 Fujimori
7428566 September 23, 2008 Siu et al.
7430578 September 30, 2008 Debes et al.
7430656 September 30, 2008 Sperber et al.
7447310 November 4, 2008 Koc et al.
7472155 December 30, 2008 Simkins et al.
7508936 March 24, 2009 Eberle et al.
7536430 May 19, 2009 Guevokian et al.
7567997 July 28, 2009 Simkins et al.
7590676 September 15, 2009 Langhammer
7646430 January 12, 2010 Brown Elliott et al.
7650374 January 19, 2010 Gura et al.
7668896 February 23, 2010 Lutz et al.
7719446 May 18, 2010 Rosenthal et al.
7720898 May 18, 2010 Driker et al.
7769797 August 3, 2010 Cho et al.
7814136 October 12, 2010 Verma et al.
7814137 October 12, 2010 Mauer
7822799 October 26, 2010 Langhammer et al.
7836117 November 16, 2010 Langhammer et al.
7865541 January 4, 2011 Langhammer
7917567 March 29, 2011 Mason et al.
7930335 April 19, 2011 Gura
7930336 April 19, 2011 Langhammer
7949699 May 24, 2011 Neoh et al.
8024394 September 20, 2011 Prokopenko et al.
8041759 October 18, 2011 Langhammer et al.
8090758 January 3, 2012 Shimanek et al.
8112466 February 7, 2012 Minz et al.
8447800 May 21, 2013 Dockser et al.
8468191 June 18, 2013 Mantor et al.
8595279 November 26, 2013 Dockser
8751551 June 10, 2014 Streicher et al.
20010023425 September 20, 2001 Oberman et al.
20010029515 October 11, 2001 Mirsky
20010037352 November 1, 2001 Hong
20020002573 January 3, 2002 Landers et al.
20020032713 March 14, 2002 Jou et al.
20020038324 March 28, 2002 Page et al.
20020049798 April 25, 2002 Wang et al.
20020078114 June 20, 2002 Wang et al.
20020089348 July 11, 2002 Langhammer
20020116434 August 22, 2002 Nancekievill
20020143841 October 3, 2002 Farooqui et al.
20030065699 April 3, 2003 Burns
20030088757 May 8, 2003 Lindner et al.
20040064770 April 1, 2004 Xin
20040083412 April 29, 2004 Corbin et al.
20040103133 May 27, 2004 Gurney
20040122882 June 24, 2004 Zakharov et al.
20040148321 July 29, 2004 Guevorkian et al.
20040172439 September 2, 2004 Lin
20040178818 September 16, 2004 Crotty et al.
20040193981 September 30, 2004 Clark et al.
20040267857 December 30, 2004 Abel et al.
20040267863 December 30, 2004 Bhushan et al.
20050038842 February 17, 2005 Stoye
20050120122 June 2, 2005 Farnham
20050144212 June 30, 2005 Simkins et al.
20050144215 June 30, 2005 Simkins et al.
20050144216 June 30, 2005 Simkins et al.
20050166038 July 28, 2005 Wang et al.
20050187997 August 25, 2005 Zheng et al.
20050187999 August 25, 2005 Zheng et al.
20050262175 November 24, 2005 Iino et al.
20060020655 January 26, 2006 Lin
20060112160 May 25, 2006 Ishii et al.
20070083585 April 12, 2007 St. Denis et al.
20070185951 August 9, 2007 Lee et al.
20070185952 August 9, 2007 Langhammer et al.
20070241773 October 18, 2007 Hutchings et al.
20080133627 June 5, 2008 Langhammer et al.
20080159441 July 3, 2008 Liao et al.
20080183783 July 31, 2008 Tubbs
20090083358 March 26, 2009 Allen
20090113186 April 30, 2009 Kato et al.
20090172052 July 2, 2009 DeLaquil et al.
20090182795 July 16, 2009 Dobbek et al.
20090187615 July 23, 2009 Abe et al.
20090228689 September 10, 2009 Muff et al.
20090292750 November 26, 2009 Reyzin et al.
20090300088 December 3, 2009 Michaels et al.
20090300323 December 3, 2009 Hessel et al.
20100098189 April 22, 2010 Oketani
20100146022 June 10, 2010 Swartzlander et al.
20100191939 July 29, 2010 Muff et al.
20110106868 May 5, 2011 Lutz
20110137970 June 9, 2011 Dockser et al.
20110161389 June 30, 2011 Langhammer et al.
20110219052 September 8, 2011 Langhammer
20110238720 September 29, 2011 Langhammer
20110320513 December 29, 2011 Langhammer
20120054254 March 1, 2012 Langhammer
20120054256 March 1, 2012 Langhammer
20120166512 June 28, 2012 Wong et al.
20130138711 May 30, 2013 Sugisawa
20140067895 March 6, 2014 Wang
20140089371 March 27, 2014 De Dinechin et al.
Foreign Patent Documents
0 158 430 October 1985 EP
0 380 456 August 1990 EP
0 411 491 February 1991 EP
0 419 105 March 1991 EP
0 461 798 December 1991 EP
0 498 066 August 1992 EP
0 555 092 August 1993 EP
0 606 653 July 1994 EP
0 657 803 June 1995 EP
0 660 227 June 1995 EP
0 668 659 August 1995 EP
0 721 159 July 1996 EP
0 905 906 March 1999 EP
0 909 028 April 1999 EP
0 927 393 July 1999 EP
0 992 885 April 2000 EP
1 031 934 August 2000 EP
1 058 185 December 2000 EP
1 220 108 July 2002 EP
2 283 602 May 1995 GB
2 286 737 August 1995 GB
2 318 198 April 1998 GB
61-237133 October 1986 JP
63-216131 August 1988 JP
4-332036 November 1992 JP
5-134851 June 1993 JP
06-187129 July 1994 JP
7-135447 May 1995 JP
11-296345 October 1999 JP
2000-259394 September 2000 JP
2002-108606 April 2002 JP
2002-251281 September 2002 JP
WO95-27243 October 1995 WO
WO96-28774 September 1996 WO
WO97-08606 March 1997 WO
WO98-12629 March 1998 WO
WO98-32071 July 1998 WO
WO98-38741 September 1998 WO
WO99-22292 May 1999 WO
WO99-31574 June 1999 WO
WO99-56394 November 1999 WO
WO00-51239 August 2000 WO
WO00-52824 September 2000 WO
WO01-13562 February 2001 WO
WO 2005/066832 July 2005 WO
WO2005-101190 October 2005 WO
Other references
  • Xilinx, Inc., “Implementing Barrel Shifters Using Multipliers,” p. 1-4, Aug. 17, 2004.
  • Altera, “DSP Blocks in Stratix III Devices”, Chapter 5, pp. 1-42, Mar. 2010.
  • Karlström, P., et al., “High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4,” Norchip Conf., pp. 31-34, 2006.
  • Thapliyal, H., et al., “Combined Integer and Floating Point Multiplication Architecture (CIFM) for FPGSs and Its Reversible Logic Implementation”, Proceedings MWSCAS 2006, Puerto Rico, 5 pages, Aug. 2006.
  • Thapliyal, H., et al., “Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs”, Proceedings of the 2007 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'07), Las Vegas, US, vol. 1, pp. 449-450, Jun. 2007.
  • Xilinx, Inc., “Virtex-5 ExtremeDSP Design Considerations,” User Guide UG193, v2.6, 114 pages, Oct. 2007.
  • Altera Corporation, “Statix II Device Handbook, Chapter 6—DSP Blocks in Stratix II Devices,” v1.1, Jul. 2004.
  • Altera Corporation, “Digital Signal Processing (DSP),” Stratix Device Handbook, vol. 2, Chapter 6 and Chapter 7, v1.1 (Sep. 2004).
  • Altera Corporation, “DSP Blocks in Stratix II and Stratix II GX Devices,” Stratix II Device Handbook, vol. 2, Chapter 6, v4.0 (Oct. 2005).
  • Altera Corporation, “FIR Compiler: MegaCore® Function User Guide,” version 3.3.0, rev. 1, pp. 3 11 through 3 15 (Oct. 2005).
  • Altera Corporation, “Advanced Synthesis Cookbook: A Design Guide for Stratix II, Stratix III and Stratix IV Devices,” Document Version 3.0, 112 pgs., May 2008.
  • Amos, D., “Pld architectures match DSP algorithms,” Electronic Product Design, vol. 17, No. 7, Jul. 1996, pp. 30, 32.
  • Analog Devices, Inc., The Applications Engineering Staff of Analog Devices, DSP Division, Digital Signal Processing Applications Using the ADSP-2100 Family (edited by Amy Mar), 1990, pp. 141-192).
  • Andrejas, J., et al., “Reusable DSP functions in FPGAs,” Field-Programmable Logic and Applications. Roadmap to Reconfigurable Computing. 10th International Conference, FPL 2000. Proceedings (Lecture Notes in Computer Science vol. 1896), Aug. 27-30, 2000, pp. 456-461.
  • Aoki, T., “Signed-weight arithmetic and its application to a field-programmable digital filter architecture,” IEICE Transactions on Electronics , 1999 , vol. E82C, No. 9, Sep. 1999, pp. 1687-1698.
  • Ashour, M.A., et al., “An FPGA implementation guide for some different types of serial-parallel multiplier-structures,” Microelectronics Journal , vol. 31, No. 3, 2000, pp. 161-168.
  • Berg, B.L., et al.“Designing Power and Area Efficient Multistage FIR Decimators with Economical Low Order Filters,” ChipCenter Technical Note, Dec. 2001.
  • Bursky, D., “Programmable Logic Challenges Traditional ASIC SoC Designs”, Electronic Design, Apr. 15, 2002.
  • Chhabra, A. et al., Texas Instruments Inc., “A Block Floating Point Implementation on the TMS320C54x DSP”, Application Report SPRA610, Dec. 1999, pp. 1-10.
  • Colet, P., “When DSPs and FPGAs meet: Optimizing image processing architectures,” Advanced Imaging, vol. 12, No. 9, Sep. 1997, pp. 14, 16, 18.
  • Crookes, D., et al., “Design and implementation of a high level programming environment for FPGA-based image processing,” IEE Proceedings-Vision, Image and Signal Processing, vol. 147, No. 4, Aug. 2000, pp. 377-384.
  • Debowski, L., et al., “A new flexible architecture of digital control systems based on DSP and complex CPLD technology for power conversion applications,” PCIM 2000: Europe Official Proceedings of the Thirty-Seventh International Intelligent Motion Conference, Jun. 6-8, 2000, pp. 281-286.
  • de Dinechin, F. et al., “Large multipliers with less DSP blocks,” retrieved from http://hal-ens-lyon.archives-ouvertes.fr/ensl-00356421/en/, 9 pgs., available online Jan. 2009.
  • Dick, C., et al., “Configurable logic for digital communications: some signal processing perspectives,” IEEE Communications Magazine, vol. 37, No. 8, Aug. 1999, pp. 107-111.
  • Do, T.-T., et al., “A flexible implementation of high-performance FIR filters on Xilinx FPGAs,” Field-Programmable Logic and Applications: From FPGAs to Computing Paradigm. 8th International Workshop, FPL'98. Proceedings, Hartenstein, R.W., et al., eds., Aug. 31-Sep. 3, 1998, pp. 441-445.
  • Gaffer, A.A., et al., “Floating-Point Bitwidth Analysis via Automatic Differentiation,” IEEE Conference on Field Programmable Technology, Hong Kong, Dec. 2002.
  • Govindu, G. et al., “A Library of Parameterizable Floating-Point Cores for FPGAs and Their Application to Scientific Computing,” Proc Int'l Conf. Eng. Reconfigurable Systems and Algorithms (ERSA'05), Jun. 2005.
  • Govindu, G. et al., “Analysis of High-performance Floating-point Arithmetic on FPGAs,” Proceedings of the 18th International Parallel and Distributed Processing Symposium (PDPS'04) pp. 149-156, Apr. 2004.
  • Guccione, S.A.,“Run-time Reconfiguration at Xilinx,” Parallel and distributed processing: 15 IPDPS 2000 workshops, Rolim, J., ed., May 1-5, 2000, p. 873.
  • Hauck, S., “The Future of Reconfigurable Systems,” Keynote Address, 5th Canadian Conference on Field Programmable Devices, Jun. 1998, http:--www.ee.washington.edu-people-faculty-hauck-publications-ReconfigFuture.PDF.
  • Haynes, S.D., et al., “Configurable multiplier blocks for embedding in FPGAs,” Electronicas Letters, vol. 34, No. 7, pp. 638-639 (Apr. 2, 1998).
  • Heysters, P.M., et al., “Mapping of DSP algorithms on field programmable function arrays,” Field-Programmable Logic and Applications. Roadmap to Reconfigurable Computing. 10th International Conference, FPL 2000 Proceedings (Lecture Notes in Computer Science vol. 1896), Aug. 27-30, 2000, pp. 400-411.
  • Huang, J., et al., “Simulated Performance of 1000BASE-T Receiver with Different Analog Front End Designs,” Proceedings of the 35th Asilomar Conference on Signals, Systems, and Computers, Nov. 4-7, 2001.
  • Lattice Semiconductor Corp, ORCA® FPGA Express™ Interface Manual: ispLEVER® Version 3.0, 2002.
  • Lucent Technologies, Microelectronics Group,“Implementing and Optimizing Multipliers in ORCA™ FPGAs,”, Application Note.AP97-008FGPA, Feb. 1997.
  • “Implementing Multipliers in FLEX 10K EABs”, Altera, Mar. 1996.
  • “Implementing Logic with the Embedded Array in FLEX 10K Devices”, Altera, May 2001, ver. 2.1.
  • Jinghua Li, “Design a pocket multi-bit multiplier in FPGA,” 1996 2nd International Conference on ASIC Proceedings (IEEE Cat. No. 96TH8140), Oct. 21-24, 1996, pp. 275-279.
  • Jones, G., “Field-programmable digital signal conditioning,” Electronic Product Design, vol. 21, No. 6, Jun. 2000, pp. C36-C38.
  • Kiefer, R., et al., “Performance comparison of software-FPGA hardware partitions for a DSP application,” 14th Australian Microelectronics Conference. Microelectronics: Technology Today for the Future. MICRO '97 Proceedings, Sep. 28-Oct. 1, 1997, pp. 88-93.
  • Kim, Y., et al., “Fast GPU Implementation for the Solution of Tridiagonal Matrix Systems,” Journal of Korean Institute of Information Scientists and Engineers, vol. 32, No. 12, pp. 692-704, Dec. 2005.
  • Kramberger, I., “DSP acceleration using a reconfigurable FPGA,” ISIE '99. Proceedings of the IEEE International Symposium on Industrial Electronics (Cat. No. 99TH8465), vol. 3 , Jul. 12-16, 1999, pp. 1522-1525.
  • Langhammer, M., “How to implement DSP in programmable logic ” Elettronica Oggi, No. 266 , Dec. 1998, pp. 113-115.
  • Langhammer, M., “Implementing a DSP in Programmable Logic ” Online EE Times, May 1998, http:--www.eetimes.com-editorial-1998-coverstory9805.html.
  • Lazaravich, B.V., “Function block oriented field programmable logic arrays,” Motorola, Inc. Technical Developments, vol. 18, Mar. 1993, pp. 10-11.
  • Lund, D., et al., “A new development system for reconfigurable digital signal processing,” First International Conference on 3G Mobile Communication Technologies (Conf. Publ. No. 471), Mar. 27-29, 2000, pp. 306-310.
  • Miller, N.L., et al., “Reconfigurable integrated circuit for high performance computer arithmetic,” Proceedings of the 1998 IEE Colloquium on Evolvable Hardware Systems (Digest) No. 233, 1998, pp. 2-1-2-4.
  • Mintzer, L., “Xilinx FPGA as an FFT processor,” Electronic Engineering, vol. 69, No. 845, May 1997, pp. 81, 82, 84.
  • Faura et al., “A Novel Mixed Signal Programmable Device With On-Chip Microprocessor,” Custom Integrated Circuits Conference, 1997. Proceedings of the IEEE 1997 Santa Clara, CA, USA, May 5, 1997, pp. 103-106.
  • Nakasato, N., et al., “Acceleration of Hydrosynamical Simulations using a FPGA board” The Institute of Electronics Information and Communication Technical Report CPSY2005-47, vol. 105, No. 515, Jan. 17, 2006.
  • Nozal, L., et al., “A new vision system: programmable logic devices and digital signal processor architecture (PLD+DSP),” Proceedings IECON '91. 1991 International Conference on Industrial Electronics, Control and Instrumentation (Cat. No. 91CH2976-9) vol. 3, Oct. 28-Nov. 1, 1991, pp. 2014-2018.
  • Osana, Y., et al., “Hardware-resource Utilization Analysis on an FPGA-Based Biochemical Simulator ReCSiP”, The Institute of Electronics Information and Communication Technical Report CPSY2005-63, vol. 105, No. 516, Jan. 18, 2006.
  • Papenfuss, J.R, et al., “Implementation of a real-time, frequency selective, RF channel simulator using a hybrid DSP-FPGA architecture,” RAWCON 2000: 2000 IEEE Radio and Wireless Conference (Cat. No. 00EX404), Sep. 10-13, 2000, pp. 135-138.
  • Parhami, B., “Configurable arithmetic arrays with data-driven control,” 34th Asilomar Conference on Signals, Systems and Computers, vol. 1, 2000, pp. 89-93.
  • “The QuickDSP Design Guide”, Quicklogic, Aug. 2001, revision B.
  • “QuickDSP™ Family Data Sheet”, Quicklogic, Aug. 7, 2001, revision B.
  • Rangasayee, K., “Complex PLDs let you produce efficient arithmetic designs,” EDN (European Edition), vol. 41, No. 13, Jun. 20, 1996, pp. 109, 110, 112, 114, 116.
  • Rosado, A., et al., “A high-speed multiplier coprocessor unit based on FPGA,” Journal of Electrical Engineering, vol. 48, No. 11-12, 1997, pp. 298-302.
  • Santillan-Q., G.F., et al., “Real-time integer convolution implemented using systolic arrays and a digit-serial architecture in complex programmable logic devices,” Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No. 99EX303), Jul. 26-28, 1999, pp. 147-150.
  • Texas Instruments Inc., “TMS320C54x DSP Reference Set, vol. 1: CPU and Peripherals”, Literature No. SPRU131F, Apr. 1999, pp. 2-1 through 2-16 and 4-1 through 4-29.
  • Tisserand, A., et al., “An on-line arithmetic based FPGA for low power custom computing,” Field Programmable Logic and Applications, 9th International Workshop, FPL'99, Proceedings (Lecture Notes in Computer Science vol. 1673) Lysaght, P., et al., eds., Aug. 30-Sep. 1, 1999, pp. 264-273.
  • Tralka, C., “ Symbiosis of DSP and PLD,” Elektronik, vol. 49, No. 14 , Jul. 11, 2000, pp. 84-96.
  • Underwood, K. “FPGAs vs. CPUs: Trends in Peak Floating-Point Performance,” Proceedings of the 2004 ACM-SIGDA 12th International Symposium on Field Programmable Gate Arrays, pp. 171-180, Feb. 22-24, 2004.
  • Valls, J., et al., “A Study About FPGA-Based Digital Filters,” Signal Processing Systems, 1998 SIPS 98, 1998 IEEE Workshop, Oct. 10, 1998, pp. 192-201.
  • “Virtex-II 1.5V Field-Programmable Gate Arrays”, Xilinx, Jan. 25, 2001, module 2 of 4.
  • “Virtex-II 1.5V Field-Programmable Gate Arrays”, Xilinx, Apr. 2, 2001, module 1 of 4.
  • “Virtex-II 1.5V Field-Programmable Gate Arrays”, Xilinx, Apr. 2, 2001, module 2 of 4.
  • Vladimirova, T. et al., “Floating-Point Mathematical Co-Processor for a Single-Chip On-Board Computer,” MAPLD'03 Conference, D5, Sep. 2003.
  • Wajih, E.-H.Y. et al., “Efficient Hardware Architecture of Recursive Karatsuba-Ofman Multiplier,” 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 6 pgs, Mar. 2008.
  • Walters, A.L., “A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on ,a FPGA Based Custom Computing Platform,” Allison L. Walters, Thesis Submitted to the Faculty of Virginia Polytechnic Institute and State University, Jan. 30, 1998.
  • Weisstein, E.W., “Karatsuba Multiplication,” MathWorld—A Wolfram Web Resource (Dec. 9, 2007), accessed Dec. 11, 2007 at http:--mathworld.wolfram.com-KaratsubaMultiplication.html.
  • Wenzel, L., “Field programmable gate arrays (FPGAs) to replace digital signal processor integrated circuits,” Elektronik , vol. 49, No. 5, Mar. 7, 2000, pp. 78-86.
  • “Xilinx Unveils New FPGA Architecture to Enable High-Performance, 10 Million System Gate Designs”, Xilinx, Jun. 22, 2000.
  • “Xilinx Announces DSP Algorithms, Tools and Features for Virtex-II Architecture”, Xilinx, Nov. 21, 2000.
  • Xilinx Inc., “Virtex-II 1.5V Field-Programmable Gate Arrays”, Advance Product Specification, DS031-2 (v1.9), Nov. 29, 2001, Module 2 of 4, pp. 1-39.
  • Xilinx Inc., “Using Embedded Multipliers”, Virtex-II Platform FPGA Handbook, UG002 (v1.3), Dec. 3, 2001, pp. 251-257.
  • Xilinx, Inc., “A 1D Systolic FIR,” copyright 1994-2002, downloaded from http:--www.iro.umontreal.ca-˜aboulham-F6221-Xilinx%20A%201D%20systolic%20FIR.htm.
  • Xilinx, Inc., “The Future of FPGA's,” White Paper, available Nov. 14, 2005 for download from http:--www.xilinx.com-prs—rls,5yrwhite.htm.
  • Xilinx Inc., “XtremeDSP Design Considerations User Guide,” v 1.2, Feb. 4, 2005.
  • Xilinx Inc., “Complex Multiplier v2.0”, DS291 Product Specification/Datasheet, Nov. 2004.
  • Zhou, G. et al., “Efficient and High-Throughput Implementations of AES-GCM on FPGAs,” International Conference on Field-Programmable Technology, 8 pgs., Dec. 2007.
  • Martinson, L. et al., “Digital Matched Filtering with Pipelined Floating Point Fast Fourier Transforms (FFT's),” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-23, No. 2, pp. 222-234, Apr. 1975.
  • Fujioka, Y., et al., “240MOPS Reconfigurable Parallel VLSI Processor for Robot Control,” Proceedings of the 1992 International Conference on Industrial Electronics, Control, Instrumentation, and Automation: Signal Processing and Systems Control; Intelligent Sensors and Instrumentation, vol. 3, pp. 1385-1390, Nov. 9-13, 1992 All references have been considered.
Patent History
Patent number: 9098332
Type: Grant
Filed: Jun 1, 2012
Date of Patent: Aug 4, 2015
Assignee: Altera Corporation (San Jose, CA)
Inventor: Martin Langhammer (Salisbury)
Primary Examiner: Chuong D Ngo
Application Number: 13/486,255
Classifications
Current U.S. Class: Repeated Addition (708/627)
International Classification: G06F 7/48 (20060101); G06F 7/49 (20060101); G06F 9/30 (20060101); G06F 7/499 (20060101); G06F 7/485 (20060101);