Abstract: Methods, apparatus, systems and articles of manufacture to perform dot product calculations using sparse vectors are disclosed. An example apparatus includes means for generating a mask vector based on a first logic operation on a difference vector and an inverse of a control vector, the control vector based on a first bitmap of a first sparse vector and a second bitmap of a second sparse vector; means for generating a first product of a third value from the first sparse vector and a fourth value from the second sparse vector, the third value based on (i) the mask vector and (ii) a second sparsity map based on the first sparse vector, the fourth value corresponding to (i) the mask vector and (ii) a second sparsity map corresponding to the second sparse vector; and means for adding the first product to a second product of a previous iteration.

Abstract: The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

Abstract: In an embodiment, a method includes configuring a specialized circuit for floating point computations using numbers represented by a hybrid format, wherein the hybrid format includes a first format and a second format. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a numeric value in the first format during a forward pass for training a deep learning network. In the embodiment, the method includes operating the further configured specialized circuit to store an approximation of a second numeric value in the second format during a backward pass for training the deep learning network.

Abstract: Systems and methods for a random number generator including a systolic array to provide a random number output. In one approach, the systolic array can be arranged in two or greater dimensions, and each cell of the array comprises a ring oscillator. Data is read from a random access memory to provide the inputs to the systolic array. A linear feedback shift register receives the random number output as a feedback signal used to address the memory to read data to provide as the inputs to the systolic array.

Abstract: A Unit Element (UE) has a positive UE and a negative UE, each having a digital X input and a digital W input with a sign bit, the sign bit is exclusive ORed with a chop clock to generate a chopped sign bit. The positive UE is enabled when the chopped sign bit is positive and the negative UE is enabled when the chopped sign bit is negative. Each positive and negative UE comprises groups of NAND gates generating an output and complementary output which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The NAND gate outputs and complementary outputs are coupled through binary weighted charge transfer capacitors the positive charge transfer line and negative charge transfer line.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a circuit configured to add multiple inputs. The circuit includes a first adder section that receives a first input and a second input and adds the inputs to generate a first sum. The circuit also includes a second adder section that receives the first and second inputs and adds the inputs to generate a second sum. An input processor of the circuit receives the first and second inputs, determines whether a relationship between the first and second inputs satisfies a set of conditions, and selects a high-power mode of the adder circuit or a low-power mode of the adder circuit using the determined relationship between the first and second inputs. The high-power mode is selected and the first and second inputs are routed to the second adder section when the relationship satisfies the set of conditions.

Abstract: An interaction prediction system for accurately predicting the occurrence of interactions, entities associated with the interactions, and/or resources involved with the interactions. The interaction predictions can be used for a number of different purposes, such as improving security of systems, predicting future interactions or the likelihood thereof, or the like. The interaction prediction system described herein more accurately predict the interactions using modeling and monitoring that increases the processing speeds by reducing the data needed to make the predictions, reduces the memory requirements to make the predictions, and increases the capacity of the processing systems when compared to traditional systems.

Abstract: The disclosure relates to systems, methods and devices to provide race-condition true random number generator (TRNG) for soft intellectual property (IP) in field-programmable gate arrays (FPGAs). In an exemplary embodiment, a pair of long adder chains are raced against one another to complete a full cycle. Due to variances in the silicon, different chains will win each race at different times and thereby produce entropy. A calibration circuit can be used to set up the adder chains in an appropriate initial state to maximize the entropy produced. This structure has been found to be robust to layout changes, and the use of two such adder-chain-pairs reduces interference from other structures. Among others, the soft IP makes adding a robust TRNG to an FPGA much easier without concerns for how the structures are laid out or what other IP is nearby in the layout. The disclosed embodiments reduces the effort to add a TRNG to an FPGA design and improves the robustness of the TRNG making the design FIPS certifiable.

Abstract: Systems and methods for producing a linear-phase digital FIR filter from two sub-filters for an audio signal. In one method, the sub-filters are provided as sub-sets having numbers of coefficients, a lower cutoff frequency of the particular sub-filter being greater than the sampling frequency of the audio signal divided by the number. The sub-sets are linearly convoluted with one another so as to form a total set having a number of coefficients greater than the numbers, and the total set is symmetrically reduced to a number less than the number, so as to form a reduced total set of the filter. A linear-phase digital FIR filter for an audio signal is created by the method.

Abstract: A microprocessor system comprises a matrix computational unit and a control unit. The matrix computational unit includes a plurality of processing elements. The control unit is configured to provide a matrix processor instruction to the matrix computational unit. The matrix processor instruction specifies a floating-point operand formatted using a first floating-point representation format. The matrix computational unit accumulates an intermediate result value calculated using the floating-point operand. The intermediate result value is in a second floating-point representation format.

Abstract: Real time cognitive reasoning using a circuit with varying confidence level alerts including receiving a first set of data results and a second set of data results; transferring a first unit of charge from a first charge capacitor on the A-B circuit to a collection capacitor on the A-B circuit for each of the first set of data results that indicates a positive data point; transferring a second unit of charge from a second charge capacitor to the collection capacitor for each of the second set of data results that indicates a positive data point; and triggering a first sense amp on the A-B circuit if the charge on the collection capacitor exceeds a first charge threshold, indicating that the positive data points in the first set of data results is greater than the positive data points in the second set of data results to a first statistical significance with a first confidence level.

Abstract: A processing apparatus having a programmable circuit including a plurality of ALUs, comprises a holding unit which holds configuration information for switching the programmable circuit from a first circuit setting to a second circuit setting, and timing information; and an updating unit which updates each ALU so as to switch the programmable circuit from the first circuit setting to the second circuit setting, wherein in switching from the first circuit setting to the second circuit setting after the programmable circuit has executed the first data processing, the updating unit, using the timing information, updates the first ALU at a timing at which last data of the first data processing is output from the first ALU, and updates the second ALU at a timing at which the last data is output from the second ALU.

Abstract: A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m?r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m?r?1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m?r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

Abstract: Approximation circuitry utilizes bitwise operations on operands to provide approximate results of operations on the operands. A significant digit detector utilizes bitwise operations on the received operands to identify or detect approximate most significant bits in the operands, and then utilizes these identified most significant bits to generate approximate values for each of the operands. Intermediate registers receive and store the approximate values from the significant digit detector. A combinatorial network, such as a lookup table (LUT), thereafter utilizes the approximate values stored in the intermediate registers to generate an approximate result. The approximate result has a value that is an approximate value of a given operation, such as multiplication or division, on the operands provided to the significant digit detector.

Abstract: Real time cognitive reasoning using a circuit with varying confidence level alerts including receiving a first set of data results and a second set of data results; transferring a first unit of charge from a first charge capacitor on the A-B circuit to a collection capacitor on the A-B circuit for each of the first set of data results that indicates a positive data point; transferring a second unit of charge from a second charge capacitor to the collection capacitor for each of the second set of data results that indicates a positive data point; and triggering a first sense amp on the A-B circuit if the charge on the collection capacitor exceeds a first charge threshold, indicating that the positive data points in the first set of data results is greater than the positive data points in the second set of data results to a first statistical significance with a first confidence level.

Abstract: Enhanced techniques and circuitry are presented herein for artificial neural networks. These artificial neural networks are formed from artificial synapses, which in the implementations herein comprise a memory arrays having non-volatile memory elements. In one implementation, an apparatus comprises a plurality of non-volatile memory arrays configured to store weight values for an artificial neural network. Each of the plurality of non-volatile memory arrays can be configured to receive data from a unified buffer shared among the plurality of non-volatile memory arrays, operate on the data, and shift at least portions of the data to another of the plurality of non-volatile memory arrays.

Abstract: Provided is an interpolation technique in which command values chronologically input can be interpolated without increasing a jerk and with less follow-up delay with respect to a command. A control unit (10) of a servo driver (20) has a function of sequentially generating, on the basis of four command values from x(k?2) to x(k+1), a kth interpolation function for calculating command values in a kth (?3) time interval and a function of generating, as the kth interpolation function, a fifth-order equation with respect to time in which function values at a start time and an end time of the kth time interval match x(k) and x(k+1), respectively, and in which a second derivative value at a start time of the kth time interval matches a second derivative value at an end time of a (k?1)th time interval corresponding to a (k?1)th interpolation function.

Abstract: A processing element and an operating method thereof in a neural network are disclosed. The processing element may include a first multiplexer selecting one of a first value stored in a first memory and a second value stored in a second memory, a second multiplexer selecting one of a first data input signal and an output value of the first multiplexer, a third multiplexer selecting one of the output value of the first multiplexer and a second data input signal, a multiplier multiplying an output value of the second multiplexer by an output value of the third multiplexer, a fourth multiplexer for selecting one of the output value of the second multiplexer and an output value of the multiplier, and a third memory storing an output value of the fourth multiplexer.

Abstract: Provided is a fast Fourier transform device for analyzing specific frequency components of an input signal. The fast Fourier transform device includes an address generator that generates an address, based on a first frequency index corresponding to a first frequency, an FFT coefficient table that outputs a first Fourier transform coefficient corresponding to the generated address among Fourier transform coefficients of the first frequency index, and an operator that calculates a frequency characteristic of an input signal associated with the first frequency, based on the input signal and the first Fourier transform coefficient.