Transimpedance amplifier with variable inductance input reducing peak variation over gain

- INPHI CORPORATION

A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking. TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode.

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Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of and claims priority to U.S. patent application Ser. No. 15/226,814, filed on Aug. 2, 2016, which is incorporated by reference herein.

BACKGROUND

Embodiments of the present invention relate to communication systems and integrated circuit (IC) devices. More particularly, embodiments provide a transimpedance amplifier device and method therefor.

Over the last few decades, the use of communication networks has exploded. In the early days Internet, popular applications were limited to emails, bulletin board, and mostly informational and text-based web page surfing, and the amount of data transferred was usually relatively small. Today, Internet and mobile applications demand a huge amount of bandwidth for transferring photo, video, music, and other multimedia files. For example, a social network like FACEBOOK processes more than 500 TB of data daily. With such high demands on data and data transfer, existing data communication systems need to be improved to address these needs.

CMOS technology is commonly used to design communication systems implementing Optical Fiber Links. As CMOS technology is scaled down to make circuits and systems run at higher speed and occupy smaller chip (die) area, the operating supply voltage is reduced for lower power. Conventional FET transistors in deep-submicron CMOS processes have very low breakdown voltage as a result the operating supply voltage is maintained around 1 Volt. The Photo-detectors (PD) used in 28G and 10G Optical Receivers require a bias voltage of more than 2 Volts across the anode and cathode nodes of the PD for better photo-current responsivity. These limitations provide significant challenges to the continued improvement of communication systems scaling and performance.

There have been many types of communication systems and methods. Unfortunately, they have been inadequate for various applications. Therefore, improved communication systems and methods are desired.

SUMMARY

A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowered inductance afforded by the control voltage applied to the FET reduces voltage peaking. TIAs in accordance with embodiments may be particularly suited for operation over a wide dynamic range to amplify incoming electrical signals received from a photodiode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a fiber optic communication system in an environment that includes trans-impedance amplifiers.

FIG. 2 is a schematic of a full differential trans-impedance amplifier with resistive gain control.

FIG. 3 illustrates a circuit including a trans-impedance amplifier according to an embodiment.

FIG. 4 is a simplified view of a resistor-inductor-capacitor (RLC) circuit.

FIG. 5 plots voltage versus frequency for a trans-impedance amplifier operating under different gain conditions, with and without input inductance control according to embodiments.

DETAILED DESCRIPTION

Embodiments are directed to apparatuses and methods of providing trans-impedance amplifiers. More specifically, particular embodiments provide transimpedance amplifiers with variable inductance input to reduce peaking behavior over different gain conditions. There are other embodiments as well.

The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification, (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

Furthermore, any element in a claim that does not explicitly state “means for” performing a specified function, or “step for” performing a specific function, is not to be interpreted as a “means” or “step” clause as specified in 35 U.S.C. Section 112, Paragraph 6. In particular, the use of “step of” or “act of” in the Claims herein is not intended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

Please note, if used, the labels left, right, front, back, top, bottom, forward, reverse, clockwise and counter clockwise have been used for convenience purposes only and are not intended to imply any particular fixed direction. Instead, they are used to reflect relative locations and/or directions between various portions of an object.

The trans-impedance amplifier or TIA is a key component in high-speed communication (e.g., fiber optic) networks and systems. To accommodate the continual demand for more data bandwidth over such networks and systems, multi-level signaling (e.g., pulse-amplitude modulation or PAM) has been deployed. The use of multi-level signaling in turn demands higher performance from the TIAs in the system. Specifically, the TIA needs to accurately reproduce the multiple levels of the signal with low distortion (e.g., high linearity), low noise, and wide bandwidth, while leveraging power-efficient and cost-effective semiconductor manufacturing processes and materials (e.g., Si CMOS).

FIG. 1 illustrates a fiber optic communication system 100 in an environment that includes trans-impedance amplifiers. As an option, one or more instances of fiber optic communication system 100 or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein. Also, fiber optic communication system 100 or any aspect thereof may be implemented in any desired environment.

As shown in FIG. 1, fiber optic communication system 100 illustrates the key components of a fiber optic communications system including one or more TIAs. For example, fiber optic communication system 100 can represent a 100 GbE-LR4 system. Fiber optic communication system 100 can also be representative of similar systems in a variety of environments and applications, such as non-optical serial data communication links and memory data interfaces. Specifically, fiber optic communication system 100 comprises a serializer 102, a laser and modulator 103, a 4:1 optical mux 104, a fiber optic link 105, a 1:4 optical demux 106, a photodiode and TIA array 107, and a deserializer 109. Photodiode and TIA array 107 further comprises a plurality of TIAs 108 (e.g., TIA 1081, TIA 1082, TIA 1083, and TIA 1084) each with an associated photodiode as illustrated in FIG. 1. In other systems, any number of TIAs can be used. Fiber optic communication system 100 illustrates that parallel (e.g., N wide) input data 110 is received by serializer 102 and converted to a serial data stream having four channels (e.g., for LR4). The serial data is then received by laser and modulator 103 to be converted to modulated (e.g., PAM-xx, QPSK, etc.) optical signals. The four channels are multiplexed into one channel by 4:1 optical mux 104 and delivered to optical link 105. The optical signal is received by 1:4 optical demux 106 and demultiplexed to four channels and delivered to photodiode and TIA array 107. The plurality of TIAs 108 convert the current signals (e.g., through the photodiodes) to voltage signals to be received by deserializer 109. Deserializer 109 then converts the four channels of serial data to parallel (e.g., N wide) received data 111.

The plurality of TIAs 108 are a critical component of fiber optic communication system 100 in that they enable an accurate (e.g., low BER) recovery of the information contained within input data 110. The plurality of TIAs 108 accomplishes this, in part, by converting the optical representation of input data 110 into the voltage representation of input data 110. As more sophisticated signal modulation and longer links are deployed, techniques are needed meet these requirements by implementing a low cost TIA that exhibits high linearity, low noise, low power, and wide bandwidth.

FIG. 2 is a schematic 200 of a full differential trans-impedance amplifier with resistive gain control. As an option, one or more instances of schematic 200 or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein. Also, schematic 200 or any aspect thereof may be implemented in any desired environment. While FIG. 2 shows a differential TIA implementation, this is not required. According to other embodiments the TIA could be single-ended or pseudo-differential (two single-ended TIAs followed by a differential amplifier).

As shown in FIG. 2, schematic 200 comprises a photodiode 201, a first inverting amplifier 2021, a second inverting amplifier 2022, a first buffer 2031, a second buffer 2032, an analog DC control loop 204, and an analog AC control loop 205. A first feedback resistor RF 2061 is connected between the input and output of first inverting amplifier 2021, and a second feedback resistor RF 2062 is connected between the input and output of second inverting amplifier 2022. For illustrative purposes, the value of first feedback resistor RF 2061 and the value of second feedback resistor RF 2062 can be represented by “R1” and “R2”, respectively, and the gain of first inverting amplifier 2021 and the gain of second inverting amplifier 2022 can be represented by “G1” and “G2”, respectively. In some embodiments, schematic 200 can represent a CMOS implementation of a SiGe (e.g., bipolar) design. In such implementations, the use of CMOS inverters as first inverting amplifier 2021 and second inverting amplifier 2022 can simplify implementation, provide low noise, and allow operation at low voltages (e.g., less than 1V). As shown in schematic 200, a first current IPD 2201 flowing from the anode of photodiode 201 is steered either to a current ITn 221 toward first inverting amplifier 2021, or to a current IRn 222 toward first buffer 2031 through a transistor TCGn 211 (e.g., MOS device), wherein an analog tuning voltage VTUNEn 212 at the gate of transistor TGCn 211 can adjust the amount of current IPD 2201 that is steered to current ITn 1221 and to current IRn 222. Similarly, a second current IPD 2202 (e.g., equal to first current IPD 2201) flowing into the cathode of photodiode 201 includes a current ITp 223 from second inverting amplifier 2022, and a current IRp 224 from second buffer 2032 through a transistor TGCp 213 (e.g., MOS device), wherein a second analog tuning voltage VTUNEp 214 at the gate of transistor TGCp 213 can tune the amount of current IRp 224 (e.g., relative to current ITp 223) included in current IPS 2202. The amount of tuning or steering provided, in part, by voltage VTUNEn 212 will be determined, in part, by the impedance looking into first inverting amplifier 2021 (e.g., equal to R1/(G1+1)) and the impedance looking into the drain of transistor TGCn 211, which is determined, in part, by the impedance of transistor TGCn 211 and the output impedance of first buffer 2031. Similarly, the amount of tuning or steering provided, in part, by voltage VTUNEp 214 will be determined, in part, by the impedance looking into second inverting amplifier 2022 (e.g., equal to R2/(G2+1)) and the impedance looking into the drain of transistor TGCp 213, which is determined, in part, by the impedance of transistor TGCp 213 and the output impedance of second buffer 2032. The analog tuning voltages can derive from a digital-to-analog convertor (DAC) of any type to produce an analog voltage.

In some embodiments, each of the plurality of buffers 203 is configured to be a unity gain buffer with very low output impedance. In certain embodiments, voltage VTUNEn 212 and voltage VTUNEp 214 are controlled by analog AC control loop 205 to produce a fixed peak-to-peak output voltage determined by the difference between a negative output voltage VOUTn 215 and a positive output voltage VOUTp 216, respectively. In some embodiments, analog AC control loop 205 can include an analog power rectifier and comparator, and an analog control loop. In certain embodiments, the bias or DC voltage at the input of first inverting amplifier 202.sub.1 is controlled, in part, by analog DC control loop 204 through a transistor TPDCn 217 and first feedback resistor RF 2061, and the bias or DC voltage at the input of second inverting amplifier 2022 is controlled, in part, by analog DC control loop 204 through a transistor TDCp 218 and second feedback resistor RF 2062. Such control of the DC voltages at the input of first inverting amplifier 2021 and second inverting amplifier 2022 can serve to prevent unwanted DC currents that can increase power dissipation and degrade total harmonic distortion or THD.

In some embodiments, the desired operation and performance of the implementation shown in schematic 200 can require that both first buffer 2031 and second buffer 2032 have a very high bandwidth and very low output impedance (e.g., a few ohms at frequencies greater than 1 GHz). Such performance cannot be achieved using a cost-effective semiconductor manufacturing process (e.g., 28 nm CMOS) with either widely used device structures (e.g., planar FET) or specialized device structures (e.g., FinFET). This is due, in part, to differences in device transconductance or gm among various semiconductor manufacturing processes (e.g., CMOS FET gm is less than SiGe bipolar gm). For example, transistor TGCn 211 and transistor TGCp 213 that are tuned by analog AC control loop 205 would need to range from a very small impedance (e.g., 2-3Ω) to a very large impedance (e.g., over 100 k Ω). If implemented in CMOS, the size of transistor TGCn 211 and transistor TGCp 213 required to meet these metrics would result in parasitic capacitances that would significantly limit the TIA bandwidth (e.g., when gain control is not needed). Further, high linearity is difficult to achieve using transistor TGCn 211 and transistor TGCp 213 in a series configuration as the characteristics of the devices will change as various device voltages (e.g., VGS and VBS) change with first current IPD 2201 and second current IPD 2202, respectively. Further, in some embodiments, distortion can increase as more AC current is shunted away from first inverting amplifier 2021 and second inverting amplifier 2022, and into first buffer 2031 and second buffer 2032, respectively. Thus, there is a need for techniques implementing a TIA that exhibits high linearity, low noise, low power, and wide bandwidth.

FIG. 3 is a simplified block diagram of a circuit 300 comprising a transimpedance amplifier device 302 according to an embodiment of the present invention. As shown, circuit 300 includes a transimpedance amplifier TIA 303 coupled to a photodiode PD 304 across a chip boundary 306.

Several inductances are represented in the connection between the PD and the TIA. The inductance Lbw 308 represents the inductance of the bond wire (bw) between the PD and the chip including the TIA. The inductance L1310 represents at least the inherent inductance offered by electrical conductors present on the chip leading to the TIA.

It is noted that the PD is expected to operate under a variety of conditions. That is, the PD is designed to produce a corresponding output current in response to incoming optical signals varying over a wide range of intensities (weak to strong).

It is the responsibility of the TIA to amplify this incoming electrical signal. To accommodate the variance in input current, the TIA is configured to operate under different gain conditions (represented by the arrow 312). In some embodiments this dynamic range of TIA operation may be about 20 dB, may be about 18 dB, may be about 15 dB, may be about 10 dB, or may be about 5 dB.

However, one result of operating the TIA under such a wide spectrum of possible gain conditions, is that the optimal input impedance of the TIA also changes. This, in combination with capacitance effects, gives rise to unwanted distortion in output of the TIA. In particular, output voltage of the TIA may exhibit peaking under low gain conditions.

Accordingly, in order to avoid this distortion, embodiments provide the TIA structure with a variable inductance component 320 at the input node 322. That variable inductance component functions to reduce variation in peak amplitude over different gain conditions.

In the particular embodiment of FIG. 3, the variable inductance component comprises an inductor L2 324 at the TIA input. The inductor L2 has a first node in communication with the photodiode and a drain 326 of a Field Effect Transistor (FET) 328. The inductor L2 has a second node in communication with the FET source 330.

In certain embodiments the FET 328 may be of a SiGe bi-CMOS design. However this is not required, and the FET could be of other designs, including but not limited to JFET or FinFet.

A control voltage VL 332 from a voltage source 334 is applied to the FET gate 335 via resistor 336. This control voltage effectively controls the input inductance to the TIA by adding a variable impedance across the inductor L2.

Under high gain conditions, the optimal input impedance of the TIA is high. Thus an elevated effective input inductance (e.g., the full Lbw+L1+L2) is needed in order to achieve bandwidth. The Fen control bias is small or zero.

Under low gain conditions, the optimal input impedance of the TIA is lower. A high Fen control bias VL, VL>>Vin+Vth applied to the Fet1 shorts out the inductor L2. The effective inductance from the photodiode (PD) to the TIA is then reduced from Lbw+L1+L2 to Lbw+L1.

As mentioned above, unwanted voltage peaking behavior may be observed for a TIA that is operated under lower gain conditions. According to embodiments, this unwanted peaking behavior may be reduced or eliminated by applying a control voltage to the FET.

Specifically, at intermediate control voltages VL the inductance L2 is not fully shorted. It then becomes a resistor-inductor-capacitor (RLC) network as shown in FIG. 4, with Rds representing the channel resistance of the control FET Fet1, as controlled by the control voltage VL, and Cds representing:

[ Cds + CgdCgs Cgd + Cgs ] .
Here, the second term represents parasitic capacitance effects arising from the FET gate (g). Reduced peaking variation is achieved by actively controlling the effective inductance at the input of the TIA.

FIG. 5 plots normalized voltage (dB) versus frequency (GHz) for the circuit of FIG. 3, with the trans-impedance amplifier operating under six (6) different voltage gain control (Vgc) conditions: Vgc=0, 0.5, 1.0, 1.5, 2.0, and 2.5.

In FIG. 5 these six (6) gain conditions break out into the following groups:

Low gain conditions 502: Vgc=0, 0.5, and 1.0

High gain conditions 504: Vgc=1.5, 2.0, and 2.5

A total of twelve (12) gain curves are shown in FIG. 5. The dashed curves of FIG. 5 represent the TIA operating without inductance control at the input. The solid curves of FIG. 5 represent the TIA operating with inductance control at the input according to embodiments.

FIG. 5 shows that absent implementation of variable inductance input, significant peaking is observed at low gain conditions (dashed lines). This peaking behavior is significantly reduced by application of the variable input inductance according to embodiments. In particular, at low gain, a ˜3 dB reduction in peaking (ΔZ) is observed (solid lines).

FIG. 5 shows that this reduction in peaking effect is less pronounced in the high gain operational regime of the TIA, as is desired.

Returning to FIG. 3, that particular embodiment shows the variable inductance component at the TIA input as comprising a field-effect transistor (Fet). That Fet may comprise a MOSFET—for example a PMOSFET or an NMOSFET. The Fet could alternatively comprise a JFET or other transistor architecture.

Other embodiments, however, may feature different structures in place of the Fet architecture. One example could be a micro-electrical mechanical system (MEMS) comprising a switch including a moveable element (e.g., a deformable membrane).

While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.

Claims

1. A method for reducing peaking at an amplifier output under low gain conditions between the amplifier output and an output signal of a photodiode, the method comprising:

providing a transimpedance amplifier (TIA) having an input node; and
connecting the input node of the TIA to a variable inductance component having a first terminal in electrical communication with the output signal of the photodiode;
connecting a second terminal of the variable inductance component to be in electrical communication with the input node of the TIA; and
connecting a third terminal of the variable inductance component to be in electrical communication with a variable control voltage to change an effective inductance at the input node of the TIA, the variable inductance component comprising,
an inductor having a first node in electrical communication with the output signal of the photodiode, a second node in electrical communication with the input node of the TIA, and
a switching device having a first contact in communication with the first node, a second contact in electrical communication with the second node, and a third contact being in electrical communication with the variable control voltage.

2. The method of claim 1 wherein:

the switching device comprises a SiGe bi-CMOS field-effect transistor (bi-CMOS FET);
the first contact comprises a drain of the bi-CMOS FET;
the second contact comprises a source of the bi-CMOS FET; and wherein
the third contact comprises a gate of the bi-CMOS FET in communication with a variable voltage source through a resistor.

3. The method of claim 1 wherein:

the switching device comprises a field-effect transistor (FET);
the first contact comprises a drain of the FET;
the second contact comprises a source of the FET; and wherein
the third contact comprises a gate of the FET in communication with a variable voltage source.

4. The method of claim 3 wherein the FET comprises a MOSFET.

5. The method of claim 4 wherein the MOSFET comprises a p-channel MOSFET.

6. The method of claim 4 wherein the MOSFET comprises an n-channel MOSFET.

7. The method of claim 4 wherein the FET comprises a JFET.

8. The method of claim 1 wherein the switching device comprises a micro-electrical mechanical system having a moveable element.

9. The method of claim 1 wherein the TIA is configured to operate with a dynamic range of about 18 dB to about 20 dB.

10. The method of claim 1 wherein the variable control voltage to change an effective inductance at the input node of the TIA is configured to reduce peaking at an output node of the TIA under low gain conditions.

11. A fiber optic communications system having a photodiode with an output signal, the fiber optic communications system comprising:

a transimpedance amplifier (TIA) having an input node; and
a variable inductance component having a first terminal in electrical communication with the output signal of the photodiode, a second terminal electrically connected to the input node of the TIA, and a third terminal electrically connected to a variable control voltage to change an effective inductance at the input node of the TIA, the variable inductance component comprising,
an inductor having a first node in electrical communication with the photodiode,
a second node in communication with the input node of the TIA and
a switching device having a first contact in communication with the first node, a second contact in electrical communication with the second node, and a third contact being connected to the variable control voltage.

12. The system of claim 11 wherein:

the switching device comprises a SiGe bi-CMOS field-effect transistor (bi-CMOS FET);
the first contact comprises a drain of the bi-CMOS FET;
the second contact comprises a source of the bi-CMOS FET; and wherein
the third contact comprises a gate of the bi-CMOS FET in communication with a variable voltage source through a resistor.

13. The system of claim 11 wherein:

the switching device comprises a field-effect transistor (FET);
the first contact comprises a drain of the FET;
the second contact comprises a source of the FET; and wherein the third contact comprises a gate of the FET in communication with a variable voltage source.

14. The system of claim 13 wherein the FET comprises a MOSFET.

15. The system of claim 14 wherein the MOSFET comprises a p-channel MOSFET.

16. The system of claim 14 wherein the MOSFET comprises an n-channel MOSFET.

17. The system of claim 14 wherein the FET comprises JFET.

18. The system of claim 11 wherein the switching device comprises a micro-electrical mechanical system having a moveable element.

19. The system of claim 11 wherein the TIA is configured to operate with a dynamic range of about 18 dB to about 20 dB.

20. The system of claim 11 wherein the TIA is configured to operate with a dynamic range of about 15 dB to about 18 dB.

Referenced Cited

U.S. Patent Documents

8754711 June 17, 2014 Welch
8766728 July 1, 2014 Ito et al.
9590801 March 7, 2017 Shringarpure
20130135054 May 30, 2013 Ito
20150086221 March 26, 2015 Shringarpure
20150155946 June 4, 2015 Broekaert et al.
20160118947 April 28, 2016 Shringarpure et al.
20160149548 May 26, 2016 Gorecki et al.

Patent History

Patent number: 9899969
Type: Grant
Filed: Aug 22, 2017
Date of Patent: Feb 20, 2018
Assignee: INPHI CORPORATION (Santa Clara, CA)
Inventor: Tom Broekaert (Santa Clara, CA)
Primary Examiner: Shi K Li
Assistant Examiner: Mina Shalaby
Application Number: 15/683,444

Classifications

Current U.S. Class: Having Signal Feedback Means (330/260)
International Classification: H03F 3/08 (20060101); H03F 1/34 (20060101); H04B 10/25 (20130101); H04B 10/54 (20130101); H04Q 11/00 (20060101);