Having Signal Feedback Means Patents (Class 330/260)
  • Patent number: 10281940
    Abstract: A low dropout regulator provided includes: an impedance unit; a differential amplifier being electrically connected to the impedance unit; a current mirror unit being electrically connected to the differential amplifier; and an adaptive bias unit being electrically connected to the differential amplifier and the current mirror unit. The impedance unit is electrically connected to a negative feedback route of the differential amplifier to make a gain of the negative feedback route greater than a gain of a positive feedback route of the differential amplifier.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 7, 2019
    Assignee: PIXART IMAGING INC.
    Inventors: Tsung-Han Yang, Chia-So Chuang
  • Patent number: 10243516
    Abstract: A first circuit unit of an audio amplifier includes a first emitter follower connected to an pre stage input terminal, a second emitter follower connected to an pre stage input terminal, a main transistor connected to an output path of the first emitter follower and an output path of the second emitter follower, a first resistor and a second resistor, which are series-connected between the output path of the first emitter follower and a DC voltage source, and a zener diode connected to a series-connection point between the first resistor and the second resistor. A second circuit unit has a circuit configuration that is complementary to the first circuit unit. A path leading to a collector of each transistor configuring the first and second emitter followers in one of the circuit units is connected to the series-connection point in the other circuit unit.
    Type: Grant
    Filed: February 4, 2018
    Date of Patent: March 26, 2019
    Assignee: ONKYO CORPORATION
    Inventors: Tsuyoshi Kawaguchi, Norimasa Kitagawa, Takuya Oka
  • Patent number: 10181827
    Abstract: A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking. TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: January 15, 2019
    Assignee: INPHI CORPORATION
    Inventor: Tom Broekaert
  • Patent number: 10122337
    Abstract: A programmable gain amplifier includes an active load module, a first differential pair, a second differential pair and a power source module. The first and second differential pairs are electrically connected to the active load module. The power source module is electrically connected to the first current source end of the first differential pair and the second current source end of the second differential pair. The power source module supplies a first current to the first differential pair through the first current source end. The power source module supplies a second current to the second differential pair through the second current source end. The power source module adjusts the potential of the first current, the potential of the second current, or both.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: November 6, 2018
    Assignee: SILICON INTEGRATED SYSTEMS CORP.
    Inventors: Ssu-Che Yang, Wen-Chi Lin, Keng-Nan Chen
  • Patent number: 10122353
    Abstract: A differential signal offset adjustment circuit may include a first circuit for receiving a first one of a differential input signal and generating a first one of a differential output signal with positive offset based on a differential offset signal. The circuit may further include a second circuit for receiving a second one of a differential input signal and generating a second one of a differential output signal with a negative offset based on the differential offset signal.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: November 6, 2018
    Assignee: Finisar Corporation
    Inventors: Sagar Ray, Arash Izadi
  • Patent number: 10069480
    Abstract: An active filter device and a circuit arrangement comprising an active filter device are disclosed. In an embodiment the active filter device includes sensor terminals for applying a sensor signal depending on a sensed noise signal, an output terminal for providing a correction signal that is suitable for reducing the noise signal, a signal source adapted for generating a correction signal and a high-pass filter coupled between the sensor terminals and the signal source, wherein the correction signal is generated with a dependence on a high-pass filtered sensor signal.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: September 4, 2018
    Assignee: EPCOS AG
    Inventor: Andrew Tucker
  • Patent number: 10042373
    Abstract: An integrated circuit voltage regulator includes a transconductor first stage; and a negative impedance cancellation stage, where the negative impedance cancellation stage comprises cross-coupled transistors at outputs of said transconductor first stage, and resistors in the transconductor first stage and the negative impedance cancellation stage introduce zeros in a transfer function, compensating for parasitic poles. The resistors may compensate for parasitic capacitance inherent in transistors. Load transistors may be coupled to outputs of the transconductance first stage. The voltage regulator may be implemented in a Complementary Metal-Oxide-Semiconductor (CMOS) structure, which may be a system-on-chip integrated circuit. The voltage regulator may provide immunity to power supply noise. The negative impedance cancellation stage may include differential input transistors coupled to the cross-coupled transistors.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: August 7, 2018
    Assignee: Entropic Communications, LLC.
    Inventor: Raed Moughabghab
  • Patent number: 10004117
    Abstract: Embodiments of an amplifier for a constant-current light-emitting diode (LED) driver circuit and a constant-current LED driver integrated circuit (IC) device having the amplifier are described. In one embodiment, an amplifier includes a folded cascode input stage including chopping switch circuits configured to perform frequency chopping to reduce an input offset of the amplifier and a rail-to-rail output stage connected to the folded cascode input stage. The rail-to-rail output stage includes slew rate enhancement circuits.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: June 19, 2018
    Assignee: NXP B.V.
    Inventor: Ge Wang
  • Patent number: 9998301
    Abstract: An isolator system has an isolator that generates differential isolator signals and a receiver that generates digital data representative of signals received from the isolator. The system also may include an RC filter coupled between the isolator and the receiver. During operation, the filter may distribute transient signals across various circuit paths in the isolator, only some of which are coupled to the receiver inputs. Over time, the filter may attenuate transient contributions at the receiver inputs. In this manner, the filter may limit effects of these common mode transients.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: June 12, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Ruida Yun, Baoxing Chen
  • Patent number: 9960738
    Abstract: A tunable peaking amplifier circuit including: an input node, an output node, and a feedback node; a first input amplifier having an input connected to the input node and an output connected to the feedback node; a second input amplifier having an input connected to the input node; a coupling capacitor connected between an output of the second input amplifier and the feedback node; an amplifier having an input connected to the feedback node and an output connected to the output node; a feedback circuit including: a base feedback amplifier having an input connected to the output node and an output connected to the feedback node; and a tunable feedback amplifier having an input connected to the output node and an output connected to the feedback node; and a tuning circuit for varying a transconductance of the feedback circuit to adjust an operational frequency of the peaking amplifier circuit.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael Chen, Steven M. Clements, Mohak Chhabra, Steven E. Mikes, Hayden C. Cranford, Jr.
  • Patent number: 9960773
    Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 1, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Eashwar Thiagarajan, Harold M. Kutz, Hans Klein, Jaskarn Singh Johal, Jean-Paul Vanitegem, Kendall V. Castor-Perry, Mark Hastings, Amsby D. Richardson, Jr., Anasuya Pai Maroor, Ata Khan, Dennis R. Seguine, Carl Ferdinand Liepold, Onur Ozbek
  • Patent number: 9935616
    Abstract: The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (FEOL) device level. The programmable resistive element is formed in at least one back end of line (BEOL) wiring level, and the programmable resistive element is in a non-volatile resistive state that is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: April 3, 2018
    Assignee: NXP USA, Inc.
    Inventors: Michael A. Sadd, Anirban Roy
  • Patent number: 9923522
    Abstract: Bias current is supplied to a first differential pair and a second differential pair from a first transistor being a single current source. Bias current is supplied to a third differential pair and a fourth differential pair from a second transistor being a single current source. An input voltage is at a power supply potential, and an input voltage is at a ground potential. When the second differential pair and the third differential pair are turned OFF, the bias current supplied from the first transistor flows to an output stage via the first differential pair, and the bias current supplied from the second transistor flows to the output stage via the fourth differential pair. Therefore, when the second differential pair and the third differential pair are turned OFF, a circuit current is kept constant, and a fluctuation in a frequency characteristic can be restrained.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: March 20, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takayuki Nakai
  • Patent number: 9899969
    Abstract: A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking. TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: February 20, 2018
    Assignee: INPHI CORPORATION
    Inventor: Tom Broekaert
  • Patent number: 9874888
    Abstract: In one example, a circuit includes a voltage source, a pass module, a differential amplifier module, and a control module. The pass module is configured to electronically couple, using a channel having a resistance, the voltage source and a load and to modify the resistance of the channel based on a control signal. The differential amplifier module is configured to generate a differential signal based on a comparison of a voltage reference and a representation of a voltage at the load. The control signal is based on the differential signal. The control module is configured to generate the representation of the voltage at the load according to a transfer function. The transfer function includes a zero positioned substantially at a crossover frequency of the transfer function.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: January 23, 2018
    Assignee: Infineon Technologies AG
    Inventor: Derek Bernardon
  • Patent number: 9831832
    Abstract: A low noise amplifier (LNA) includes a first transistor and a second transistor. A source of the second transistor is connected to a drain of the first transistor. The LNA further includes a feedback transformer. A gate of the first transistor is connected to a primary winding of the feedback transformer and a gate of the second transistor is connected to a secondary winding of the feedback transformer.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsuan Liu, Hsieh-Hung Hsieh, Tzu-Jin Yeh
  • Patent number: 9813044
    Abstract: An active high gain filter includes high value resistances in feedback implemented using a negative resistance circuit configuration. The high value resistance is implemented using two or smaller resistances connected in the negative resistance circuit configuration. This implementation permits integration of the filter circuit using less occupied area while still providing an accurate transfer function response.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: November 7, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventor: Marco Orazio Cavallaro
  • Patent number: 9787264
    Abstract: Techniques and mechanisms for providing signal communication with a configurable transceiver circuit. In an embodiment, an integrated circuit comprises transceiver circuitry including an output stage and current mirror circuitry. The output stage is coupled to receive a differential signal pair and to provide at least one output signal based on the differential signal pair. In another embodiment, configuration logic is operable to select between a first mode and a second mode of the transceiver circuit. The first mode includes the current mirror circuitry being disabled from providing a current signal to the output stage, and a first circuit path being closed to provide voltage to the output stage. The second mode includes the first circuit path being open and the current mirror circuitry being enabled to provide a current signal to the output stage.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Miaobin Gao, Christine M. Krause, Hiu-Chin Wu, Hengju Cheng
  • Patent number: 9780745
    Abstract: Disclosed herein are a method, circuitry and an integrated circuit chip for use in signal processing. The integrated circuit chip comprises an operational amplifier, a reference amplifier, and a control unit. The control unit is coupled to the reference amplifier and to the operational amplifier. The control unit is configured to control the reference amplifier based on a signal received from the reference amplifier.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 3, 2017
    Assignee: Infineon Technologies AG
    Inventors: Christoph Boehm, Maximilian Hofer
  • Patent number: 9774305
    Abstract: A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: September 26, 2017
    Assignee: INPHI CORPORATION
    Inventor: Tom Broekaert
  • Patent number: 9728829
    Abstract: A circuit for blocking undesired input direct current of AC-coupled broadband circuits. The circuit includes a capacitor coupled to an input port and a common node. The input port receives a RF input signal. Additionally, the circuit includes a current source supplying a DC current to the common node leading a bias current to an output port. Further, the circuit includes a variable voltage source through an internal load and a close loop with an application circuit having an input load coupled to the output port to determine various bias voltages to control the bias current at the output port in association with a RF output signal that is substantially free of any input direct current originated from the RF input signal and is associated with an inherent low cut-off frequency independent of the various bias voltages.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: August 8, 2017
    Assignee: INPHI CORPORATION
    Inventors: Ariel Leonardo Vera Villarroel, Subramaniam Shankar, Steffen O. Nielsen
  • Patent number: 9717431
    Abstract: A differential voltage measuring system includes two electrodes that are connected to a patient at an input and make available a respective measurement contact at an output. A shunt resistor is connected in series with the second electrode. A first amplifier circuit has a first input for a first signal from the first electrode, a second input for a second signal from the second electrode, and an output. A second amplifier circuit has a first input that is connected in series with the shunt resistor, a second input that is connected in parallel with the shunt resistor, and an output. A first signal detection unit is provided at the output of the first amplifier circuit, and a second signal detection unit is provided at the output of the second amplifier circuit. The second signal detection unit detects the signal from the second amplifier circuit as a measurement variable.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: August 1, 2017
    Assignee: Siemens Aktiengesellschaft
    Inventors: Ulrich Batzer, Peter Greif, Harald Karl
  • Patent number: 9692375
    Abstract: Disclosed is a circuit having a differential stage comprising a pair or transistors. The transistors are biased by respective bias transistors. Each bias transistor has a respective feedback network configured to reduce transconductance of the bias transistor, to increase a gain of the differential stage.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: June 27, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • Patent number: 9692381
    Abstract: Circuits providing low noise amplification with continuous time linear equalization are described. An exemplary circuit includes four amplification elements, such as MOS transistors. The amplification elements are arranged in differential pairs, and the differential pairs are cross-coupled with a frequency-dependent coupling, such as a capacitive coupling, to enhance high-frequency gain. The outputs of the amplification elements are combined to provide an output representing inverted and un-inverted sums of differences in the input signals.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: June 27, 2017
    Assignee: KANDOU LABS, S.A.
    Inventor: Armin Tajalli
  • Patent number: 9588533
    Abstract: An integrated circuit voltage regulator uses a simple CMOS structure to implement a High Unity Gain BandWidth voltage regulator providing for low voltage ripple at the output of the regulator up to high frequencies in the hundreds of MHz range. A transconductor first stage is followed by an impedance cancellation second stage allowing DC gain to be set completely independently of the bandwidth.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: March 7, 2017
    Assignee: Entropic Communications, LLC
    Inventor: Raed Moughabghab
  • Patent number: 9509253
    Abstract: A circuit may include an amplifying circuit and a t-coil inductor. The amplifying circuit may include an input node, an output node, an amplifier, and a feedback loop. The feedback loop may be coupled between the input node and the output node. The amplifying circuit may be configured to receive a current signal on the input node and to output a voltage signal based on the current signal on the output node. The t-coil inductor may include a first portion and a second portion. A first node of the first portion may be coupled to the input node of the amplifying circuit and the second portion may be included in the feedback loop.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Nikola Nedovic
  • Patent number: 9509256
    Abstract: An apparatus includes: a plurality of amplification stages, each stage comprising a cascode transistor; and a bridge circuit coupled between gate terminals of cascode transistors in two adjacent stages of the plurality of amplification stages, the bridge circuit including a plurality of diodes.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: November 29, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Saihua Lin, Anup Savla
  • Patent number: 9431977
    Abstract: A system for a feedback amplifier with sub-40 khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing an amplifier having feedback paths comprising source followers and feedback resistors. Gate terminals of the source followers may be coupled to output terminals of the amplifier circuit. The feedback paths may be coupled prior to the coupling capacitors at inputs of the amplifier circuit. Voltages may be level shifted prior to the coupling capacitors to ensure stable bias conditions for the amplifier circuit. The amplifier circuit may be integrated in a CMOS photonics chip with the source followers comprising CMOS transistors. The amplifier circuit may receive current-mode logic or voltage signals. The electrical signals may be received from a photodetector, which may comprise a silicon germanium photodiode differentially coupled to the amplifier circuit. Optical signals for the photodetector in the chip may be received via optical fibers.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: August 30, 2016
    Assignee: Luxtera, Inc.
    Inventor: Brian Welch
  • Patent number: 9419564
    Abstract: Circuits providing low noise amplification with continuous time linear equalization are described. An exemplary circuit includes four amplification elements, such as MOS transistors. The amplification elements are arranged in differential pairs, and the differential pairs are cross-coupled with a frequency-dependent coupling, such as a capacitive coupling, to enhance high-frequency gain. The outputs of the amplification elements are combined to provide an output representing inverted and un-inverted sums of differences in the input signals.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: August 16, 2016
    Assignee: KANDOU LABS, S.A.
    Inventor: Armin Tajalli
  • Patent number: 9413309
    Abstract: Provided herein are apparatus and methods for a cascode amplifier topology for millimeter-wave power application. The cascode amplifier can use a neutralized common source stage cascoded with a bootstrapped common gate stage to provide an amplifier topology having enhanced performance, gain, stability and reliability. Additionally, a bootstrap capacitor of the common gate stage can be patterned between the source fingers and the drain fingers of a cascode transistor so as to improve device performance. Operating as an RF power amplifier, a single-stage cascode amplifier using the neutralized common source stage with the bootstrapped common gate stage can provide greater than 15 dB of power gain to signals of the E band.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: August 9, 2016
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Dixian Zhao, Patrick Reynaert, Michael F. Keaveney
  • Patent number: 9385671
    Abstract: A circuit includes a first pair of transistors connected in parallel between a first node and a second node with a diode-connected transistor coupled to the second node. A second pair of transistors has current terminals connected at a third node. A first and second current sink transistors are connected in a current mirror configuration with the diode-connected transistor and further coupled to the third node. A first differential amplifier has an output coupled to control terminals of the first and third transistors and an input coupled to a further current node of the third transistor. A second differential amplifier has an output coupled to control terminals of the second and fourth transistors and an input coupled to a further current node of the fourth transistor.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: July 5, 2016
    Assignee: STMicroelectronics S.r.l.
    Inventor: Marco Orazio Cavallaro
  • Patent number: 9369097
    Abstract: An apparatus includes a first path tuned to a first frequency band and a second path tuned to a second frequency band. The apparatus also includes cross-coupled circuitry having a first input coupled to the first path and a second input coupled to the second path and having a first output coupled to the second path and a second output coupled to the first path.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: June 14, 2016
    Assignee: Qualcomm Incorporated
    Inventor: Saihua Lin
  • Patent number: 9362824
    Abstract: A constant on-time control switching converter with DC calibration is disclosed. A current flowing into a capacitor of a DC calibration circuit is reduced by introducing a transconductance amplifier and a resistor. Thus, the equivalent capacitance of the capacitor is magnified, which allows the user to integrate a capacitor with smaller capacitance to realize DC calibration.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: June 7, 2016
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventor: Qian Ouyang
  • Patent number: 9202561
    Abstract: A resistive memory device incorporates a reference current generation circuit to generate a reference current for the sense amplifier that is immune to variation in the resistance of the reference resistive memory cells. In some embodiments, the reference current generation circuit uses reference resistive memory cells configured in the low resistance state only. The reference current generation circuit generates the reference current by combining a reference cell current and a bias current. The bias current is regulated by a feedback circuit in response to changes in the reference current to maintain the reference current at a substantially constant value and having a current value being an average of the cell currents for a resistive memory cell in the high resistance state and the low resistance state.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: December 1, 2015
    Assignee: Integrated Silicon Solution, Inc.
    Inventors: Geun-Young Park, Seong Jun Jang, Justin Kim
  • Patent number: 9160324
    Abstract: A buffer circuit includes a buffering unit suitable for buffering an input signal and outputting an output signal and a feedback control unit suitable for adjusting a slew rate of the input signal in response to the output signal.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: October 13, 2015
    Assignee: SK Hynix Inc.
    Inventor: Tae-Jin Hwang
  • Patent number: 9148087
    Abstract: Circuits providing low noise amplification with continuous time linear equalization are described. An exemplary circuit includes four amplification elements, such as MOS transistors. The amplification elements are arranged in differential pairs, and the differential pairs are cross-coupled with a frequency-dependent coupling, such as a capacitive coupling, to enhance high-frequency gain. The outputs of the amplification elements are combined to provide an output representing inverted and un-inverted sums of differences in the input signals.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: September 29, 2015
    Assignee: KANDOU LABS, S.A.
    Inventor: Armin Tajalli
  • Patent number: 9112455
    Abstract: In a signal amplifying circuit, a flow rate signal, inputted between flow rate signal input terminals of a connector, is inputted into one input terminal and the other input terminal of an instrumentation amplifier through resistive elements and subjected to differential amplification. The amplified output signal thereof is outputted to a sample hold circuit through a coupling capacitor. The flow rate signals, inputted between the flow rate signal input terminals, are buffered by buffer amplifiers, and output signals thereof are outputted to a fault detecting circuit. An interconnection, which connects one of the flow rate signal input terminals and a non-inverting input terminal of one of the buffer amplifiers, is guarded by a guard ring pattern. An interconnection, which connects the other one of the flow rate signal input terminals and a non-inverting input terminal of the other one of the buffer amplifiers, is guarded by another guard ring pattern.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: August 18, 2015
    Assignee: AZBIL CORPORATION
    Inventors: Osamu Momose, Ichiro Mitsutake, Shinsuke Matsunaga, Taka Inoue, Masahide Ushiyama
  • Patent number: 9059673
    Abstract: An amplifier circuit and an operation method thereof are provided. The amplifier circuit includes two stages of amplifiers. When the amplifier circuit is operated in a high gain mode, the two stages of amplifiers are operated normally to provide high gain. When the amplifier circuit is operated in a low gain mode, the second stage of amplifier is turned off, and the first stage of amplifier is coupled to output terminals of the amplifier circuit through signal isolation elements so as to form a single stage of amplifier. Therefore, the amplifier circuit can change the total gain value thereof according to a requirement of gain.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: June 16, 2015
    Assignee: Novatek Microelectronics Corp.
    Inventor: Ying-Chung Chiu
  • Publication number: 20150145597
    Abstract: A multi-stage transimpedance amplifier (TIA) which includes a common gate amplifier configured to receive a current signal, the common gate amplifier is configured to convert the current signal into an amplified voltage signal. The multi-stage TIA further includes a capacitive degeneration amplifier configured to receive the amplified voltage signal, the capacitive degeneration amplifier is configured to equalize the amplified voltage signal to form an equalized signal. The multi-stage TIA further includes an inverter configured to receive the equalized signal, the inverter is configured to increase a signal strength of the equalized signal to form an output signal. The multi-stage TIA further includes a feedback configured to receive the output signal, wherein the feedback is connected to an input and an output of the inverter.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 28, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN
  • Publication number: 20150130539
    Abstract: A quasi-differential amplifier with an input port and an output port. The amplifier has a phase shifter network with a first port connected to the input port, a second port, and a third port. A first amplifier has an input connected to the second port of the phase shifter network, and an output, and a second amplifier has an input connected to the third port of the phase shifter network, and an output. A balun circuit includes a first differential port connected to an output of the first amplifier, a second differential port connected to an output of the second amplifier, and a single-ended port. An output matching network is connected to the single-ended port of the balun circuit and to the output port.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 14, 2015
    Inventor: OLEKSANDR GORBACHOV
  • Publication number: 20150130538
    Abstract: In one embodiment, a differential amplifier circuit includes a first input terminal, a second input terminal, a first transistor, a second transistor, a third transistor, a current source, a first output terminal, a second output terminal, a first passive element, and a second passive element. The first (second) transistor has a control terminal connected to the first (second) input terminal. The third transistor has a control terminal. The control terminal is applied predetermined bias voltage. The current source is connected to a first terminal in each of the first transistor, second transistor, and third transistor. The first (second) output terminal is connected to a second terminal of the first (second) transistor. The first (second) passive element is connected between the first (second) input terminal and the first (second) output terminal.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 14, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tetsuro ITAKURA, Masanori FURUTA, Shunsuke KIMURA, Go KAWATA, Hideyuki FUNAKI
  • Patent number: 9031517
    Abstract: The present invention discloses a transmit-receive (TR) front end. The TR front end includes a low-noise amplifier (LNA); a power amplifier (PA); a transformer, coupled to the PA, for increasing a voltage swing and a power transmission of the PA; and a TR switch, coupled between the transformer and the LNA. The LNA is single ended and there is no transformer between the LNA and the TR switch.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: May 12, 2015
    Assignee: Mediatek
    Inventors: Albert Chia-Wen Jerng, Wen-Kai Li, Chien-Cheng Lin
  • Patent number: 9008332
    Abstract: A processing chip for a digital microphone and related input circuit and a digital microphone are described herein. In one aspect, the input circuit for a processing chip of a digital microphone includes: a PMOS transistor, a resistor, a current source, and a low-pass filter. The described processing chip possesses high anti high-frequency interference capabilities and the described input circuit possesses high high-frequency power supply rejection ratio.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 14, 2015
    Assignee: Beijing KT Micro, Ltd.
    Inventors: Wenjing Wang, Jianting Wang, Rongrong Bai, Jing Cao
  • Publication number: 20150091645
    Abstract: An envelope tracking power transmitter includes an envelope amplifier, a common-gate power modulation linearizer and a power amplifier. The envelope amplifier may receive a first envelope voltage to generate a power supply voltage that is amplified in proportion to change of the first envelope voltage. The common-gate power modulation linearizer may receive a second envelope voltage to amplify the second envelope voltage according to change of the second envelop voltage. The power amplifier may receive a first output of the envelope amplifier as a power supply voltage and a drain bias voltage, may receive a second output of the common-gate power modulation linearizer as a common gate bias voltage, and may amplify a radio frequency (RF) input signal to provide a RF output signal by maintaining an output capacitance according to an envelope of the RF input signal.
    Type: Application
    Filed: September 29, 2014
    Publication date: April 2, 2015
    Inventors: Chul Soon Park, Woo Young Kim, Inn Yeal Oh, Joo Young Jang, Hyuk Su Son
  • Publication number: 20150084695
    Abstract: In one embodiment, a cascode amplifier includes an amplifier circuit, a replica circuit, a bias circuit, and a feedback circuit. The amplifier circuit includes a first transistor and a second transistor. The second transistor is cascode-connected to the first transistor. The replica circuit includes a third transistor and a fourth transistor. The third transistor has a control terminal connected to a control terminal of the first transistor. The fourth transistor is cascode-connected to the third transistor. The bias circuit applies a bias voltage to a control terminal of the second transistor and a control terminal of the fourth transistor. The feedback circuit performs a feedback control of a voltage of the control terminal of the third transistor. The feedback circuit reduces the difference between a reference current and a current at a predetermined point of the replica circuit.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 26, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kohei Onizuka
  • Patent number: 8988402
    Abstract: An output circuit includes a differential amplifier circuit, an output amplifier circuit, a control circuit, input and output terminals, and first to third supply terminals applied with first to third supply voltages, respectively. The third supply voltage is set a voltage between the first and second supply voltages. The differential amplifier circuit differentially receives signals of the input and output terminals. The output amplifier circuit includes first and second transistors of different conduction type each other coupled in series between the first and third supply terminals via the output terminal, and having control terminals coupled to first and second output nodes of the differential amplifier circuit, respectively. The control circuit includes a third transistor and a switch, and controls the third transistor being in a diode coupling mode between the first supply terminal and the control terminal of the first transistor for a given period of the output period.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Tsuchi
  • Patent number: 8970305
    Abstract: An amplifier circuit including an amplifier, a first feedback path, and a second feedback path. The amplifier is configured to amplify an input signal in accordance with a gain. The first feedback path includes a first capacitance, and responsive to the input signal being within in a first frequency range, the first feedback path configured to provide feedback from the output of the amplifier to an inverting input of the amplifier. The second feedback path includes a first resistance connected in series with a second capacitance, and responsive to the input signal being within in a second frequency range, the second feedback path is configured to provide feedback from the output of the amplifier to the inverting input of the amplifier. The second frequency range is less than the first frequency range, and the gain of the amplifier levels off according to a value of the second capacitance.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 3, 2015
    Assignee: Marvell International Ltd.
    Inventor: Farbod Aram
  • Patent number: 8963641
    Abstract: A differential amplifier circuit that includes a negative resistor in parallel to synthesize a larger source resistance is disclosed. In one or more implementations, a differential amplifier circuit includes a first transistor and a second transistor. The first transistor is configured to receive a first differential input and the second transistor is configured to receive a second differential input. The differential amplifier circuit also includes a third transistor and a fourth transistor that form a pair of cross-coupled transistors coupled to the first transistor and the second transistor. The pair of cross-coupled transistors are configured to generate a negative impedance at an output node, and the negative impedance, combined with an impedance of the first transistor, is configured to generate a sufficient termination impedance for a transmission line electrically connected to the output node.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Edward W. Liu
  • Patent number: 8964074
    Abstract: An amplification circuit includes an amplifier, a first capacitor including a first terminal connected to an input terminal of the amplifier, a second capacitor including a first terminal connected to the input terminal of the amplifier and a second terminal connected to an output terminal of the amplifier, and a correction unit configured to correct a difference in bias dependency between capacitance values of the first and second capacitors.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: February 24, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideo Kobayashi, Masanori Ogura
  • Patent number: 8963448
    Abstract: An output buffer circuit includes an amplifier and a transmission circuit. The amplifier includes a plurality of inputs and an output. The inputs provide first input signals and second input signals to the amplifier. The output provides an output signal as a first input signal of the first input signals to the amplifier. The transmission circuit has an input coupled to the output of the amplifier and further has an output that provides a transmission circuit output signal as a second input signal of the second input signals to the amplifier.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung Tae Kim, Soo Ik Cha, Jun Ho Song, Jin Chul Choi, Chul Ho Choi