Remote isolation device module
Latest Teradyne, Inc. Patents:
- Method for reduction of SIC MOSFET gate voltage glitches
- Waveguide connector for connecting first and second waveguides, where the connector includes a male part, a female part and a self-alignment feature and a test system formed therefrom
- Reducing timing skew in a circuit path
- Probe for a test system
- Managing memory in an electronic system
Description
FIG. 1 is a perspective view of the module;
FIG. 2 is a top view of the module;
FIG. 3 is a bottom view of the module;
FIG. 4 is a front view of the module;
FIG. 5 is a back view of the module;
FIG. 6 is a view of the left side of the module; and
FIG. 7 is a view of the right side of the module.
Referenced Cited
Patent History
Patent number: D291559
Type: Grant
Filed: Nov 13, 1984
Date of Patent: Aug 25, 1987
Assignee: Teradyne, Inc. (Boston, MA)
Inventors: Brian C. Narveson (Deerfield, IL), John Toth (Buffalo Grove, IL)
Primary Examiner: Wallace R. Burke
Assistant Examiner: Ruth E. Takemoto
Application Number: 6/670,955
Type: Grant
Filed: Nov 13, 1984
Date of Patent: Aug 25, 1987
Assignee: Teradyne, Inc. (Boston, MA)
Inventors: Brian C. Narveson (Deerfield, IL), John Toth (Buffalo Grove, IL)
Primary Examiner: Wallace R. Burke
Assistant Examiner: Ruth E. Takemoto
Application Number: 6/670,955
Classifications
Current U.S. Class:
D13/99