Semi-conductor substrate with conducting pattern

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Description

FIG. 1 is a top perspective view of a semi-conductor substrate with conducting pattern shwoing our new design;

FIG. 2 is a bottom perspective view thereof;

FIG. 3 is a right side elevational view thereof;

FIG. 4 is a left side elevational view thereof;

FIG. 5 is a rear elevational view thereof; and

FIG. 6 is a front elevational view thereof.

FIG. 7 is a top plan view thereof; and

FIG. 8 is a bottom plan view thereof.

Referenced Cited
U.S. Patent Documents
4288841 September 8, 1981 Gogal
4338621 July 6, 1982 Braun
4437141 March 13, 1984 Prokop
4458291 July 3, 1984 Yanagisawa et al.
4513355 April 23, 1985 Shroeder et al.
4677526 June 30, 1987 Muehling
4698663 October 6, 1987 Sugimoto et al.
Foreign Patent Documents
0232837 August 1987 EPX
0048945 March 1983 JPX
644662 November 1984 JPX
647072 December 1984 JPX
647074 December 1984 JPX
647078 December 1984 JPX
673983 November 1985 JPX
673983-1 November 1985 JPX
673984 November 1985 JPX
150353 July 1986 JPX
0271863 December 1986 JPX
0035653 February 1987 JPX
Other references
  • Electronic Design, p. 7, dtd 10-16-86, NCR 1C package pictured thereon. Electronic Design, p. 190, dtd 10-16-86, Disc Controll picured thereon. Electronics, p. 131, dtd 8-7-86, CMOS chip pictured thereon. Electronics, p. 7, Feb. 24, 1986, by Fujitsu Microelectronics, Inc.
Patent History
Patent number: D319814
Type: Grant
Filed: Apr 13, 1988
Date of Patent: Sep 10, 1991
Assignee: Ibiden Co., Ltd. (Ogaki)
Inventors: Terutomi Hasegawa (Ogaki), Nobumichi Goto (Seki)
Primary Examiner: Susan J. Lucas
Assistant Examiner: J. Sincavage
Law Firm: Lorusso & Loud
Application Number: 7/181,262