Semiconductor wafer testing apparatus

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Description

FIG. 1 is a top, front and right side perspective view of a semiconductor wafer testing apparatus showing my new design;

FIG. 2 is a top plan view;

FIG. 3 is a front elevational view;

FIG. 4 is a left side elevational view;

FIG. 5 is a right side elevational view;

FIG. 6 is a rear elevational view; and,

FIG. 7 is a bottom plan view thereof.

Referenced Cited
U.S. Patent Documents
D323628 February 4, 1992 Takao
5141212 August 25, 1992 Beeding
5264069 November 23, 1993 Dietrich et al.
Other references
  • Fully Automatic Wafer Prober Model 785, Tokyo Electron Limited, p. 2.
Patent History
Patent number: D350490
Type: Grant
Filed: Apr 7, 1993
Date of Patent: Sep 13, 1994
Assignees: Tokyo Electron Kabushiki Kaisha (Tokyo), Tokyo Electron Yamanashi Kabushiki Kaisha (Irasaki)
Inventor: Itaru Takao (Nirasaki)
Primary Examiner: Alan P. Douglas
Assistant Examiner: Antoine D. Davis
Law Firm: Ladas & Parry
Application Number: 0/6,815