Semiconductor wafer measuring instrument
Latest Tokyo Electron Limited Patents:
Description
FIG. 1 is a top, front and right side perspective view of a semiconductor wafer measuring instrument showing my new design;
FIG. 2 is a front elevational view;
FIG. 3 is a right side elevational view, the left side elevational view being a mirror image;
FIG. 4 is a top plan view;
FIG. 5 is a rear elevational view; and
FIG. 6 is a bottom plan view thereof.
Referenced Cited
U.S. Patent Documents
Foreign Patent Documents
D188789 | September 1960 | Hannon |
D223174 | March 1972 | Pettavel |
D262950 | February 9, 1982 | Orr, II |
D277979 | March 12, 1985 | Brown et al. |
D307397 | April 24, 1990 | Lehtikoski |
D314347 | February 5, 1991 | Garnish et al. |
4530635 | July 23, 1985 | Engelbrecht et al. |
4684113 | August 4, 1987 | Douglas et al. |
4700488 | October 20, 1987 | Curti |
4719705 | January 19, 1988 | Laganza et al. |
4723766 | February 9, 1988 | Beeding |
4907931 | March 13, 1990 | Mallory et al. |
4938654 | July 3, 1990 | Schram |
4941800 | July 17, 1990 | Koike et al. |
4955590 | September 11, 1990 | Narushima et al. |
733184 | January 1988 | JPX |
Patent History
Patent number: D323628
Type: Grant
Filed: Apr 25, 1989
Date of Patent: Feb 4, 1992
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Itaru Takao (Yamanashi)
Primary Examiner: Bruce W. Dunkins
Assistant Examiner: Antoine D. Davis
Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt
Application Number: 7/343,124
Type: Grant
Filed: Apr 25, 1989
Date of Patent: Feb 4, 1992
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Itaru Takao (Yamanashi)
Primary Examiner: Bruce W. Dunkins
Assistant Examiner: Antoine D. Davis
Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt
Application Number: 7/343,124
Classifications
Current U.S. Class:
Measuring, Regulating Or Indicating Instrument, Or Casing (D10/46)