Piezoelectric semiconductor element
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Description
FIG. 1 is a front view of the inventive design for a piezoelectric semiconductor element;
FIG. 2 is a top view of the inventive design of FIG. 1;
FIG. 3 is a bottom view of the inventive design of FIG. 1;
FIG. 4 is a left side view of the inventive design of FIG. 1;
FIG. 5 is a right side view of the inventive design of FIG. 1;
FIG. 6 is a rear view of the inventive design of FIG. 1; and,
FIG. 7 is a cross-section view of the inventive design of FIG. 1 taken along the lines 7--7 of FIG. 6.
Referenced Cited
U.S. Patent Documents
Foreign Patent Documents
Other references
D251185 | February 27, 1979 | Fanshawe |
3968466 | July 6, 1976 | Nakamura et al. |
4596155 | June 24, 1986 | Kistler |
4661653 | April 28, 1987 | Aigo |
4732042 | March 22, 1988 | Adams |
4764747 | August 16, 1988 | Kurtz et al. |
4782319 | November 1, 1988 | Dell'Acqua et al. |
5317921 | June 7, 1994 | Kremidas |
1-10552 | May 1991 | JPX |
- Japanese Watch Institute Report No. 120, p. 8, FIG. 5, Mar. 20, 1987 Electronic Technology; p. 52; Mar. 1986.
Patent History
Patent number: D356778
Type: Grant
Filed: Sep 24, 1993
Date of Patent: Mar 28, 1995
Assignee: Seiko Epson Corporation (Nagano)
Inventors: Kiyoto Takeda (Nagano), Kiyoteru Furukawa (Tokyo)
Primary Examiner: Joel Sincavage
Law Firm: Oliff & Berridge
Application Number: 0/13,420
Type: Grant
Filed: Sep 24, 1993
Date of Patent: Mar 28, 1995
Assignee: Seiko Epson Corporation (Nagano)
Inventors: Kiyoto Takeda (Nagano), Kiyoteru Furukawa (Tokyo)
Primary Examiner: Joel Sincavage
Law Firm: Oliff & Berridge
Application Number: 0/13,420
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)