Processing tube for use in a semiconductor wafer heat processing apparatus
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Description
FIG. 1 a perspective view of a processing tube for use in a semiconductor wafer heat processing apparatus;
FIG. 2 a front elevational view thereof;
FIG. 3 a top plan view thereof;
FIG. 4 a bottom plan view thereof;
FIG. 5 a cross sectional view thereof taken along line V--V in FIG. 2;
FIG. 6 a rear elevational view thereof;
FIG. 7 a left side view thereof;
FIG. 8 a right side view thereof;
FIG. 9 a cross sectional view thereof taken along line IX--IX in FIG. 3; and,
FIG. 10 a cross sectional view thereof taken along line X--X in FIG. 3.
Referenced Cited
U.S. Patent Documents
4587689 | May 13, 1986 | Lee |
5046909 | September 10, 1991 | Murdoch |
5314574 | May 24, 1994 | Takahashi |
5320218 | June 14, 1994 | Yamashita et al. |
5407449 | April 18, 1995 | Zinger |
5516732 | May 14, 1996 | Flegal |
5518360 | May 21, 1996 | Toda et al. |
5536128 | July 16, 1996 | Shimoyashiro et al. |
5658115 | August 19, 1997 | Yamazaki et al. |
5752796 | May 19, 1998 | Muka |
Patent History
Patent number: D406113
Type: Grant
Filed: Jul 24, 1997
Date of Patent: Feb 23, 1999
Assignee: Tokyo Electron Limited (Tokyo-To)
Inventors: Tetsuya Hanagata (Tokyo), Shingo Watanabe (Kanagawa)
Primary Examiner: Brian N. Vinson
Law Firm: Ladas & Parry
Application Number: 0/74,293
Type: Grant
Filed: Jul 24, 1997
Date of Patent: Feb 23, 1999
Assignee: Tokyo Electron Limited (Tokyo-To)
Inventors: Tetsuya Hanagata (Tokyo), Shingo Watanabe (Kanagawa)
Primary Examiner: Brian N. Vinson
Law Firm: Ladas & Parry
Application Number: 0/74,293
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;
International Classification: 1303;