Surface mount package

- GEM Services, Inc.
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Description

FIG. 1 is a perspective view of a surface mount package showing my new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a bottom plan view thereof:

FIG. 4 is a front elevational view thereof:

FIG. 5 is a rear elevational view thereof;

FIG. 6 is a left side elevational view thereof; and,

FIG. 7 the right side elevational view thereof.

The broken line showing the environment is for illustrative purpose only and forms not part of the claimed design.

Claims

The ornamental design for a surface mount package, as shown and described.

Referenced Cited
U.S. Patent Documents
4984062 January 8, 1991 Uemira et al.
5224021 June 29, 1993 Takada et al.
5446623 August 29, 1995 Kanetake
5521429 May 28, 1996 Aono et al.
5689135 November 18, 1997 Ball
6211462 April 3, 2001 Carter, Jr. et al.
Other references
  • JEDEC Solid State Product Outlines, “Small Outline J-Lead” (SOJ).300 Body Family (MS-013 Body), Issue A, Jun., 1988, MO-088, AA-AF.
  • JEDEC Solid State Product Outline, Low Profile Small Outline J-Lead Package (LSOJ), PRSO-J/LSOJ, Issue B, Jun., 1999, MO-199, pp. 1-5.
  • JEDEC Solid State Product Outlines, “Plastic Small Outline (SOJ) Package Family with.330 Inch Body Width”, Issue B, May, 1992, MO-121, pp. 1-2.
Patent History
Patent number: D467885
Type: Grant
Filed: Jul 18, 2001
Date of Patent: Dec 31, 2002
Assignee: GEM Services, Inc. (Santa Clara, CA)
Inventors: James Harnden (Hollister, CA), Richard K. Williams (Cupertino, CA), Anthony Chia (Singapore), Chu Weibing (Shanghai)
Primary Examiner: Mitchell Siegel
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Townsend and Townsend and Crew LLP
Application Number: 29/145,292
Classifications
Current U.S. Class: Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;