Semiconductor device

- Kabushiki Kaisha Toshiba
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Description

FIG. 1 is a front perspective view of a semiconductor device, showing our new design;

FIG. 2 is a rear perspective view thereof;

FIG. 3 is a top plan view thereof; a bottom plan view being a mirror image thereof;

FIG. 4 is a right side elevational view thereof; a left side elevational view being a mirror image thereof;

FIG. 5 is a front elevational view thereof;

FIG. 6 is a rear elevational view thereof;

FIG. 7 is a front perspective view of a second embodiment of a semiconductor device, showing our new design;

FIG. 8 is a rear perspective view thereof;

FIG. 9 is a top plan view thereof; a bottom plan view being a mirror image thereof;

FIG. 10 is a right side elevational view thereof; a left side elevational view being a mirror image thereof;

FIG. 11 is a front elevational view thereof; and,

FIG. 12 is a rear elevational view thereof.

Claims

The ornamental design for a semiconductor device, as shown and described.

Referenced Cited
U.S. Patent Documents
5401910 March 28, 1995 Mandai et al.
5450286 September 12, 1995 Jacques et al.
5459641 October 17, 1995 Kuriyama
5726859 March 10, 1998 Khadem et al.
D396846 August 11, 1998 Nakayama et al.
6232655 May 15, 2001 Sugimura
D444132 June 26, 2001 Iwanishi et al.
6330165 December 11, 2001 Kohjiro et al.
6459048 October 1, 2002 Sakai et al.
Other references
  • Website showing a Power MOSFET (P series).
  • Catalog showing a Power MOSFET (PowerFLAT).
Patent History
Patent number: D476962
Type: Grant
Filed: Sep 27, 2002
Date of Patent: Jul 8, 2003
Assignee: Kabushiki Kaisha Toshiba (Tokyo)
Inventors: Takayuki Yoshihira (Yokohama), Gentaro Ookura (Tokyo)
Primary Examiner: Ted Shooman
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/168,143
Classifications
Current U.S. Class: Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;