Electronics component package element
Latest Pulse Engineering, Inc. Patents:
Description
FIG. 1 is a side elevation view of a first embodiment of an electronics component package, showing our new design;
FIG. 2 is a top plan view thereof;
FIG. 3 is a bottom plan view thereof;
FIG. 4 is a front elevation view thereof;
FIG. 5 is a side elevation view of a second embodiment of an electronics component package, showing our new design;
FIG. 6 is a top plan view thereof;
FIG. 7 is a bottom plan view thereof; and,
FIG. 8 is a front plan view thereof.
Claims
The ornamental design of an electronics components package element, as shown and described herein.
Referenced Cited
U.S. Patent Documents
Other references
3638149 | January 1972 | Bopp et al. |
4292614 | September 29, 1981 | Ono et al. |
4507633 | March 26, 1985 | Minks |
4924213 | May 8, 1990 | Decho et al. |
5438307 | August 1, 1995 | Chou |
5801930 | September 1, 1998 | Dittmann |
6549108 | April 15, 2003 | Fausch |
- Allied Electronics, 1990,pp. 402 (upper left), 615 (upper right and middle left).
Patent History
Patent number: D487255
Type: Grant
Filed: Mar 10, 2003
Date of Patent: Mar 2, 2004
Assignee: Pulse Engineering, Inc. (San Diego, CA)
Inventors: Tung Dang (San Marcos, CA), Glen Alan Cotant (Ramona, CA)
Primary Examiner: Nanda Bondade
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Gazdzinski & Associates
Application Number: 29/177,596
Type: Grant
Filed: Mar 10, 2003
Date of Patent: Mar 2, 2004
Assignee: Pulse Engineering, Inc. (San Diego, CA)
Inventors: Tung Dang (San Marcos, CA), Glen Alan Cotant (Ramona, CA)
Primary Examiner: Nanda Bondade
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Gazdzinski & Associates
Application Number: 29/177,596
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;
International Classification: 1303;