Semiconductor device
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Description
FIG. 1 is a front, top and right side perspective view of a semiconductor device, showing my new design;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a rear elevational view thereof;
FIG. 4 is a top plan view thereof;
FIG. 5 is a bottom plan view thereof;
FIG. 6 is a left side elevational view thereof; and,
FIG. 7 is a right side elevational view thereof.
Claims
The ornamental design for a semiconductor device, as shown and described.
Referenced Cited
U.S. Patent Documents
Foreign Patent Documents
4346396 | August 24, 1982 | Carroll, II et al. |
D280812 | October 1, 1985 | Takahashi |
5459350 | October 17, 1995 | Date et al. |
5512784 | April 30, 1996 | Fried et al. |
5563441 | October 8, 1996 | Kato |
D420983 | February 22, 2000 | Choi |
6362517 | March 26, 2002 | Bell et al. |
6404065 | June 11, 2002 | Choi |
751629 | December 1988 | JP |
865628 | April 1993 | JP |
Patent History
Patent number: D489695
Type: Grant
Filed: Sep 30, 2002
Date of Patent: May 11, 2004
Assignee: Kabushiki Kaisha Toshiba (Tokyo)
Inventor: Satoshi Komoto (Tokyo)
Primary Examiner: Philip S. Hyder
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/168,230
Type: Grant
Filed: Sep 30, 2002
Date of Patent: May 11, 2004
Assignee: Kabushiki Kaisha Toshiba (Tokyo)
Inventor: Satoshi Komoto (Tokyo)
Primary Examiner: Philip S. Hyder
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/168,230
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;
International Classification: 1303;