Circuit board
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Description
FIG. 1 is a front perspective of the invention.
FIG. 2 is a plan elevation of the invention.
FIG. 3 is a bottom plan of the invention.
FIG. 4 is a front elevation of the invention.
FIG. 5 is a rear elevation of the invention.
FIG. 6 is a right end elevation of the invention; and,
FIG. 7 is a left end elevation of the invention.
The broken lines define the boundary of the claimed design and form no part of the claimed design.
Claims
The ornamental design for a circuit board, as shown and described.
Referenced Cited
Patent History
Patent number: D525213
Type: Grant
Filed: May 1, 2003
Date of Patent: Jul 18, 2006
Assignee: Siemens Aktiengesellschaft (Munich)
Inventors: Janos-Gerold Enderlein (Berlin), Jörg Romahn (Berlin)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Morrison & Foerster LLP
Application Number: 29/180,813
Type: Grant
Filed: May 1, 2003
Date of Patent: Jul 18, 2006
Assignee: Siemens Aktiengesellschaft (Munich)
Inventors: Janos-Gerold Enderlein (Berlin), Jörg Romahn (Berlin)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Morrison & Foerster LLP
Application Number: 29/180,813
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)