Electronic device

- Intel
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Description

FIG. 1 is a perspective view illustrating an electronic device design according to one embodiment;

FIG. 2 is a front view illustrating an electronic device design according to one embodiment;

FIG. 3 is a back view illustrating an electronic device design according to one embodiment;

FIG. 4 is a side view illustrating an electronic device design according to one embodiment;

FIG. 5 is another side view illustrating an electronic device design according to one embodiment;

FIG. 6 is a top view illustrating an electronic device design according to one embodiment;

FIG. 7 is a bottom view illustrating an electronic device design according to one embodiment;

FIG. 8 is a perspective view illustrating an electronic device design according to one embodiment;

FIG. 9 is a front view illustrating an electronic device design according to one embodiment;

FIG. 10 is a back view illustrating an electronic device design according to one embodiment;

FIG. 11 is a side view illustrating an electronic device design according to one embodiment;

FIG. 12 is another side view illustrating an electronic device design according to one embodiment;

FIG. 13 is a top view illustrating an electronic device design according to one embodiment; and,

FIG. 14 is a bottom view illustrating an electronic device design according to one embodiment.

The broken lines shown immediately adjacent to the shaded areas in FIGS. 1 and 8 and also those shown immediately adjacent to the solid contour lines surrounding the unshaded region of the display window in FIGS. 8, 9, 13, represent the bounds of the claimed design, while all other broken lines are directed to environment and form no part of the claimed design.

Claims

The ornamental design for an electronic device, as shown and described.

Referenced Cited
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6785128 August 31, 2004 Yun
6816365 November 9, 2004 Hill et al.
D615539 May 11, 2010 Jen
D616883 June 1, 2010 Denhez et al.
D631472 January 25, 2011 Kawase et al.
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20050041378 February 24, 2005 Hamada et al.
Other references
  • “Thunderbolt (interface)” retrieved Aug. 7, 2012 from Wikipedia at http://en.wikipedia.org/wiki/Thunderbolt—%28interface%29 ; 7 pages.
  • Nelson, Tom, “What is Thunderbolt High Speed I/O?”, retrieved Aug. 7, 2012 from http://macs.about.com/od/faq1/f/What-Is-Thunderbolt-High-Speed-I-O.htm ; 2 pages.
  • Intel Corporation Technology Brief, “Thunderbolt Technology”, copyright 2012. Retrieved Aug. 7, 2012 from http://www.intel.com/content/dam/doc/technology-brief/thunderbolt-technology-brief.pdf ; 4 pages.
  • VAIO 13.1″ Z Series Laptop; retrieved Jul. 31, 2012 from http://store.sony.com/webapp/wcs/stores/servlet/ProductDisplay?catalogId=10551&storeId=10151&langId=-1&productId=8198552921666449851#additionalImage1″ , 3 pages.
Patent History
Patent number: D694748
Type: Grant
Filed: Jul 30, 2012
Date of Patent: Dec 3, 2013
Assignee: Intel Corporation (Santa Clara, CA)
Inventors: James M. Okuley (Portland, OR), Kimi Jensen (Beaverton, OR)
Primary Examiner: Freda S Nunn
Application Number: 29/428,400
Classifications
Current U.S. Class: Laptop Type (D14/315)