Abstract: Embodiments are generally directed to selective packing of patches for immersive video. An embodiment of a processing system includes one or more processor cores; and a memory to store data for immersive video, the data including a plurality of patches for multiple projection directions. The system is to select the patches for packing, the selection of the patches based at least in part on which of the multiple projection directions is associated with each of the patches. The system is to encode the patches into one or more coded pictures according to the selection of the patches.

Abstract: This disclosure describes systems, methods, and devices related to control frames status. A device may receive a control frame from a station (STA) at a beginning of a transmission opportunity (TxOP) that includes availability and unavailability information. The device may acknowledge the availability and unavailability information of the STA based on fields within the control frame, including unavailability target start time field and unavailability duration field. The device may adjust a transmission schedule to avoid transmitting to the STA during its indicated unavailability period. The device may initiate a TxOP with an initial control frame that includes updated availability and unavailability information based on the control frame from the STA.

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

Abstract: Network apparatus, communicatively coupled to a provider of services, that includes gateway circuitry to receive application programming interface (API) request data from a computing device that indicates a requested service. The gateway circuitry is to (1) select, based upon the API request data, at least one of the services corresponding to the requested service, and (2) generate, based upon mapping of the API request data to the at least one of the services, corresponding request data specifically for use in invoking the at least one of the services. The gateway circuitry is to (1) generate the corresponding request data by performing at least one programmable transformation, (2) be used in association with at least one proxy-related operation, (3) register the services for use in association with service discovery, and (4) verify the API request data and an identity associated with the computing device.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

Abstract: Described herein is a graphics processor having processing resources with configurable thread and register configurations. Program code can configure a number of registers and accumulators that will be used by hardware threads during execution of the program code by the graphics processor. Processing resources within the graphics processor can be configured to assign different numbers of registers and accumulators to hardware threads based on the configuration requested by program code to be executed by the processing resource.

Abstract: Techniques for instruction prefix encoding for cryptographic computing capability data types are described. In an embodiment, an apparatus includes an instruction decoder to decode a first instruction including a first prefix; and cryptography circuitry to perform a cryptographic operation on data, the cryptographic operation to be based at least in part on the first prefix and a relative enumeration in a pointer to the data.

Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a positive-type photo-imageable dielectric (PID) material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter through the material on the surface, a second diameter at the surface of the glass layer, and the first diameter is equal to the second diameter plus 1 micron or minus 1 micron; and a dielectric layer on the material at the surface of the glass layer, the dielectric layer including a conductive pathway electrically coupled to the via.

Abstract: An integrated circuit structure includes a plurality of interconnect lines and a plurality of dummy lines that are co-planar with the plurality of interconnect lines, where a ratio of line length to end-to-end spacing of the dummy lines varies inversely with a density of the interconnect lines within each of a plurality of regions. The regions are of approximately equal area within a rectangular grid array.

Abstract: Physical therapy assistant-as-a-service (PTaaS) enables the automatic evaluation of a patient's performance of physical therapy exercises and the automatic provision of feedback to the patient on their exercise performance in real-time. A patient device can provide real-time patient exercise video to a PTaaS backend that performs checks prior to the patient performing the exercise (pre-checks) and checks during patient performance of the exercise (live checks). If any of the checks fail, the PTaaS can provide feedback to the patient, such as if the patient is in an incorrect starting pose or has a body part at an incorrect angle before beginning the exercise or if the patient's form or posture during performance of the exercise needs to be adjusted. The PTaaS can automatically generate exercise metrics, reports, and physical therapy insights that a physical therapy clinician can access from a clinician portal.

Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a polyimide or a dielectric material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter through the material on the surface, a second diameter at the surface of the glass layer, and the first diameter is equal to the second diameter plus 1 micron or minus 1 micron; and a dielectric layer on the material at the surface of the glass layer, the dielectric layer including a conductive pathway electrically coupled to the via.

Abstract: A wavelength multiplexing optical fiber transmitter, receiver, or transceiver where multiple emitters and/or photodetectors of different center wavelengths are coupled to a single optical fiber core terminus through multiple waveguides, which may be directly printed in free space. The optical assemblies described are suitable for optical data link applications, for example, to reduce a number of optical fibers needed for a given bandwidth or increase the bandwidth of a give number of optical fibers. Bidirectional fiber termination may also be implemented with an emitter and a photodetector pair coupled to a single optical fiber core terminus through multiple waveguides.

Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.

Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.

Abstract: Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.

Abstract: Acknowledgment management techniques for UL MU transmissions are described. In various embodiments, an AP may observe a limit with respect to a number of TIDs for which corresponding A-MPDUs are to be acknowledged in a given immediate/compressed multi-user (MU) block ACK (BA). In some embodiments, the AP may indicate such a TID limit in a broadcast transmission, such as a beacon or management frame. In various other embodiments, the AP may indicate such a TID limit in a response for a capability request, such as a Probe Response, or in a specific allocation frame, such as a trigger frame, for all STAs participating in UL MU transmissions. In various embodiments, a single TID limit may be indicated that is understood to apply to each STA. In some other embodiments, the AP may indicate a respective TID limit for each of multiple STAs. Other embodiments are described and claimed.

Abstract: An embodiment of an integrated circuit comprises circuitry to store memory protection information for a non-host memory in a memory protection cache, and perform one or more memory protection checks on a translated access request for the non-host memory based on the stored memory protection information. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine version information for a new firmware component, read dependency information corresponding to the firmware component, and determine if dependency is satisfied between the new firmware component and one or more other firmware components based on the version information and the dependency information of the new firmware component. Other embodiments are disclosed and claimed.

Abstract: Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.

Abstract: An apparatus is described. The apparatus includes a packaged semiconductor device. The packaged semiconductor device having an integrated heat spreader, wherein, a boiling enhancement structure exists on the integrated heat spreader without a block mass residing between the boiling enhancement structure and the integrated heat spreader. The boiling enhancement structure has a structured non-planar surface to promote bubble nucleation in an immersion cooling system.