Patents Assigned to Intel Corporation
  • Patent number: 10237855
    Abstract: Embodiments of the present disclosure include methods, apparatuses, and instructions for receiving at a user equipment (UE) of a third generation partnership project (3GPP) network an offset value selected from a plurality of offset values in downlink control information. The UE also receives one or more enhanced control channel elements (eCCEs) of an enhanced physical downlink control channel (ePDCCH). The UE may then determine an allocation of an uplink resource for a transmission on a physical uplink control channel (PUCCH) based at least in part on the index of a first eCCE and the offset value.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Seunghee Han, Yuan Zhu, Jong-Kae Fwu
  • Patent number: 10237872
    Abstract: Techniques for group-based spatial stream assignment signaling in 60 GHz wireless networks are described. According to various such techniques, a 60 GHz-capable transmitting device may be configured to define one or more DL MU-MIMO groups, each of which may comprise one or more respective 60 GHz-capable receiving devices. In various embodiments, the 60 GHz-capable transmitting device may include a DL MU-MIMO group ID within DL MU-MIMO control information in a PHY header of a PPDU in order to indicate that the PPDU is directed to a DL MU-MIMO group corresponding to that DL MU-MIMO group ID. In some embodiments, DL MU-MIMO control information may comprise information specifying spatial stream assignments for the 60 GHz-capable receiving devices of that DL MU-MIMO group. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Chittabrata Ghosh, Carlos Cordeiro
  • Patent number: 10234833
    Abstract: Technologies for predicting the power usage of a data center are disclosed. A data center manager gathers sensor data from the compute devices of the data center. The sensor data indicates factors such as power used by the compute device and the intake air inlet temperature. The data center manager trains a machine-learning-based algorithm based on training sensor data, and then applies the machine-learning-based algorithm to sensor data as it is being gathered. The machine-learning-based algorithm can predict a change in future power usage of the data center, and control a cooling unit to compensate before the power usage even begins to change.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Nishi Ahuja, Rahul Khanna, Abishai Daniel, Zhijie Sheng
  • Patent number: 10231632
    Abstract: Described is an apparatus which comprises: a current source to generate a current having AC and DC components; a current-to-voltage converter to convert the current or a copy of the current to a voltage proportional to a resistance, the voltage having AC and DC components that correspond to the AC and DC components of the current; a first sample-and-hold circuit to sample and filter the AC component from the voltage and to provide an output voltage with the DC component; a second sample-and-hold circuit to sample the output voltage; a voltage-to-current converter to convert the sampled output voltage to a corresponding current; and an amplifier to receive the output voltage.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventor: Craig P. Finlinson
  • Patent number: 10235327
    Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Huimin Chen, Duane G. Quiet
  • Patent number: 10235175
    Abstract: A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, William C. Rash, Yazmin A. Santiago
  • Patent number: 10234930
    Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Victor W. Lee, Edward T. Grochowski, Daehyun Kim, Yuxin Bai, Sheng Li, Naveen K. Mellempudi, Dhiraj D. Kalamkar
  • Patent number: 10234920
    Abstract: In one embodiment, a processor includes: at least one core to execute instructions; a power controller to control power consumption of the processor; and a storage to store a plurality of entries to associate a dynamic capacitance with a time duration for which a current spike is to be exposed to a power delivery component. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Jorge P. Rodriguez
  • Patent number: 10237696
    Abstract: A method for location-based assistance includes maintaining in a personal digital assistant (PDA) (22, 24, 26) a data structure that is indicative of a state of a user (32, 34, 36) of the PDA. Responsively to the state, a map (30) is generated in the PDA indicating targets (42, 44, 46, 48) within an area of relevance surround a present location of the user. Based on the map, the PDA provides a suggestion to the user of an action to be taken by the user with respect to one or more of the targets.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Ronen Aharon Soffer, Amir Yessachar
  • Patent number: 10234956
    Abstract: Processing techniques and device configurations for performing and controlling output effects at a plurality of wearable devices are generally described herein. In an example, a processing technique may include receiving, at a computing device, an indication of a triggering gesture that occurs at a first wearable device, determining an output effect corresponding to the indication of the triggering gesture, and in response to determining the output effect, transmitting commands to computing devices that are respectively associated with a plurality of wearable devices, the commands causing the plurality of wearable devices to generate the output effect at the plurality of wearable devices. In further examples, output effects such as haptic feedback, light output, or sound output, may be performed by the plurality of wearable devices, associated computing devices, or other controllable equipment.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Saurin Shah, Narayan Sundararajan, Manan Goel, Brian K. Vogel, Jason Blanchard, Jason Wright, Lakshman Krishnamurthy, Swarnendu Kar
  • Patent number: 10235302
    Abstract: In an embodiment, a processor for invalidating cache entries comprises: at least one processing unit; a processor cache; and direct cache unit. The direct cache unit is to receive, from a first device, a direct read request for data in a first cache entry in the processor cache; determine whether the direct read request is an invalidating read request; in response to a determination that the direct read request is an invalidating read request: send the data in the first cache entry directly from the processor cache to the first device without accessing a main memory; and invalidate the first cache entry in the processor cache. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Samantha J. Edirisooriya, Geetani R. Edirisooriya
  • Patent number: 10235128
    Abstract: An embodiments of a contextual sound apparatus may include a sound identifier to identify a sound, a context identifier to identify a context, and an action identifier communicatively coupled to the sound identifier and the context identifier to identify an action based on the identified sound and the identified context. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Robert L. Vaughn, James B. Eynard
  • Patent number: 10235180
    Abstract: A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Srikanth T. Srinivasan, Matthew C. Merten, Bambang Sutanto, Rahul R. Kulkarni, Justin M. Deinlein, James D. Hadley
  • Patent number: 10235171
    Abstract: An apparatus includes a first circuit to determine a real program order (RPO) of an eldest undispatched instruction from among a plurality of strands, a second circuit to determine an RPO limit based on a delta value and the RPO of the eldest undispatched instruction, an ordering buffer to store entries for instructions that are waiting to be retired, and a third circuit to execute an orderable instruction from a strand from the plurality of strands to cause an entry for the orderable instruction to be inserted into the ordering buffer in response to a determination that an RPO of the orderable instruction is less than or equal to the RPO limit.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Alexander Y. Ostanevich, Jayesh Iyer, Sergey P. Scherbinin, Dmitry M. Maslennikov, Denis G. Motin, Alexander V. Ermolovich, Andrey Chudnovets, Sergey A. Rozhkov, Boris A. Babayan
  • Patent number: 10235526
    Abstract: Various embodiments are directed to a system for accessing a self-encrypting drive (SED) upon resuming from a sleep power mode (SPM) state. An SED may be authenticated within a system, for example, upon resuming from a sleep state, based on unwrapping the SED passphrase with a SPM resume passphrase stored in a standby power register to receive power during the SPM state.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Asher Altman, Mark Schmisseur
  • Patent number: 10235301
    Abstract: Generally, this disclosure provides systems, methods and computer readable media for a page table edit controller configured to control access to guest page tables by virtual machine (VM) guest software through the manipulation of extended page tables. The system may include a translation look-aside buffer (TLB) to maintain a policy to lock one or more guest linear addresses (GLAs) to one or more allowable guest physical addresses (GPAs); a page walk processor to update the TLB based on the guest page tables; and a page table edit control (PTEC) module to: identify entries of the guest page tables that map GLAs associated with the policy to a first GPA; verify that the mapping conforms to the policy; and place the guest page table into one of a plurality of restricted accessibility states based on the verification, the restricted accessibility applied to the VM guests and to the page walk processor.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Michael Lemay, David M. Durham, Andrew V. Anderson, Gilbert Neiger, Ravi L. Sahita
  • Patent number: 10235732
    Abstract: A method and system are described herein for an optimization technique on two aspects of thread scheduling and dispatch when the driver is allowed to pick the scheduling attributes. The present techniques rely on an enhanced GPGPU Walker hardware command and one dimensional local identification generation to maximize thread residency.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Jayanth N. Rao, Michal Mrozek
  • Patent number: 10235177
    Abstract: In an example, an apparatus includes a binary translator (BT) including circuitry to: analyze a code block; determine that an architectural register mapped to a physical register in the physical register file is available for early reclamation; and insert a reclamation hint into the code block. In another example, a processor reclaims the physical register based at least in part on the reclamation hint.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Vineeth Mekkat, Janghaeng Lee, Youfeng Wu
  • Patent number: 10236233
    Abstract: Embodiments of heat spreaders with integrated preforms, and related devices and methods, are disclosed herein. In some embodiments, a heat spreader may include: a frame formed of a metal material, wherein the metal material is a zinc alloy or an aluminum alloy; a preform secured in the frame, wherein the preform has a thermal conductivity higher than a thermal conductivity of the metal material; and a recess having at least one sidewall formed by the frame. The metal material may have an equiaxed grain structure. In some embodiments, the equiaxed grain structure may be formed by squeeze-casting or rheocasting the metal material.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Aravindha R. Antoniswamy, Thomas J. Fitzgerald
  • Patent number: D843367
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Aleksander Magi, Randall W. Martin