Patents Assigned to Intel Corporation
  • Publication number: 20210133913
    Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.
    Type: Application
    Filed: October 13, 2020
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker, Josh Mastronarde, Iqbal Rajwani, Lakshminarayanan Striramassarma, Melaku Teshome, Vikranth Vemulapalli, Binoj Xavier
  • Publication number: 20210135007
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Application
    Filed: January 13, 2021
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
  • Publication number: 20210136680
    Abstract: A system comprising an interface to access a network slice power consumption parameter for a network slice comprising a logical network between two endpoints through a plurality of physical computing platforms; and a controller comprising circuitry, the controller to specify operating parameters for a plurality of hardware resources of a first physical computing platform in accordance with the network slice power consumption parameter.
    Type: Application
    Filed: December 11, 2020
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: John J. Browne, Chris M. MacNamara, David Hunt, Amruta Misra, Tomasz Kantecki, Shobhi Jain, Liang Ma
  • Publication number: 20210136378
    Abstract: Techniques related to adaptive quality boosting for low latency video coding are discussed. Such techniques include segmenting each of a number of temporally adjacent video frames into unique high encode quality regions and encoding each of the video frames by applying a coding quality boost to the high encode quality regions relative to other regions of the video frames.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Ximin Zhang, Changliang Wang, Sang-hee Lee, Keith Rowe
  • Publication number: 20210134153
    Abstract: A controller comprises processing circuitry to collect traffic information in a geographic region and generate traffic statistics for the region using the traffic information and a communication interface to forward the traffic statistics to an optical transmitter assembly. Other examples may be described and claimed.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventor: Fan Wang
  • Publication number: 20210135478
    Abstract: A workload dependent load-sharing mechanism in a multi-battery system. The mechanism is an energy management system that operates in three modes—energy saving mode, balancer mode, and turbo mode. The energy saving mode is a normal mode where the multiple batteries provide power to their own set of loads with least resistive dissipation. In balancing mode, the batteries are connected through switches operating in active mode so that the current shared is inversely proportion to the corresponding battery state-of-charge. In turbo mode, both batteries are connected in parallel through switches (e.g., on-switches) to provide maximum power to a processor or load. A controller optimizes the sequence and charging rate for a hybrid battery to maximize both the charging current and charging speed of the battery, while enabling longer battery life. The hybrid battery comprises a fast charging battery and a high-energy density battery.
    Type: Application
    Filed: December 23, 2020
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Jeffrey Schline, Samantha Rao, Naoki Matsumura, Ramon Cancel Olmo, Tod Schiff, Arunthathi Chandrabose
  • Publication number: 20210132306
    Abstract: An optical system can include a optical receiver comprising an optical waveguide, an optical lid adjacent the waveguide, and a reflective surface proximate an output of the optical waveguide to direct light from the waveguide towards an output of the optical lid. The optical system can also include a photodetector (PD) die comprising a substrate, a concave mirror, and a photodetector. The concave mirror is formed on a first side of the substrate and the photodetector is disposed on a second side of the substrate, the first side opposite the second side, wherein the photodetector is disposed on the second side of the PD die offset from the optical axis of the optical element.
    Type: Application
    Filed: December 11, 2020
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Alexander Krichevsky, John M. Heck
  • Publication number: 20210132665
    Abstract: A device includes an enclosure and logic. The enclosure includes a plurality of capacitive touch sensor arrays disposed at least on two of a top side, a bottom side, a left side, a right side, a front side, and a back side of the device. The enclosure also includes a first display on the front side of the device. The logic receives touch interaction information from the plurality of capacitive touch sensor arrays and initiates an action based at least in part on the touch interaction information.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Min Liu, Lakshman Krishnamurthy, David L. Graumann, Jameson H. Williams, Miriam K. Selvaraj, Bryan R. Peebler, Wendy A. March, Brian K. Vogel, Wenbo Shen, Sihua Tian, Lijuan Xiao, Tao Wang, Xiaoyan Dang, Nithyananda S. Jeganathan, Sunil A. Kulkarni, Sherman Chan Wai Lee, Kaining Yuan
  • Publication number: 20210134802
    Abstract: Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Tahir Ghani, Doug Ingerly, Rajesh Kumar
  • Publication number: 20210132123
    Abstract: A scheme for measuring AC and DC load-line (LL) using voltage and current monitoring apparatus. During calibration for LL measurement, a tested or known workload is executed on a processor or system-on-chip (SoC). The calibration can be done when the processor is first used in a real-time system (customer) scenario, or repeated whenever necessary to compensate silicon aging or other effects that affect the LL values. LL is estimated, determined, and/or calculated for each power supply rail in the processor or SoC. The measured LL is used in calculations that determine the operating voltage of an input voltage regulator (VR) at run time, thereby optimizing the power/performance characteristics of that specific system.
    Type: Application
    Filed: December 19, 2020
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Vijay Anand Mathiyalagan, Stephen Gunther
  • Publication number: 20210132943
    Abstract: Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a double word with saturation; computing a dot product of bytes and accumulating in to a dword with saturation, where the input bytes can be signed or unsigned and the dword accumulation has output saturation; etc.
    Type: Application
    Filed: July 1, 2017
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Robert VALENTINE, Dan BAUM, Zeev SPERBER, Jesus CORBAL, Elmoustapha OULD-AHMED-VALL, Bret L. TOLL, Mark J. CHARNEY, Menachem ADELMAN, Barukh ZIV, Alexander HEINECKE, Simon RUBANOVICH
  • Publication number: 20210134731
    Abstract: Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.
    Type: Application
    Filed: January 14, 2021
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventor: John S. GUZEK
  • Publication number: 20210132658
    Abstract: In an example, there is disclosed a two-in-one tablet computer, including: a tablet, including a microprocessor, a memory, a touchscreen, a solid-state disk drive, a primary battery, and a Microsoft Windows operating system; a detachable keyboard, including a magnetic hinge to magnetically snap the detachable keyboard to the tablet, circuitry to communicatively dock the detachable keyboard to the tablet via the magnetic hinge, and a secondary battery, wherein the magnetic hinge is configured to yield to one-handed human force to unsnap the tablet from the detachable keyboard; and a software monitor including instructions to determine that the detachable keyboard has been unsnapped from the tablet, and perform a software decoupling.
    Type: Application
    Filed: January 12, 2021
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Han Chau, Nithyananda S. Jeganathan, Bryan Y. Roe
  • Publication number: 20210134698
    Abstract: A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assembly or package between at least one integrated circuit device and a heat dissipation device.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Kyle J. Arrington, Aaron McCann, Kelly Lofgreen, Elah Bozorg-Grayeli, Aravindha Antoniswamy, Joseph B. Petrini
  • Publication number: 20210133518
    Abstract: An example apparatus for mining multi-scale hard examples includes a convolutional neural network to receive a mini-batch of sample candidates and generate basic feature maps. The apparatus also includes a feature extractor and combiner to generate concatenated feature maps based on the basic feature maps and extract the concatenated feature maps for each of a plurality of received candidate boxes. The apparatus further includes a sample scorer and miner to score the candidate samples with multi-task loss scores and select candidate samples with multi-task loss scores exceeding a threshold score.
    Type: Application
    Filed: April 7, 2017
    Publication date: May 6, 2021
    Applicant: INTEL CORPORATION
    Inventors: Anbang Yao, Yun Ren, Hao Zhao, Tao Kong, Yurong Chen
  • Patent number: 10996141
    Abstract: A method for operating an autonomous ground vehicle may include: via one or more processors, determining an occupation state of the autonomous ground vehicle; if the occupation state is unoccupied, autonomously initiating a testing routine, the testing routine comprising: determining a test location, determining a safety parameter of the test location; if the safety parameter fulfils a safety criterion, testing an autonomous driving system of the autonomous ground vehicle in the test location.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 4, 2021
    Assignee: INTEL CORPORATION
    Inventor: Glen Anderson
  • Patent number: 10994202
    Abstract: The present disclosure includes a method for generating simulated previews of dynamic virtual cameras, the method comprising receiving virtual camera descriptor data, receiving object tracking data, generating virtual camera behavior data based on the virtual camera descriptor data and the object tracking data, the virtual camera behavioral data corresponding to virtual camera parameters for rendering a view, and generating a simulated preview based on the object tracking data and the virtual camera behavioral data.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Fai Yeung, Patrick Youngung Shon, Gilson Goncalves De Lima, Vasanthi Jangala Naga
  • Patent number: 10993673
    Abstract: Technologies for filtering biosignals include one or more biosignal sensors coupled to a user to receive biosignals and a computing device to receive biosignals from the biosignal sensors. The biosignal sensors filter the received biosignals to identify abnormal biosignals using a plurality of domain filters including a time domain filter and a frequency domain filter. The biosignals identified as abnormal by each of the domain filters are transmitted to the computing device, while the remaining biosignals are discarded.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Venkat Natarajan, Sowmya Jonnada
  • Patent number: 10997273
    Abstract: An apparatus and method are described for distributed and cooperative computation in artificial neural networks. For example, one embodiment of an apparatus comprises: an input/output (I/O) interface; a plurality of processing units communicatively coupled to the I/O interface to receive data for input neurons and synaptic weights associated with each of the input neurons, each of the plurality of processing units to process at least a portion of the data for the input neurons and synaptic weights to generate partial results; and an interconnect communicatively coupling the plurality of processing units, each of the processing units to share the partial results with one or more other processing units over the interconnect, the other processing units using the partial results to generate additional partial results or final results. The processing units may share data including input neurons and weights over the shared input bus.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Frederico C. Pratas, Ayose J. Falcon, Marc Lupon, Fernando Latorre, Pedro Lopez, Enric Herrero Abellanas, Georgios Tournavitis
  • Patent number: 10996860
    Abstract: An apparatus for controlling a solid state drive (SSD) includes an host interface, to receive a set of memory access commands from a host computer, and processing circuitry coupled to the host interface and to memory cells of the SSD, to distinguish the write commands from the read commands in the set, and execute up to a threshold number of the write commands prior to executing any of the read commands.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Suresh Nagarajan, Shankar Natarajan