Abstract: Systems, apparatus, articles of manufacture, and methods to improve thermal dissipation and mechanical loading of integrated circuit packages are disclosed. An example apparatus includes: a socket to receive an integrated circuit package; and a plate to apply a load on the integrated circuit package towards the socket. The plate includes an internal channel to carry a coolant through the plate. The liquid coolant is to facilitate cooling of the integrated circuit package.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for inductors of voltage regulators that are built into and/or around mounting holes of a printed circuit board. An example apparatus includes a printed circuit board that includes a plurality of layers and a mounting hole extending through the plurality of layers, and an inductor at least partially in the mounting hole between two or more of the plurality of layers.

Abstract: Systems and methods for controlling flexible displays are disclosed herein. An example apparatus includes interface circuitry; machine-readable instructions; and at least one processor circuit to at least one of instantiate or execute the machine-readable instructions to determine a distance of a user relative to a display screen based on outputs of a sensor, the sensor in communication with one or more of the at least one processor circuit; determine a curvature radius of the display screen based on the user distance; and cause an actuator to adjust a curvature of the display screen based on the curvature radius.

Abstract: Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface, the trench having a depth; and a burr in the trench having a height that is less than the depth of the trench.

Abstract: Systems and methods to trigger LLM inference based on the presences of relevant audio, such as a keyword or sound event of interest. A detection head receives acoustic embeddings from an audio encoder and determines whether the audio stream includes relevant sounds (e.g., a selected audio trigger). When the audio stream does not include relevant sounds, multimodal LLM inference is bypassed, thereby saving power and protecting privacy. When relevant sounds are detected in the audio stream by the detector, the acoustic embeddings from the audio encoder are transmitted to the multimodal LLM, which proceeds to perform inference on the acoustic embeddings. The audio encoder and/or detection head can be offloaded in the hardware and implemented before the multimodal LLM in the hardware pipeline, while the multimodal LLM can be implemented in a neural processing unit.

Abstract: For example, an apparatus may include logic and circuitry configured to cause a parameter-setting server to establish a connection with a Wireless Local Area Network (WLAN) station (STA). For example, the parameter-setting server may be configured to send WLAN parameter-setting information to the WLAN STA via the connection with the WLAN STA. For example, the WLAN parameter-setting information may be configured to indicate a setting of one or more WLAN parameters to be implemented by the WLAN STA for communication in a WLAN. For example, the WLAN STA may be configured to process the WLAN parameter-setting information from the parameter-setting server to identify the setting of the one or more WLAN parameters to be implemented by the WLAN STA. For example, the WLAN STA may be configured to communicate one or more transmissions in the WLAN, for example, according to the setting of the one or more WLAN parameters.

Abstract: Techniques for computer power management are disclosed. In one embodiment, a data center includes several compute nodes and a power management node. Power telemetry data is gathered at each of the compute nodes and sent to the power management node. The power management node analyzes the telemetry data, such as by applying filtering to identify certain metrics. The power management node may use rules to analyze the telemetry data and determine whether power management actions should be performed. The power management node may instruct the compute node to, e.g., change a power state of a processor or processor core. In some embodiments, cores may be managed by an orchestrator, and the orchestrator may identify cores to be placed in high-power and low-power states, as appropriate.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to improve inspection techniques for integrated circuits with backside power delivery. An example disclosed apparatus includes at least one programmable circuit to at least one of instantiate or execute the machine readable instructions to modulate first and second bitlines for a bitcell in a memory array of an integrated circuit between first and second voltages at a frequency for a period of time, the modulating of the first and second bitlines to produce a periodic heat signal in the integrated circuit, cause a thermal imaging sensor to capture a series of images of the integrated circuit during the period of time, and determine a location of a defect in the integrated circuit based on the series of images.

Abstract: An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

Abstract: The present application provides a system including a plurality of components to be mounted to a first device in a preset layout and generate a magnetic field; a magnetometer integrated with a second device to detect the magnetic field to generate reading data associated with the magnetic field at the second device; and a processor configured to determine a position of the second device relative to the first device based on the reading data and the preset layout of the plurality of components.

Abstract: Systems and devices can include an error injection register comprising error injection parameter information. The systems and devices can also include error injection logic circuit to read error injection parameter information from the error injection register, and inject an error into a flow control unit (Flit); and protocol stack circuitry to transmit the Flit comprising the error on a multilane link. The injected error can be detected by a receiver and used to test and characterize various aspects of a link, such as bit error rate, error correcting code, cyclic redundancy check, replay capabilities, error logging, and other characteristics of the link.

Abstract: Embodiments are directed to trusted local memory management in a virtualized GPU. An embodiment of an apparatus includes one or more processors including a trusted execution environment (TEE); a GPU including a trusted agent; and a memory, the memory including GPU local memory, the trusted agent to ensure proper allocation/deallocation of the local memory and verify translations between graphics physical addresses (PAs) and PAs for the apparatus, wherein the local memory is partitioned into protection regions including a protected region and an unprotected region, and wherein the protected region to store a memory permission table maintained by the trusted agent, the memory permission table to include any virtual function assigned to a trusted domain, a per process graphics translation table to translate between graphics virtual address (VA) to graphics guest PA (GPA), and a local memory translation table to translate between graphics GPAs and PAs for the local memory.

Abstract: A wearable device measures heart rate recovery of a user in a non-clinical setting. The wearable device comprises a heart rate detector configured to detect heart rate data of the user, an activity sensor configured to detect motion of the user, and a processor. The processor is configured to identify a start of an activity by the user using the motion detected by the activity sensor. Responsive to detecting the start of the activity, the processor monitors the motion detected by the activity sensor to identify an end of the activity. A regression analysis is performed on heart rate data detected by the heart rate detector during a period of time after the end of the activity, and the heart rate recovery of the user is determined using the regression analysis.

Abstract: Described herein are techniques for automatic bug fixing of implementation RTL code to transform the code into RTL code that is closer to a reference specification. Two designs, such as a known-good reference specification and an updated implementation, can be compared in functionality via an e-graph. Rewrites are applied from the direction of the specification code to find a design that is equivalent to the specification, but syntactically close to the current implementation.

Abstract: Methods and apparatus to disengage a test head from an integrated circuit (IC) device are disclosed. An example apparatus comprises a test head to thermally interface with an IC device, a mounting piece to be coupled to the test head, and a push off tab to be mounted to the mounting piece, the push off tab including an arm to extend underneath the test head, the arm to contact the IC device before the test head is to contact the IC device.

Abstract: Technologies for secure device configuration and management include a computing device having an I/O device. A trusted agent of the computing device is trusted by a virtual machine monitor of the computing device. The trusted agent securely commands the I/O device to enter a trusted I/O mode, securely commands the I/O device to set a global lock on configuration registers, receives configuration data from the I/O device, and provides the configuration data to a trusted execution environment. In the trusted I/O mode, the I/O device rejects a configuration command if a configuration register associated with the configuration command is locked and the configuration command is not received from the trusted agent. The trusted agent may provide attestation information to the trusted execution environment. The trusted execution environment may verify the configuration data and the attestation information. Other embodiments are described and claimed.

Abstract: A time-to-digital converter (TDC) that combines the energy efficiency of a successive approximation (SAR) design with the high speed of pipelined converters by leveraging the inherently pipelined nature of time-domain signaling. The TDC achieves high speed by removing a comparator decision from a signal path, instead using AND/OR gates to separate early and late edges. The TDC uses a pipelined SAR architecture to digitize a differential delay between two incoming clock edges with high speed and low power consumption. Described is a modular digital reference voltage generator that can be used for a capacitive digital-to-analog converter (DAC). The generator comprises a decoupling capacitor, one or more clocked comparators, and power transistor(s). A simplified digital low dropout (LDO) circuitry is used to provide fast reference voltage generation with minimal overhead. The LDO circuitry is arrayed using time-interleaved synchronous clocks or staggered asynchronous clocks to provide finer timing resolution.

Abstract: In one embodiment, an apparatus includes: an interface to couple a plurality of devices of a system and enable communication according to a Compute Express Link (CXL) protocol. The interface may receive a consistent memory request having a type indicator to indicate a type of consistency to be applied to the consistent memory request. A request scheduler coupled to the interface may receive the consistent memory request and schedule it for execution according to the type of consistency, based at least in part on a priority of the consistent memory request and one or more pending consistent memory requests. Other embodiments are described and claimed.

Abstract: An apparatus and method for multiplying packed real and imaginary components of complex numbers and complex conjugates. For example, one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed real and imaginary data elements; a second source register to store a second plurality of packed real and imaginary data elements; and execution circuitry to execute the decoded instruction. The execution circuitry includes multiplier circuitry to multiply select real and imaginary data elements in the first and second source registers to generate a plurality of real and imaginary products; adder circuitry to add/subtract various real and imaginary products, scale the results according to an immediate of the instruction, round the scaled results; and saturation circuitry to saturate the rounded results.

Abstract: Methods and apparatus to operate closed-lid portable computers are disclosed. An example portable computer includes a first display on a lid of the portable computer, the first display to be deactivated when the lid is in a closed position; a second display distinct from the first display, the second display to be visible when the lid is in the closed position; instructions; and processor circuitry to execute the instructions to cause activation of the first display in response to a user interaction with the second display while the lid is in the closed position.