Patents Assigned to Intel Corporation
  • Publication number: 20240130068
    Abstract: Technologies for a flexible three-dimensional power plane in a chassis are disclosed. In one embodiment, a flexible ribbon cable is laid along a circuit board tray. The flexible ribbon cable is secured to the tray using power bosses. The power bosses connect to one or more conductors on the ribbon cable. When the circuit board is mounted on the circuit board tray, the power bosses extend through holes in the circuit board and mate with power clips on the surface of the circuit board tray. The ribbon cable, power bosses, and power clips can distribute power to various locations on the circuit board, without requiring large traces that take up space on the circuit board.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Nan Wang, Zhichao Z. Zhang, Lihui Wu, Jialiang Xu, Xiaoguo Liang, Bo Chen, Haifeng Gong
  • Publication number: 20240129944
    Abstract: For example, a wireless communication device may be configured to determine an expected interference-based value corresponding to an Uplink (UL) transmission from a wireless communication station (STA) in a Trigger-Based (TB) Multi-User (MU) UL transmission to be communicated from a plurality of STAs to the wireless communication device; to determine one or more transmit (Tx) configuration parameters for the STA based on the expected interference-based value corresponding to the UL transmission from the STA; and to transmit a trigger frame to trigger the TB MU UL transmission, the trigger frame including the one or more Tx configuration parameters to configure the UL transmission from the STA.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: INTEL CORPORATION
    Inventors: Alexander W. Min, Arik Klein, Rath Vannithamby, Ziv Avital
  • Publication number: 20240128982
    Abstract: A hardware accelerator device is provided with circuitry to perform one or more reversible data transforms on data based on a request and compress the transformed data to generate compressed transformed data. The hardware accelerator device generates an output including the compressed transformed data and transform metadata indicating the set of reversible data transforms applied to the compressed transformed data.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Smita Kumar, Patrick Fleming
  • Publication number: 20240129804
    Abstract: For example, an Access Point (AP) may be configured to process network slicing information including slice identification information and Service Level Agreement (SLA) information, wherein the slice identification information is to identify one or more Quality of Service (QoS) network slices. For example, the AP may be configured to determine a configuration of one or more radio resource allocations to be assigned to the one or more QoS network slices, and to transmit a network slicing advertisement including network slicing assignment information to indicate an assignment of the one or more radio resource allocations to the one or more QoS network slices.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Roya Doostnejad, Ehud Reshef, Laurent Cariou
  • Publication number: 20240130002
    Abstract: Various technologies relating to wireless sensor networks (WSNs) are disclosed, including, but not limited to, device onboarding and authentication, network association and synchronization, data logging and reporting, asset tracking, and automated flight state detection.
    Type: Application
    Filed: March 3, 2022
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Rahul Khanna, Yi Qian, Greeshma Pisharody, Raju Arvind, Jiejie Wang, Laura M. Rumbel, Christopher R. Carlson, Jennifer M. Williams, Prince Adu Agyeman
  • Publication number: 20240129496
    Abstract: Methods, systems, and articles are described herein related to video coding. The method comprises receiving compressed image data of video frames including a block of image data of at least one of the frames. The method also comprises receiving first partition data to be used to decode the compressed image data and indicating a partition in the block. This method comprises detecting whether or not the block has an illegal block partition. Also, the method comprises generating second partition data to indicate the illegal block partition of the block is to be ignored. Further, the method includes decoding the block at least according to the second partition data.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventor: Tsung-Han Yang
  • Publication number: 20240128181
    Abstract: Embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Brandon C. Marin, Srinivas V. Pietambaram, Hiroki Tanaka, Haobo Chen
  • Publication number: 20240129503
    Abstract: Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
  • Publication number: 20240128138
    Abstract: Semiconductor packages and methods for forming semiconductor packages are disclosed. An example semiconductor package includes a substrate and a core. An insulator material is present over the core, and along a direction perpendicular to a first surface of the core, a portion of the insulator material is between the core and a first surface of the substrate. A via extends between the first surface of the core and a second surface of the core in the direction perpendicular to the first surface of the core. A bridge die is in a recess in the substrate. The bridge die is coupled with the via. An electronic component is coupled to an end of the via at a second surface of the substrate.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Robert L. Sankman, Rahul N. Manepalli, Robert Alan May, Srinivas Venkata Ramanuja Pietambaram, Bharat P. Penmecha
  • Publication number: 20240129058
    Abstract: For example, an apparatus may include a segment parser to parse scrambled data bits of a PPDU into a first plurality of data bits and a second plurality of data bits, the PPDU to be transmitted in an OFDM transmission over an aggregated bandwidth comprising a first channel in a first frequency band and a second channel in a second frequency band; a first baseband processing block to encode and modulate the first plurality of data bits according to a first OFDM MCS for transmission over the first channel in the first frequency band; and a second baseband block to encode and modulate the second plurality of data bits according to a second OFDM MCS for transmission over the second channel in the second frequency band.
    Type: Application
    Filed: October 17, 2023
    Publication date: April 18, 2024
    Applicant: INTEL CORPORATION
    Inventors: Alexander W. Min, Thomas J. Kenney, Laurent Cariou, Shahrnaz Azizi, Xiaogang Chen, Robert J. Stacey, Qinghua Li
  • Publication number: 20240126357
    Abstract: Embodiments provided a blend circuit configured to perform a power optimized blend using blend circuitry configured such that the dynamic power consumed during the blending of two input color values is reduced when the input colors are close in value. When blending two identical input color values, a portion of the blend circuit can be bypassed and clock and/or data gated.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventor: Theo Drane
  • Publication number: 20240128340
    Abstract: Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Patrick Morrow, Glenn A. Glass, Anand S. Murthy, Rishabh Mehandru
  • Publication number: 20240126695
    Abstract: Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Yao Zu DONG, Kun TIAN, Fengguang WU, Jingqi LIU
  • Publication number: 20240126519
    Abstract: Described herein is a technique and associated tool for automatic program code optimization for high-level synthesis. The tool can efficiently explore multiple representations of an input program using e-graph rewriting and determine an HLS-efficient representation of program code for input into high-level synthesis tools.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Jianyi Cheng, Samuel Coward, Lorenzo Chelini, Rafael Barbalho, Theo Drane
  • Publication number: 20240126615
    Abstract: Embodiments for orchestrating execution of workloads on a distributed computing infrastructure are disclosed herein. In one example, environment data is received for compute devices in a distributed computing infrastructure. The environment data is indicative of an operating environment of the respective compute devices and a physical environment of the respective locations of the compute devices. Future operating conditions of the compute devices are predicted based on the environment data, and workloads are orchestrated for execution on the distributed computing infrastructure based on the predicted future operating conditions.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Sundar Nadathur, Akhilesh Thyagaturu, Jonathan L. Kyle, Scott M. Baker, Woojoong Kim
  • Publication number: 20240127031
    Abstract: A graph neural network (GNN) model is used in a scheduling process for compiling a deep neural network (DNN). The DNN, and parameter options for scheduling the DNN, are represented as a graph, and the GNN predicts a set of parameters that is expected to have a low cost. Using the GNN-based model, a compiler can produce a schedule for compiling the DNN in a relatively short and predictable amount of time, even for DNNs with many layers and/or many parameter options. For example, the GNN-based model reduces the overhead of exploring every parameter combination and does not exclude combinations from consideration like prior heuristic-based approaches.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Hamza Yous, Ian Hunter, Alessandro Palla
  • Publication number: 20240126691
    Abstract: Technologies for cryptographic separation of MMIO operations with an accelerator device include a computing device having a processor and an accelerator. The processor establishes a trusted execution environment. The accelerator determines, based on a target memory address, a first memory address range associated with the memory-mapped I/O transaction, generates a second authentication tag using a first cryptographic key from a set of cryptographic keys, wherein the first key is uniquely associated with the first memory address range. An accelerator validator determines whether the first authentication tag matches the second authentication tag, and a memory mapper commits the memory-mapped I/O transaction in response to a determination that the first authentication tag matches the second authentication tag. Other embodiments are described and claimed.
    Type: Application
    Filed: September 7, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Luis S. Kida, Reshma Lal, Soham Jayesh Desai
  • Publication number: 20240127408
    Abstract: Embodiments are generally directed to an adaptive deformable kernel prediction network for image de-noising. An embodiment of a method for de-noising an image by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel values for the pixel; generating a plurality of offsets for the pixel respectively corresponding to the plurality of kernel values, each of the plurality of offsets to indicate a deviation from a pixel position of the pixel; determining a plurality of deviated pixel positions based on the pixel position of the pixel and the plurality of offsets; and filtering the pixel with the convolutional kernel and pixel values of the plurality of deviated pixel positions to obtain a de-noised pixel.
    Type: Application
    Filed: November 20, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Anbang Yao, Ming Lu, Yikai Wang, Xiaoming Chen, Junjie Huang, Tao Lv, Yuanke Luo, Yi Yang, Feng Chen, Zhiming Wang, Zhiqiao Zheng, Shandong Wang
  • Publication number: 20240127414
    Abstract: Systems and methods for tone mapping of high dynamic range (HDR) images for high-quality deep learning based processing are disclosed. In one embodiment, a graphics processor includes a media pipeline to generate media requests for processing images and an execution unit to receive media requests from the media pipeline. The execution unit is configured to compute an auto-exposure scale for an image to effectively tone map the image, to scale the image with the computed auto-exposure scale, and to apply a tone mapping operator including a log function to the image and scaling the log function to generate a tone mapped image.
    Type: Application
    Filed: October 20, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventor: Attila Tamas Afra
  • Publication number: 20240128247
    Abstract: Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Gang Duan, Jeremy Ecton, Suddhasattwa Nad, Hiroki Tanaka