Patents Assigned to Intel Corporation
  • Publication number: 20190158209
    Abstract: There is disclosed in one example a fiberoptic communication circuit for wavelength division multiplexing (WDM) communication, including: an incoming waveguide to receive an incoming WDM laser pulse; an intermediate slab including a demultiplexer circuit to isolate n discrete modes from the incoming WDM laser pulse; n outgoing waveguides to receive the n discrete modes, the outgoing waveguides including fully-etched rib-to-channel waveguides; and an array of n photodetectors to detect the n discrete modes.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Wenhua Lin, Judson Douglas Ryckman, Ling Liao, Kelly Christopher Magruder, Harel Frish, Assia Barkai, Han-din Liu, Yimin Kang
  • Publication number: 20190158958
    Abstract: A wearable device for binaural audio is described. The wearable device includes a feedback mechanism, a microphone, an always on binaural recorder (AOBR), and a processor. The AOBR is to capture ambient noise via the microphone and interpret the ambient noise. An alert is issued by the processor to the feedback mechanism based on a notification detected via the microphone in the ambient noise.
    Type: Application
    Filed: January 18, 2019
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Rajesh Poornachandran, David Gottardo, Swarnendu Kar, Saurabh Dadu, Mark MacDonald
  • Publication number: 20190155575
    Abstract: An integrated circuit with specialized processing blocks are provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.
    Type: Application
    Filed: November 20, 2017
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Martin Langhammer, Dongdong Chen
  • Publication number: 20190154739
    Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
    Type: Application
    Filed: January 22, 2019
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Gerhard SCHROM, J. Keith HODGSON, Alexander LYAKHOV, Chiu Keung TANG, Narayanan RAGHURAMAN, Narayanan NATARAJAN
  • Publication number: 20190156533
    Abstract: Embodiments are generally directed to minimum or maximum sample indexing in a control surface. An embodiment of an apparatus includes a graphics processor including: a sampler to sample a value; one or more of a color unit or a depth unit; and at least one minimum or maximum sample (min/max) setter subunit for the color unit or depth unit, the min/max setter subunit to receive a new sample value, store the sample value in a resource containing a plurality of sample values, and update indexing include index values for one or more of a minimum sample value and a maximum sample value in the plurality of sample values of the resource.
    Type: Application
    Filed: November 20, 2017
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventor: Devan Burke
  • Publication number: 20190158024
    Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.
    Type: Application
    Filed: December 31, 2018
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Khang Choong YONG, Raymond CHONG, Ramaswamy PARTHASARATHY, Stephen HALL, Chin Lee KUAN
  • Publication number: 20190155928
    Abstract: A semiconductor package apparatus may include technology to determine difference information between a parent node of a hierarchical data structure and a child node of the parent node, and store the difference information with the child node of the hierarchical data structure. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: November 22, 2017
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventor: Gilad Baruch
  • Publication number: 20190158716
    Abstract: A method, system, and article is directed to geolocation and attitude correction for mobile rolling shutter cameras.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Gregoire Kerr, Zoran Zivkovic
  • Publication number: 20190156499
    Abstract: Techniques are provided for detection of humans in images that include depth information. A methodology embodying the techniques includes segmenting an image into multiple windows and estimating the distance to a subject in each window based on depth pixel values in that window, and filtering to reject windows with sizes that are outside of a desired window size range. The desired window size range is based on the estimated subject distance and the focal length of the depth camera that produced the image. The method further includes generating classifier features for each remaining windows (post-filtering) for use by a cascade classifier. The cascade classifier creates candidate windows for further consideration based on a preliminary detection of a human in any of the remaining windows. The method further includes merging neighboring candidate windows and executing a linear classifier on the merged candidate windows to verify the detection of a human.
    Type: Application
    Filed: May 19, 2016
    Publication date: May 23, 2019
    Applicant: INTEL CORPORATION
    Inventors: HAIBING REN, YIMIN ZHANG, FEI DUAN
  • Publication number: 20190155780
    Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Tsu-Chien HSUEH, Ganesh BALAMURUGAN, Bryan K. Casper
  • Publication number: 20190159256
    Abstract: An apparatus of a Fifth Generation NodeB (gNB) to operate in a License Assisted Access (LAA) system configures a transmission initiation time interval contention window size (CWS) of N number of subframes between Category 4 Listen Before Talk (LBT) uplink (UL) transmissions by a user equipment (UE) operating in the LAA system, and a memory to store a value of N which can have a value 6 or greater or 10 or greater. An apparatus of a UE to operate in an LAA system decodes a configuration from the gNB of a transmission initiation time interval contention CWS of N number of subframes between Category 4 LBT UL transmissions in the LAA system. The CWS is increased to a next higher value when an UL grant or an autonomous UL (AUL) downlink feedback indicator (DFI) is not received before the expiration of a timer.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Salvatore Talarico, Jeongho Jeon, Wenting Chang, Huaning Niu
  • Publication number: 20190155574
    Abstract: An integrated circuit with specialized processing blocks is provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.
    Type: Application
    Filed: September 27, 2018
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Martin Langhammer, Dongdong Chen, Kevin Hurd
  • Publication number: 20190157205
    Abstract: A microelectronic structure includes a substrate having a first surface and a cavity extending into the substrate from the substrate first surface, a first microelectronic device and a second microelectronic device attached to the substrate first surface, and a bridge disposed within the substrate cavity and attached to the first microelectronic device and to the second microelectronic device. The bridge includes a plurality conductive vias extending from a first surface to an opposing second surface of the bridge, wherein the conductive vias are electrically coupled to deliver electrical signals from the substrate to the first microelectronic device and the second microelectronic device. The bridge further creates at least one electrical signal connection between the first microelectronic device and the second microelectronic device.
    Type: Application
    Filed: January 22, 2019
    Publication date: May 23, 2019
    Applicant: INTEL CORPORATION
    Inventors: Nitin A. Deshpande, Omkar G. Karhade
  • Publication number: 20190155239
    Abstract: In one embodiment, an apparatus comprises a fabric controller of a first computing node. The fabric controller is to receive, from a second computing node via a network fabric that couples the first computing node to the second computing node, a request to execute a kernel on a field-programmable gate array (FPGA) of the first computing node; instruct the FPGA to execute the kernel; and send a result of the execution of the kernel to the second computing node via the network fabric.
    Type: Application
    Filed: June 30, 2016
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Nicolas A. Salhuana, Karthik Kumar, Thomas Willhalm, Francesc Guim Bernat, Narayan Ranganathan
  • Publication number: 20190158096
    Abstract: A method includes detecting an open in a first IO element of a first bank of IOs and not in a second bank of IOs. The first and second banks of IOs are in a channel of a first die. The method includes shifting a first connection between the first IO element and a first core fabric of the first die to second connection between a second IO element and the first core fabric. The second IO element is in the first bank of IOs. The method includes shifting a third connection between a third IO element and a second core fabric of a second die to fourth connection between a fourth IO element and the second core fabric. The third and fourth IO elements are in a third bank of IOs of the second die. The method includes not shifting connections in the second and fourth banks of IOs.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Lai Guan Tang, Hup Chin Teh, Kiun Kiet Jong
  • Publication number: 20190157310
    Abstract: Techniques are disclosed for backside contact resistance reduction for semiconductor devices with metallization on both sides (MOBS). In some embodiments, the techniques described herein provide methods to recover low contact resistance that would otherwise be present with making backside contacts, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some embodiments, the techniques include adding an epitaxial deposition of very highly doped crystalline semiconductor material in backside contact trenches to provide enhanced ohmic contact properties. In some cases, a backside source/drain (S/D) etch-stop layer may be formed below the replacement S/D regions of the one or more transistors formed on the transfer wafer (during frontside processing), such that when backside contact trenches are being formed, the backside S/D etch-stop layer may help stop the backside contact etch process before consuming a portion or all of the S/D material.
    Type: Application
    Filed: July 1, 2016
    Publication date: May 23, 2019
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, ANAND S. MURTHY, KARTHIK JAMBUNATHAN, CHANDRA S. MOHAPATRA, MAURO J. KOBRINSKY, PATRICK MORROW
  • Publication number: 20190157598
    Abstract: Embodiments related to emissive devices for displays are discussed. Some embodiments include light emitting diodes including an electron transport layer core having a tube shape with an inner and an outer sidewall, an emission layer on the inner and outer sidewalls, and a hole transport layer on the emission layer, displays and systems including such light emitting diodes, and methods for fabricating them. Other embodiments include emissive laser devices having an emission layer between a hole transport layer and an electron transport layer and first and second metasurface mirrors adjacent to the hole transport layer and the electron transport layer, respectively, displays and systems including such emissive laser devices, and methods for fabricating them.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Khaled AHMED, Ali KHAKIFIROOZ, Richmond HICKS
  • Publication number: 20190157210
    Abstract: Disclosed herein are package substrates with integrated components, as well as related apparatuses and methods. For example, in some embodiments, an integrated circuit (IC) package, may include: a substrate having opposing first and second faces, an insulating material disposed between the first and second faces, and a thin film transistor (TFT) disposed between the first and second faces, wherein a conductive portion of the TFT is disposed on a layer of the insulating material, and the conductive portion of the TFT is a gate, source, or drain of the TFT; and a die coupled to the first face of the substrate.
    Type: Application
    Filed: May 25, 2016
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Robert Alan May, Kristof Kuwawi Darmawikarta, Sri Ranga Sai Boyapati
  • Publication number: 20190157253
    Abstract: A circuit system includes an integrated circuit package, first and second memory modules, and a base circuit board. The integrated circuit package houses a main integrated circuit die. The first memory module has a first circuit board and first memory integrated circuit dies coupled to the first circuit board. The second memory module has a second circuit board and second memory integrated circuit dies coupled to the second circuit board. The base circuit board is coupled to the integrated circuit package and to the first and second memory modules. The base circuit board includes conductors that couple the integrated circuit package to the first and second memory modules. The second memory module has a reverse orientation on the base circuit board relative to the first memory module such that the second memory integrated circuit dies face away from the first memory integrated circuit dies.
    Type: Application
    Filed: January 22, 2019
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: David Browning, John Eley
  • Publication number: 20190156145
    Abstract: Techniques related to feature detection and matching fisheye images are discussed. Such techniques include determining a geometric constraint for the feature matching using match results from a first image based feature matching and generating resultant matches based on applying the geometric constraint and a second image based feature matching that applies a looser image based feature matching requirement than the image based feature matching.
    Type: Application
    Filed: January 29, 2019
    Publication date: May 23, 2019
    Applicant: Intel Corporation
    Inventors: Niloufar Pourian, Oscar Nestares