Abstract: Composite IC die package including IC die on both a first and second side of an interposer. The backside of first IC die are attached, for example through a direct bond, to a first side of the interposer. Redistribution layer (RDL) metal features are then fabricated, for example with semi-additive processes (SAP), to form interconnects to the frontside of the first die that terminate at first-level interconnect (FLI) interfaces. The frontside of second IC are attached, for example through a direct bond, to a second side of the interposer. Through vias in the interposer couple the second IC die to the first IC die and/or the FLI interfaces. Through vias of the interposer may be coupled to pillars on the first side of the interposer with the first IC die positioned between the pillars, facilitating power delivery to the second IC die.

Abstract: The disclosure relates to fractional-bit network quantization and deployment of CNN models. An AI accelerator, including: an input buffer configured to buffer an input image; a weight buffer configured to buffer convolutional kernel indexes for a convolutional layer of a CNN model; a kernel pattern buffer configured to buffer a 1-bit convolutional kernel subset for the convolutional layer of the CNN model, wherein the 1-bit convolutional kernel subset includes 2? 1-bit convolutional kernels with a size of K×K; a PE array including one or more PE nodes, each of which is configured to generate convolutional results of an image region of the input image and 1-bit convolutional kernels corresponding to the convolutional kernel indexes in the 1-bit convolutional kernel subset; and an output buffer configured to buffer convolutional results of respective image regions of the input image and the 1-bit convolutional kernels corresponding to the convolutional kernel indexes.

Abstract: The application relates to apparatuses used in a wireless local area network. An apparatus used in an access point (AP) multi-link device (MLD) or a non-AP MLD, wherein the apparatus includes processor circuitry configured to cause the AP MLD to do cross-link availability information exchange with a non-AP MLD by using an Availability Window element to indicate availability information of an mmWave link or cause the non-AP MLD to do cross-link availability information exchange with an AP MLD by using the Availability Window element to indicate the availability information of the mmWave link.

Abstract: An apparatus is provided which comprises: an integrated circuit logic device, an integrated circuit power device conductively coupled with a first surface of the integrated circuit logic device, wherein the integrated circuit power device extends laterally beyond a side of the integrated circuit logic device, one or more vias adjacent the side of the integrated circuit logic device extending from contact with the integrated circuit power device to level with a second surface of the integrated circuit logic device opposite the first surface of the integrated circuit logic device, and conductive contacts on the second surface of the integrated circuit logic device. Other embodiments are also disclosed and claimed.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, an assembly may include a photonic integrated circuit (PIC) having a surface; a first layer, on the surface of the PIC, the first layer including an electrical integrated circuit (EIC) surrounded by a first material; and a second layer, on the first layer, the second layer including a second material, a microlens, and an alignment feature. In some embodiments, the alignment feature of the second layer is a first alignment feature, and the photonic assembly may further include a medium for transmitting optical signals, on the second layer, the medium having a second alignment feature aligned with the first alignment feature, and an optical fiber arranged to receive an optical signal from the microlens.

Abstract: An apparatus to facilitate a block normalized adder (BNA) with four-deep systolic parameter support is disclosed. The apparatus includes matrix acceleration hardware comprising: data processing units, wherein the respective data processing units comprise normalization adding circuitry including: multiplier circuits; shifters to receive multiplier outputs from the multiplier circuits and apply block normalization; and an accumulator circuit to accumulate shifter outputs from the shifters with an intermediate value, wherein the accumulator circuit to generate an accumulator output in a high precision and unnormalized format to pass to a next stage of the matrix acceleration hardware; a bypass data structure to cause a global source operand to bypass the data processing units; and an adder circuit to add the accumulator output from a final data processing unit of the data processing units with the global source operand and apply round to nearest even to generate a final output.

Abstract: An apparatus for speech model with personalization via ambient context harvesting, is described herein. The apparatus includes a microphone, context harvesting module, confidence module, and training module. The context harvesting module is to determine a context associated with the captured audio signals. A confidence module is to determine a confidence of the context as applied to the audio signals. A training module is to train a neural network in response to the confidence being above a predetermined threshold.

Abstract: Logic to generate a 320 megahertz (MHz) extremely high throughput (EHT) physical layer protocol data unit (PPDU) comprising a multi-resource unit (MRU). Logic to generation of a non-orthogonal frequency division multiple access (non-OFDMA) 320 MHz EHT PPDU, wherein the MRU comprises a 240 MHz multi- MRU, the 240 MHz MRU comprising at least two contiguous 996 tone resource units (RUs). Logic to generation of an OFDMA 320 MHz EHT PPDU, wherein the MRU comprises at least one 996 tone RU and one 484 tone RU. Logic to cause the transmission of the 320 MHz EHT PPDU. And logic to receive and decode the 320 MHz EHT PPDU.

Abstract: This disclosure describes systems, methods, and devices related to measurement gaps. A user equipment (UE) device may identify a configuration message, received from a 5G network device prior to switching from an active bandwidth part (BWP), for a pre-configured measurement gap during which the UE device is to perform an both gapless and gap-based frequency measurements, the configuration message indicating that the pre-configured measurement gap requires activation; identify an activation of the pre-configured measurement gap; and measure a reference signal during the pre-configured measurement gap.

Abstract: Integrated circuit (IC) devices having direct-bonded dies. An IC device may include an IC substrate with a dielectric layer and a fluorophore between sidewalls of the dielectric layer. The fluorophore may be a quantum dot. The IC device may include a second IC substrate with a second fluorophore, the second IC substrate hybrid bonded with the first IC substrate fluorophore, and the first and second fluorophores vertically aligned. The first fluorophore may absorb light at a first wavelength and emit light at a second wavelength, and the second fluorophore may absorb light at the second wavelength and emit light at a third wavelength. The light at a third wavelength may be detected and used to align the first and second IC substrates, e.g., before direct bonding.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to train a teacher network and a student network simultaneously without a pre-trained teacher model.

Abstract: An example apparatus for mining multi-scale hard examples includes a convolutional neural network to receive a mini-batch of sample candidates and generate basic feature maps. The apparatus also includes a feature extractor and combiner to generate concatenated feature maps based on the basic feature maps and extract the concatenated feature maps for each of a plurality of received candidate boxes. The apparatus further includes a sample scorer and miner to score the candidate samples with multi-task loss scores and select candidate samples with multi-task loss scores exceeding a threshold score.

Abstract: Technologies for protocol execution include a command device to broadcast a protocol message to a plurality of computing devices and receive an aggregated status message from an aggregation system. The aggregated status message identifies a success or failure of execution of instructions corresponding with the protocol message by the plurality of computing devices such that each computing device of the plurality of computing devices that failed is uniquely identified and the success of remaining computing devices is aggregated into a single success identifier.

Abstract: Methods, apparatus, systems, and articles of manufacture utilizing conjugated polymers in integrated circuit packages with glass substrates are disclosed. A disclosed integrated circuit (IC) package includes: a glass substrate; a first electrode; an organic material; and a second electrode. The first electrode is between the glass substrate and the organic material. The organic material includes at least one of a conjugated polymer or a metal-organic supramolecule. The organic material is between the first electrode and the second electrode.

Abstract: The present disclosure is generally related to artificial intelligence (AI) and/or machine learning (ML) workflows including ML entity lifecycle management and reporting mechanisms for reporting the validation performance of an ML entity. An ML training (MLT) function trains an ML model using a training dataset and may validate the ML model using a validation dataset. An MLT report is generated, which includes an attribute indicating the performance of the ML model when performing on training data. To support the ML model validation performance reporting, an attribute is defined in the MLT report to indicate the performance of the ML model when performing on the validation data. The attribute may be a new attribute or an extension/enhancement of an existing attribute in the MLT training report.

Abstract: In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.

Abstract: Examples described herein relate to a network interface device comprising an interface to memory and circuitry. In some examples, the circuitry is to: determine a number of data units stored in a page in the memory and based on no data unit stored in a page of memory, permit storage of a data unit in the page in the memory.

Abstract: The technology disclosed herein includes a memory to store a plurality of pages, a page of the plurality of pages configured as one of a trusted execution environment (TEE) configuration and a non-TEE configuration, and a memory controller to attempt to access the page using a memory address and the TEE configuration and generate a first error correcting code (ECC); and when data for the first ECC is at least one of correct and correctable by ECC for the attempt to access the page using the TEE configuration, attempt to access the page using the memory address and the non-TEE configuration and generate a second ECC, and when data the second ECC is at least one of correct and correctable by ECC for the attempt to access the page using the non-TEE configuration, store the memory address as an unknown cacheline address.

Abstract: Bits are stored in cells having two transistors between two parallel bitlines. In a memory array, first and second transistor channels in a bit cell are parallel and offset and coupled to first and second bitlines, respectively, which are also parallel and offset. Adjacent bit cells share corresponding transistor channel structures. The transistor channels may be orthogonal to the bitlines. The memory array may be on an integrated circuit (IC) die, which may be coupled to a power supply in an IC system. In an IC system, the memory array may be coupled to a power supply and a cooling structure.

Abstract: An integrated circuit structure includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes a first interconnect feature and a second interconnect feature. The second interconnect layer includes a third interconnect feature, a fourth interconnect feature, and a fifth interconnection feature. The third interconnect feature extends from an upper surface of the first interconnect feature to an upper surface of the second interconnect layer. In an example, the fourth interconnect feature extends from an upper surface of the second interconnect feature to below the upper surface of the second interconnect layer, and the fifth interconnect feature extends from an upper surface of the fourth interconnect feature to the upper surface of the second interconnect layer. Thus, a double-decked vertical stack of interconnect features is formed using the fourth interconnect feature within the second interconnect layer.