Abstract: This disclosure describes systems, methods, and devices related to traffic indications for multi-link devices (MLDs). A device may generate a first traffic indication map (TIM) with a first bitmap including a first indication that traffic is to be sent by a first access point (AP) device of the MLD to a first non-AP device of a second MLD using a first communication link The device may generate a second TIM with a second bitmap including a second indication that no traffic is to be sent by a second AP device of the MLD to a second non-AP device of the second MLD using a second communication link The device may send, using the first communication link, the beacon, the beacon including the first TIM and the second TIM. The device may send, using the first communication link, a data frame to the first non-AP device of the second MLD.

Abstract: The disclosure is directed to apparatus and methods for manufacturing including a collaborative robot, a camera operatively coupled to the collaborative robot, a memory coupled to the collaborative robot, and processing circuitry coupled to the memory, the processing circuitry configured to receive image data of at least one component intended for a printed circuit board (PCB), the image data collected by the camera operatively coupled to the collaborative robot, determine, based on the image data, a coordinate location for the component, and secure the component to the PCB using an end effector of the collaborative robot based on the received image data. In one embodiment, the collaborative robot is configured to operate alongside a human, the collaborative robot in combination with the camera configured to manufacture a computer system with the PCB.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: An initializer for circle distribution on a 2D surface using a polar coordinate system for image compression, video compression, motion detection, and posture detection. The initializer can also be used for sphere distribution in a 3D shape. The initializer uses a mixed deterministic and iterative/stochastic approach. Using the polar coordinate system for initialization enables coverage of the user space, and after parameters are initialized, the method transitions to a cartesian coordinate system. Methods for using the polar system in CPU units by applying an XNOR/AND architecture for neural network model compression are also described. The neural network includes a perceptron for supervised learning of binary classifiers. The unit responsible for multiplication in a MAC architecture can be replaced with a non-linear expressive function. Thus, a neural network having a non-linear expressive perceptron (quadtron) is described for solving circle distribution and other problems.

Abstract: This disclosure describes systems, methods, and devices related to aligned channel access. A device may perform a first backoff countdown on a first link associated with a first station device (STA) of the device, wherein the device is a multi-link device (MLD). The device may detect a second backoff countdown associated with a second STA of the MLD after the first backoff countdown reaches zero. The device may determine to hold the first backoff countdown at zero based on the value of the second backoff countdown. The device may transmit in synchronization on the first link and on the second link from the first STA and the second STA respectively based on holding the first backoff countdown at zero.

Abstract: This disclosure describes systems, methods, and devices related to adding or removing communication access points (APs) affiliated with an associated AP multi-link device (AP-MLD). A non-AP-MLD may identify a communication link between the non-AP-MLD and an AP-MLD, the communication link previously used by the non-AP-MLD; encode a request frame comprising a multi-link reconfiguration element indicative of a request to add or remove the communication link; cause the non-AP-MLD to transmit the request frame to the AP-MLD; and identify a response frame received from the AP-MLD, the response frame comprising the multi-link reconfiguration element and indicating whether the communication link was accepted or rejected to be added or removed.

Abstract: This disclosure describes systems, methods, and devices related to WLAN sensing sounding. A device may identify a sensing null data packet (NDP) request frame received from a second device, the sensing NDP request frame associated with performing a wireless local area network channel sounding procedure; identify transmit parameters included in a transmit control field of the sensing NDP request frame; generate an NDP frame using the transmit parameters; and send, in response to the sensing NDP request frame, the NDP frame to the second device.

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.

Abstract: Described herein is a generalized optimal reduction scheme for reducing an array modulo a constant. The constant modulo operation calculates a result for array of bits xi, width n modulo an odd positive integer constant d, (e.g., x[n:0] mod d). Circuitry to perform such operation can be configured to compress the array of bits xi, width n into an array of bits yi width m. The techniques described herein enable the design of optimal circuitry via iterative exploration of all potential reduction strategies that are available given the input constraints.

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

Abstract: Embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. One embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. The graphics core includes execution resources to execute an instruction via a plurality of hardware threads and barrier circuitry to synchronize execution of the plurality of hardware threads, wherein the barrier circuitry is configured to provide a plurality of re-usable named barriers.

Abstract: This disclosure describes systems, methods, and devices related to bond strength measurement. A device may comprise a first portion of a plate connected to a movement mechanism, a second portion of the plate comprising a sticky probe and a third portion of the plate comprising a mirror with a reflective side pointing outwards. The device may further comprise an optical fiber sensor assembly comprising an optical fiber bundle for sending light through a first optical fiber and receiving light reflected from the mirror through a second optical fiber.

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

Abstract: The techniques described in the detailed description above enable the manufacturing of circuits with increased performance and efficiency when performing division by a constant number. One embodiment provides circuitry including an input circuit to receive an input value including a plurality of bits, a logarithmic tree coupled with the input circuit, the logarithmic tree configured to compute an array of values based on a plurality of multi-bit groups of the plurality of bits of the input value, each value in the array of values includes a modulus of a corresponding multi-bit group with respect to the constant, a binary array adder to compute a quotient of the division operation based on the array of values, the input value, and the constant, and an output circuit to output the quotient.

Abstract: Described herein is a technique for automatic program code optimization for high-level synthesis. One embodiment provides a method comprising receiving input including first program code in a high-level language; translating the first program code into an intermediate language; constructing an equality graph (e-graph) from the intermediate language; interleaving control-flow, data path, and gate-level transformations to explore equivalent hardware designs represented by the e-graph; selecting a hardware design based on a cost function; extracting a representation of a selected hardware design in the intermediate language; generating second program code in the high-level language; and performing high-level synthesis using the second program code.

Abstract: A first computing system includes a data store with a sensitive dataset. The first computing system uses a feature extraction tool to perform a statistical analysis of the dataset to generate feature description data to describe a set of features within the dataset. A second computing system is coupled to the first computing system and does not have access to the dataset. The second computing system uses a data synthesizer to receive the feature description data and generate a synthetic dataset that models the dataset and includes the set of features. The second computing system trains a machine learning model with the synthetic data set and provides the trained machine learning model to the first computing system for use with data from the data store as an input.

Abstract: An apparatus comprising translator circuitry to receive a plurality of physical addresses of memory data, determine an offset associated with each of the physical page addresses and apply a tweak seed to each offset to generate a plurality of tweaks.

Abstract: The disclosure is directed to apparatus and methods for detection of out of position (OOP) components in a carrier tape forming machine. An apparatus includes cross track sensors coupled to the bus interface circuitry, the cross track sensors configured to detect OOP components prior to overlaying the components on the carrier tape with cover tape, optical sensors to detect the OOP components on the carrier tape after overlaying with cover tape and prior to sealing and to detect reflections from OOP components seated on the carrier tape, an amplifier coupled to the optical sensors to amplify signals generated by the optical sensors and set a range for determining whether the components are OOP, and relays to receive indications of detected OOP components, and a controller coupled to the relays to stop the carrier tape forming machine as a function of signals received by the relays.

Abstract: Embodiments described herein provide a technique to facilitate the broadcast or multicast of asynchronous loads to shared local memory of a plurality of graphics cores within a graphics core cluster. One embodiment provides a graphics processor including a cache memory a graphics core cluster coupled with the cache memory. The graphics core cluster includes a plurality of graphics cores. The plurality of graphics cores includes a graphics core configured to receive a designation as a producer graphics core for a multicast load, read data from the cache memory; and transmit the data read from the cache memory to a consumer graphics core of the plurality of graphics cores.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage elements to generate one or more compressed storage elements, the first compression to remove zero points of the one or more storage elements based on the sparsity map and perform a second compression of the one or more compressed storage elements, the second compression to store the one or more compressed storage elements contiguously in memory.