Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the Li cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

Abstract: In one embodiment, a crosspoint memory device is manufactured by forming a material stack and patterning the material stack to form a plurality of memory cells of the cross point memory device. Forming the material stack includes depositing a select device (SD) region material comprising chalcogenide, depositing a layer comprising carbon on the SD region material at a temperature below 40° C., depositing an ohmic contact layer on the layer comprising carbon, and depositing a phase change material (PM) region material comprising chalcogenide on the ohmic contact layer.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to reduce latency during viewport switching in immersive video. An example apparatus include at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to: obtain a first bitstream having a first encoded frame and a second encoded frame, the second encoded frame encoded at a higher resolution than the first encoded frame and having a coding dependency on the first encoded frame, rewrite the first bitstream into a second bitstream based on field of view information, the second bitstream including a third encoded frame indicative of a portion of the second encoded frame that corresponds to the field of view information and including the first encoded frame, and transmit the second bitstream to a client device for decoding and rendering the portion of the second encoded frame.

Abstract: For example, a Bluetooth (BT) device may be capable of configuring a BT link for communication between the BT device and a keyboard device. For example, the BT device may be configured to identify a keypress attribute of keypresses on the keyboard device. For example, the BT device may be configured to identify the keypress attribute based on transmissions from the keyboard device to the BT device over the BT link between the BT device and the keyboard device. For example, the BT device may configure a bandwidth (BW) allocation for the BT link, for example, based on the keypress attribute.

Abstract: Bandwidth part (BWP) switching for aperiodic sounding reference signal (SRS) transmissions is triggered via a downlink control information (DCI) format that does not include scheduling information. When a DCI format does not schedule a physical uplink shared channel (PUSCH) and does not include a channel state information (CSI) request, the UE may interpret one or more fields of the DCI format for the aperiodic SRS transmission.

Abstract: A system includes processing circuitry; and a memory device including instructions embodied thereon, wherein the instructions, which when executed by the processing circuitry, configure the processing circuitry to perform operations comprising: accessing input data, at an aggregator node, the input data including sensor data from a plurality of sensor nodes, each sensor data having a respective signature; validating the sensor data by using respective cryptographic hash functions on the sensor data and evaluating the respective result using the respective signature; performing an aggregation function on the sensor data to produce aggregate data; executing a hash function on the aggregate data to produce a hash value for the aggregate data; bundling the sensor data, respective signatures of the sensor data, aggregate data, and hash value for the aggregate data in a data structure; and exposing the data structure to subscriber nodes on the IoT network.

Abstract: Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure above a substrate. The interconnect structure may include an inter-level dielectric (ILD) layer and a separation layer above the ILD layer. A first conductor and a second conductor may be within the ILD layer. The first conductor may have a first physical configuration, and the second conductor may have a second physical configuration different from the first physical configuration. Other embodiments may be described and/or claimed.

Abstract: Techniques for automatic fusion of arithmetic in-flight instructions are described. An example apparatus comprises a buffer to store instructions to be issued to a functional unit for execution, and circuitry coupled to the buffer to combine two or more instructions from the buffer into a single combined instruction. Other examples are disclosed and claimed.

Abstract: An apparatus is described. The apparatus includes an accelerator having an interface to plug into an electronic system. The accelerator includes a field programmable gate array integrated circuit to perform acceleration, a general purpose processor integrated circuit to execute software related to the acceleration and controller circuitry to dynamically change, without rebooting the general purpose processor integrated circuit, allocation of the accelerator's power budget to the field programmable gate array integrated circuit and the general purpose processor integrated circuit.

Abstract: Devices and methods power configurations of radio communication devices. A device may include a memory storing communication activity data comprising information indicating a plurality of attributes with respect to communication activities over a radio connection between a user equipment (UE) and a base station (BS). The device may further include a processor that is configured to provide the communication activity data to a trained machine learning model configured to predict a communication activity for the radio connection between the UE and the BS and encode a power preference information for transmission to the BS based on the predicted communication activity.

Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.

Abstract: An IC device includes a metal layer that includes staggered metal lines. The metal lines are in two or more levels along a direction. There may be one or more metal lines in each level. At least some of the metal lines are aligned along the direction so that widths of the metal lines may be maximized for a given total width of the metal layer. The alignment of the metal lines may be achieved through DSA of a diblock copolymer. The metal layer may be connected to vias in two or more levels. The vias may be also connected to another metal layer or a semiconductor device in a FEOL section of the IC device. A via and the metal line connected to the via may be formed through a same recess and deposition process to eliminate interface between the via and metal line.

Abstract: Embodiments include semiconductor devices. In an embodiment, a semiconductor device comprises a first non-planar transistor over a substrate and a second non-planar transistor over the substrate and parallel to the first non-planar transistor. In an embodiment, a gate structure is over the first non-planar transistor and the second non-planar transistor. In an embodiment, a power rail is between the first non-planar transistor and the second non-planar transistor. In an embodiment, a top surface of the power rail is below a top surface of a gate structure.

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, ferroelectric three-dimensional (3D) memory architectures. Other embodiments may be disclosed or claimed.

Abstract: Systems, apparatuses and methods may provide for technology that determines a power-off period associated with a non-volatile memory (NVM), sets a completion time of a write procedure corresponding to the NVM to a first value if the power-off period exceeds a threshold, and sets the completion time to a second value if the power-off period does not exceed the threshold, wherein the first value is greater than the second value.

Abstract: Embodiments herein relate to a three-transistor gain cell which is provided using a complementary field-effect transistor device to achieve scaling. The cell includes an n-type layer arranged above a p-type layer. In one implementation, two nMOS transistors are arranged above one pMOS transistor and a conductive path is provided to connect the gate of one of the nMOS transistors to a storage node in the p-type layer, where the storage node is coupled to a drain of the pMOS transistor. In another implementation, one nMOS transistor is arranged above two pMOS transistors and a conductive path is provided to connect the gate of one of the pMOS transistors to a storage node in the n-type layer, where the storage node is coupled to a source of the nMOS transistor.

Abstract: At least one instruction storage coupled with a fetch unit including sets of fetch circuitry each having a same plurality of pipeline stages. The sets of fetch circuitry perform fetch operations to fetch blocks of instructions from the at least one instruction storage. Stall circuitry, in response to an indication of a hazard for a given pipeline stage of a first set of fetch circuitry, retains a fetch operation for a first block of instructions at the given pipeline stage, and zero or more fetch operations for zero or more corresponding blocks of instructions at zero or more preceding pipeline stages of the first set of fetch circuitry, until the hazard has been removed. The stall circuitry advances a fetch operation for a second block of instructions from the given pipeline stage of a second set of fetch circuitry, during an initial cycle of the one or more cycles.

Abstract: Released fins for advanced integrated circuit structure fabrication are described. For example, an integrated circuit structure includes a sub-fin. A dielectric spacer material is on the sub-fin. A fin is on the dielectric spacer material. A void in the dielectric spacer material, the void vertically between the sub-fin and the fin.