Patents Assigned to Intel Corporation
  • Publication number: 20250149145
    Abstract: Physical therapy assistant-as-a-service (PTaaS) enables the automatic evaluation of a patient's performance of physical therapy exercises and the automatic provision of feedback to the patient on their exercise performance in real-time. A patient device can provide real-time patient exercise video to a PTaaS backend that performs checks prior to the patient performing the exercise (pre-checks) and checks during patient performance of the exercise (live checks). If any of the checks fail, the PTaaS can provide feedback to the patient, such as if the patient is in an incorrect starting pose or has a body part at an incorrect angle before beginning the exercise or if the patient's form or posture during performance of the exercise needs to be adjusted. The PTaaS can automatically generate exercise metrics, reports, and physical therapy insights that a physical therapy clinician can access from a clinician portal.
    Type: Application
    Filed: December 26, 2024
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventors: Sharon Talmor Marcovici, Rajasekaran Andiappan, Dan Horovitz, Amit Gur, Lakshman Krishnamurthy
  • Publication number: 20250147233
    Abstract: A wavelength multiplexing optical fiber transmitter, receiver, or transceiver where multiple emitters and/or photodetectors of different center wavelengths are coupled to a single optical fiber core terminus through multiple waveguides, which may be directly printed in free space. The optical assemblies described are suitable for optical data link applications, for example, to reduce a number of optical fibers needed for a given bandwidth or increase the bandwidth of a give number of optical fibers. Bidirectional fiber termination may also be implemented with an emitter and a photodetector pair coupled to a single optical fiber core terminus through multiple waveguides.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventors: Junyi Qiu, Mozhgan Mansuri, Beom-Taek Lee
  • Publication number: 20250150569
    Abstract: Embodiments are generally directed to selective packing of patches for immersive video. An embodiment of a processing system includes one or more processor cores; and a memory to store data for immersive video, the data including a plurality of patches for multiple projection directions. The system is to select the patches for packing, the selection of the patches based at least in part on which of the multiple projection directions is associated with each of the patches. The system is to encode the patches into one or more coded pictures according to the selection of the patches.
    Type: Application
    Filed: December 27, 2024
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventors: Eyal Ruhm, Jill Boyce, Asaf J. Shenberg
  • Publication number: 20250150968
    Abstract: This disclosure describes systems, methods, and devices related to control frames status. A device may receive a control frame from a station (STA) at a beginning of a transmission opportunity (TxOP) that includes availability and unavailability information. The device may acknowledge the availability and unavailability information of the STA based on fields within the control frame, including unavailability target start time field and unavailability duration field. The device may adjust a transmission schedule to avoid transmitting to the STA during its indicated unavailability period. The device may initiate a TxOP with an initial control frame that includes updated availability and unavailability information based on the control frame from the STA.
    Type: Application
    Filed: January 7, 2025
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventors: Laurent CARIOU, Thomas J. KENNEY
  • Publication number: 20250147762
    Abstract: Described herein is a graphics processor having processing resources with configurable thread and register configurations. Program code can configure a number of registers and accumulators that will be used by hardware threads during execution of the program code by the graphics processor. Processing resources within the graphics processor can be configured to assign different numbers of registers and accumulators to hardware threads based on the configuration requested by program code to be executed by the processing resource.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventors: Vasanth Ranganathan, Gang Chen, Supratim Pal, Jorge Eduardo Parra Osorio, Arthur Hunter, Boris Kuznetsov, Deepak N K, Siva Kumar Seemakurthi, James Valerio, Shubham Dinesh Chavan, Abhishek Kumar Singh, Samir Pandya, Sandeep Tippannanavar Niranjan, Alan Curtis, Jain Philip, Maltesh Kulkarni, Fangwen Fu, John Wiegert, Brent Schwartz
  • Publication number: 20250149459
    Abstract: An integrated circuit structure includes a plurality of interconnect lines and a plurality of dummy lines that are co-planar with the plurality of interconnect lines, where a ratio of line length to end-to-end spacing of the dummy lines varies inversely with a density of the interconnect lines within each of a plurality of regions. The regions are of approximately equal area within a rectangular grid array.
    Type: Application
    Filed: January 7, 2025
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventors: Burak Baylav, Dhananjay Bhawe
  • Publication number: 20250151355
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.
    Type: Application
    Filed: January 10, 2025
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventors: Hubert C. George, Ravi Pillarisetty, Jeanette M. Roberts, Nicole K. Thomas, James S. Clarke
  • Publication number: 20250149455
    Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a polyimide or a dielectric material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter through the material on the surface, a second diameter at the surface of the glass layer, and the first diameter is equal to the second diameter plus 1 micron or minus 1 micron; and a dielectric layer on the material at the surface of the glass layer, the dielectric layer including a conductive pathway electrically coupled to the via.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventors: Nicholas Haehn, Jeremy Ecton, Brandon C. Marin, Srinivas V. Pietambaram, Gang Duan
  • Publication number: 20250150361
    Abstract: Network apparatus, communicatively coupled to a provider of services, that includes gateway circuitry to receive application programming interface (API) request data from a computing device that indicates a requested service. The gateway circuitry is to (1) select, based upon the API request data, at least one of the services corresponding to the requested service, and (2) generate, based upon mapping of the API request data to the at least one of the services, corresponding request data specifically for use in invoking the at least one of the services. The gateway circuitry is to (1) generate the corresponding request data by performing at least one programmable transformation, (2) be used in association with at least one proxy-related operation, (3) register the services for use in association with service discovery, and (4) verify the API request data and an identity associated with the computing device.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Ned Smith, Kshitij Doshi, Alexander Bachmutsky, Suraj Prabhakaran
  • Publication number: 20250151318
    Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventors: Ritesh K. DAS, Kiran CHIKKADI, Ryan PEARCE
  • Publication number: 20250147822
    Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventors: Vadim Sukhomlinov, Kshitij A. Doshi
  • Publication number: 20250148089
    Abstract: Techniques for instruction prefix encoding for cryptographic computing capability data types are described. In an embodiment, an apparatus includes an instruction decoder to decode a first instruction including a first prefix; and cryptography circuitry to perform a cryptographic operation on data, the cryptographic operation to be based at least in part on the first prefix and a relative enumeration in a pointer to the data.
    Type: Application
    Filed: July 1, 2023
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventors: David M. Durham, Michael LeMay, Hans Goran Liljestrand
  • Publication number: 20250149421
    Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a positive-type photo-imageable dielectric (PID) material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter through the material on the surface, a second diameter at the surface of the glass layer, and the first diameter is equal to the second diameter plus 1 micron or minus 1 micron; and a dielectric layer on the material at the surface of the glass layer, the dielectric layer including a conductive pathway electrically coupled to the via.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 8, 2025
    Applicant: Intel Corporation
    Inventor: Jeremy Ecton
  • Patent number: 12293237
    Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
    Type: Grant
    Filed: December 19, 2023
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
  • Patent number: 12292608
    Abstract: Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the CMOS-based device, the interconnect structure including conductive interconnects and vias in a dielectric layer. A photonics waveguide is over the interconnect structure, the photonics waveguide including silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Nicole K. Thomas, Pratik Koirala, Nityan Nair, Paul B. Fischer
  • Patent number: 12293231
    Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Chenmin Sun, Yipeng Wang, Rahul R. Shah, Ren Wang, Sameh Gobriel, Hongjun Ni, Mrittika Ganguli, Edwin Verplanke
  • Patent number: 12293956
    Abstract: An apparatus is described. The apparatus includes a packaged semiconductor device. The packaged semiconductor device having an integrated heat spreader, wherein, a boiling enhancement structure exists on the integrated heat spreader without a block mass residing between the boiling enhancement structure and the integrated heat spreader. The boiling enhancement structure has a structured non-planar surface to promote bubble nucleation in an immersion cooling system.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Jin Yang, Jimmy Chuang, Xicai Jing, Yuan-Liang Li, Yuyang Xia, David Shia, Mohanraj Prabhugoud, Maria de la Luz Belmont, Oscar Farias Moguel, Andres Ramirez Macias, Javier Avalos Garcia, Jessica Gullbrand, Shaorong Zhou, Chia-Pin Chiu, Xiaojin Gu
  • Patent number: 12292840
    Abstract: An embodiment of an integrated circuit comprises circuitry to store memory protection information for a non-host memory in a memory protection cache, and perform one or more memory protection checks on a translated access request for the non-host memory based on the stored memory protection information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Utkarsh Y. Kakaiya, Rajesh Sankaran, David Koufaty
  • Patent number: 12292975
    Abstract: The disclosure generally relates method, system and apparatus to prevent denial of service (DOS) attacks on PCIe based computing devices. In an exemplary embodiment, an independent register is used in combination with a filter driver and additional logic to form an integrity check for power down instructions. An exemplary system includes a register circuitry corresponding to the IP device, the register circuitry having a designated storage bit to indicate an unlocked state of the register; a filter driver to receive a first power state transition request when the IP device is idle after a predetermined period, the power state transition request defining a timeout period; a controller to change the power state of the IP device to the unlock state; a decision logic to receive and authenticate a second power state transition request in response to validation of register circuitry being unlocked.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Sriram Ranganathan, Pannerkumar Rajagopal, Saravanakumar Ulaganathan, Siddhartha Selvaraj, Radhakrishna Pai
  • Patent number: 12292844
    Abstract: Methods, apparatus, systems, and articles of manufacture to transmit and/or receive data streams with a network interface controller are disclosed. An example apparatus includes a direct memory access engine to fetch a descriptor for a data transmission from system memory; and determine a time to generate an interrupt based on the descriptor; a scheduler to trigger the interrupt when the time occurs, the interrupt to cause an application to sample data and store the sampled data as a payload data structure into the system memory; the direct memory access engine to access the payload data structure from the system memory; and the scheduler to cause transmission of the payload data structure.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Kishore Kasichainula, Boon Leong Ong