Abstract: This disclosure describes systems, methods, and devices related to extremely high throughput (EHT) resource unit (RU) allocation. A device may utilize a tone plan to generate an EHT frame to be sent using an 80 MHz frequency band, wherein the tone plan comprises a plurality of null tones. The device may encode one or more resource units (RUs) for the EHT frame, wherein the one or more RUs comprise at least one of a 26-tone RU, a 52-tone RU, a 106-tone RU, a 242-tone RU, a 484-tone RU, or a 996-tone RU, wherein the 106-tone RU, the 242-tone RU, and the 484-tone RU comprise null tones located at least at subcarriers ±258, ±257, ±256, ±255, and ±254. The device may cause to send the EHT frame to a first station device using the 80 MHz frequency band.

Abstract: Described herein is a cloud-based gaming system in which graphics processing operations of a cloud-based game can be performed on a client device. Client-based graphics processing can be enabled in response to a determination that the client includes a graphics processor having a performance that exceeds a minimum threshold. When a game is remotely executed and streamed to a client, the client is configurable to provide network feedback that can be used to adjust execution and/or encoding for the game.

Abstract: A high-level understanding of the scene captured by a camera allows for the use of scene-level understanding in the processing of the captured image. A downscaled image of a captured scene is generated and used as a basis for artificial intelligence analysis before the full image of the captured scene is processed. The downscaled image is generated concurrently with the capturing of the raw image at the image sensor and before full image signal processor (ISP) processing. Neural networks and other AI algorithms can be applied directly to the downscaled image to perform high-level understanding using minimal resources. The processing of the full scale captured image can be adapted to specific scenarios based on the understanding rather than undergoing all-purpose processing. The high-level understanding is provided to the full image processing pipe for enhancements in image quality, video conferencing, face detection, and other user experiences.

Abstract: Techniques related to video coding with fast low-latency bitstream size control includes detecting outliers and determining a target bitstream size based on the outlier and reinforcement-learning.

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

Abstract: An apparatus for sensing a heart rate of a subject, including an eyewear frame and a heart rate sensing circuit. The sensing circuit includes first and second piezoelectric sensors configured to be in communication with the subject's skin and to generate first and second voltage signals in response to a periodic vibration in at least one artery of the subject, a first voltage amplifier configured to receive the first voltage signal and output a first amplified voltage signal related to the heart rate of the subject, a second voltage amplifier configured to receive the second voltage signal and output a second amplified voltage signal related to the heart rate of the subject, and a device configured to output a differential signal that is a representation of a difference between the first amplified voltage signal and the second amplified voltage signal that relates to the heart rate.

Abstract: A wearable device measures heart rate recovery of a user in a non-clinical setting. The wearable device comprises a heart rate detector configured to detect heart rate data of the user, an activity sensor configured to detect motion of the user, and a processor. The processor is configured to identify a start of an activity by the user using the motion detected by the activity sensor. Responsive to detecting the start of the activity, the processor monitors the motion detected by the activity sensor to identify an end of the activity. A regression analysis is performed on heart rate data detected by the heart rate detector during a period of time after the end of the activity, and the heart rate recovery of the user is determined using the regression analysis.

Abstract: Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.

Abstract: Embodiments are directed to tagless implicit integrity with multi-perspective pattern search for memory safety. An embodiment of an apparatus includes one or more processors comprising hardware circuitry to: access encrypted data stored in a memory hierarchy using a pointer; decrypt the encrypted data using a current version of a pointer tag of the pointer to yield first decrypted data; perform an entropy test on the first decrypted data; responsive to the entropy test failing to detect patterns in the first decrypted data, re-decrypt the encrypted data using one or more different versions of the pointer tag of the pointer to yield one or more other decrypted data; perform the entropy test on the one or more other decrypted versions; and responsive to the entropy test detecting the patterns in the one or more other decrypted data, signal an exception to the one or more processors with respect to the encrypted data.

Abstract: A groove alignment structure comprises an etch stop material and a substrate over the etch stop material. A set of grooves is along a first direction in a top surface of the substrate, and adhesive material is in a bottom of the set of grooves. Optical fibers are in the set of grooves over the adhesive material and a portion of the optical fibers extends above the substrate. A set of polymer guides is along the first direction on the top surface of the substrate interleaved with the set of grooves.

Abstract: Multi-port Media Control Channel (MAC) with flexible data-path width. A multi-port receive (RX) MAC block includes multiple RX ports and a plurality of RX circuit blocks comprising an RX MAC pipeline for performing MAC Layer operations on RX data received at the RX ports. The RX circuit blocks are connected with variable-width datapath segments, and the RX MAC block is configured to implement a multi-port arbitration scheme such as a TDM (Time-Division Multiplexed) scheme under which RX data received at a given RX port are forwarded over the variable-width datapath segments using datapath widths associated with that RX port. A multi-port transmit (TX) MAC block implementing a TX MAC pipeline comprising TX circuit blocks connected with variable-width datapath segments is also provided. The RX and TX MAC blocks include CRC modules configured to calculate CRC values on input data received over datapaths having different widths.

Abstract: Logic may implement observation layer intrusion detection systems (IDSs) to combine observations by intrusion detectors and/or other intrusion detection systems. Logic may monitor one or more control units at one or more observation layers of an in-vehicle network, each of the one or more control units to perform a vehicle function. Logic may combine observations of the one or more control units at the one or more observation layers. Logic may determine, based on a combination of the observations, that one or more of the observations represent an intrusion. Logic may determine, based at least on the observations, characteristics of an attack, and to pass the characteristics of the attack information to a forensic logging system to log the attack or pass the characteristics of the attack to a recovery system for informed selection of recovery procedures. Logic may dynamically adjust a threshold for detection of suspicious activity.

Abstract: Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

Abstract: Methods, apparatus, systems are disclosed for altering displayed content on a display device responsive to a user's proximity. In accord with an example, a computing system includes a display, a sensor to output a signal, machine readable instructions, and programmable circuitry to be programmed in accordance with the instructions to intermittingly determine a distance between the compute system and a person based on the signal, and cause a size of at least one object to be presented on the display to be adjusted based on the distance.

Abstract: Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.

Abstract: A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

Abstract: Systems, apparatuses and methods may provide for technology that detects a generic cloud service call in an application, wherein platform-specific parameters are unspecified in the cloud service call. The technology may also select a first cloud platform based on one or more performance constraints associated with the first cloud platform and automatically generate a first platform-specific service call based on the cloud service call and the first set of parameters. In one example, the technology also maps the cloud service call to the first platform-specific service call. Additionally, the technology may migrate the cloud service call to a second cloud platform without rewriting the generic cloud service call.

Abstract: The technology disclosed herein includes a memory to store a plurality of pages, a page of the plurality of pages configured as one of a trusted execution environment (TEE) configuration and a non-TEE configuration, and a memory controller to attempt to access the page using a memory address and the TEE configuration and generate a first error correcting code (ECC); and when data for the first ECC is at least one of correct and correctable by ECC for the attempt to access the page using the TEE configuration, attempt to access the page using the memory address and the non-TEE configuration and generate a second ECC, and when data the second ECC is at least one of correct and correctable by ECC for the attempt to access the page using the non-TEE configuration, store the memory address as an unknown cacheline address.

Abstract: An apparatus is provided, where the apparatus includes a plurality of components, wherein an individual component has a corresponding throttling priority of a plurality of throttling priorities. The apparatus further includes logic to selectively throttle one or more of the plurality of components. In an example, an order in which the one or more of the plurality of components are to be throttled may be based on the plurality of throttling priorities.

Abstract: In one example, a head mounted display system includes at least one memory; and at least one processor to execute instructions to: detect a first position and a first view direction of a head of a user based on sensor data generated by at least one of an accelerometer, at least one camera, or a gyroscope at a first point in time; determine a latency associated with a time to cause an image to be presented on the display; determine a predicted position and a predicted view direction of the head of the user at a second point in time based on the latency; render, prior to the second point in time, the image for presentation on the display based on the predicted position and the predicted view direction of the head of the user; and cause the display to present the rendered image.