Patents Assigned to Intel Corporation
  • Publication number: 20240089083
    Abstract: A method comprises receiving, from a remote device, a first encrypted data set encrypted using a first encryption scheme, performing a set of computations on the first encrypted data set to generate a first set of encrypted results, encrypting the first set of encrypted results using a second encryption scheme to generate a second set of encrypted results, sending the second set of encrypted results to the remote device, receiving, from the remote device, third set of encrypted results in which the first encryption scheme has been decrypted, and generating a set of decrypted results by applying a decryption algorithm to the third set of encrypted results to decrypt the second encryption scheme.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Kylan Race, Ernesto Zamora Ramos, Jeremy Bottleson, Jingyi Jin
  • Publication number: 20240090025
    Abstract: For example, an Access Point (AP) may be configured to transmit a frame including a prioritized-access enabled/disabled field to indicate whether a prioritized-access contention mechanism is to be enabled or disabled over a wireless medium. For example, the prioritized-access contention mechanism may be configured to allow a prioritized station (STA) to transmit a reservation signal over the wireless medium at a reservation signal transmission time, and to contend the wireless medium according to a high-priority contention policy to obtain a Transmit Opportunity (TxOP) after transmission of the reservation signal. For example, the reservation signal transmission time may be based on an end of a predefined time duration from a start of a contention period. For example, the reservation signal may be configured to indicate a busy Clear Channel Assessment (CCA) to a receiving STA.
    Type: Application
    Filed: September 30, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Laurent Cariou, Thomas J. Kenney, Dmitry Akhmetov, Dibakar Das
  • Publication number: 20240088035
    Abstract: Described herein are full wafer devices that include passive devices formed in a power delivery structure. Power is delivered to the full wafer device on a backside of the full wafer device. A passive device in a backside layer is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Tahir Ghani, Wilfred Gomes, Anand S. Murthy
  • Publication number: 20240086357
    Abstract: Systems and methods for updating remote memory side caches in a multi-GPU configuration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a first memory, a first memory side cache memory, a first communication fabric, and a first memory management unit (MMU). The graphics processor includes a second graphics processing unit (GPU) having a second memory, a second memory side cache memory, a second memory management unit (MMU), and a second communication fabric that is communicatively coupled to the first communication fabric. The first MMU is configured to control memory requests for the first memory, to update content in the first memory, to update content in the first memory side cache memory, and to determine whether to update the content in the second memory side cache memory.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Altug Koker, Joydeep Ray, Aravindh Anantaraman, Valentin Andrei, Abhishek Appu, Sean Coleman, Nicolas Galoppo Von Borries, Varghese George, Pattabhiraman K, SungYe Kim, Mike Macpherson, Subramaniam Maiyuran, Elmoustapha Ould-Ahmed-Vall, Vasanth Ranganathan, James Valerio
  • Publication number: 20240086064
    Abstract: Embodiments described herein enable the offload of address calculations required to access a data element within an array of data elements from primary compute resources of a graphics processor to the memory access circuitry of the graphics processor. The memory access circuitry is configured to receive a message to access a data element of an array of data elements in the memory, the message to include an index of the data element in the array of data elements, calculate a byte address for the data element based in part on the index of the data element in the array of data elements, and submit a memory access request to the memory to access the data element at the byte address.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: John Wiegert, Joydeep Ray, Timothy Bauer, James Valerio
  • Publication number: 20240089082
    Abstract: A method comprises receiving, from an input device, an input speech signal, encoding the input speech signal to generate a first homomorphically encrypted string, sending the homomorphically encrypted string to a remote device via communication link, receiving, from the remote device, a reply comprising a second homomorphically encrypted string, decoding the second homomorphically encrypted string into an output speech signal, and outputting the output speech signal on an audio output device.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy Bottleson, Ernesto Zamora Ramos, Kylan Race, Fillipe Dias Moreira de Souza, Hubert de Lassus, Jingyi Jin
  • Publication number: 20240086199
    Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.
    Type: Application
    Filed: August 4, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Balaji Vembu, Abhishek R. Appu, Joydeep Ray, Altug Koker
  • Publication number: 20240089601
    Abstract: Multi-camera dynamic calibration can be performed using three or more images, each from a separate camera viewing the same 3D scene. Multi-camera translation magnitude can be determined by incorporating information from an additional image. A relative translation scale is determined for a configuration of three cameras using a ratio of translation magnitudes. The translation scale can be expanded to configurations having more than three cameras using the relative scale of the pair-wise camera translations to determine translation scales for a multi-camera set-up. If the ground-truth translation is known for a pair of cameras, then the translation magnitude can be determined for all pairs of cameras to ground-truth accuracy. Multi-camera scale estimation is divided into smaller overlapping triplet-camera scale estimation, and the translation scale determination corresponding to each image pair is applied iteratively to overlapping sets of three images.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventor: Avinash Kumar
  • Publication number: 20240088029
    Abstract: Described herein are full wafer devices that include interconnect layers on a back side of the device. The backside interconnect layers couple together different dies of the full wafer device. The backside interconnect layers include an active layer that includes active devices, such as transistors. The active devices may act as switches, e.g., to control routing of signals between different dies of the full wafer device.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Tahir Ghani, Wilfred Gomes, Anand S. Murthy, Sagar Suthram
  • Publication number: 20240086329
    Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a cache, one or more execution units (EUs) to execute program code, prefetch logic to maintain tracking information of memory instructions in the program code that trigger a cache miss and compiler logic to receive the tracking information, insert one or more pre-fetch instructions in updated program code to prefetch data from a memory for execution of one or more of the memory instructions that triggered a cache miss and download the updated program code for execution by the one or more EUs.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Vasileios Porpodas, Guei-Yuan Lueh, Subramaniam Maiyuran, Wei-Yu Chen
  • Publication number: 20240086258
    Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Reshma Lal, Pradeep Pappachan, Luis Kida, Soham Jayesh Desai, Sujoy Sen, Selvakumar Panneer, Robert Sharp
  • Publication number: 20240086683
    Abstract: An apparatus to facilitate workload scheduling is disclosed. The apparatus includes one or more clients, one or more processing units to processes workloads received from the one or more clients, including hardware resources and scheduling logic to schedule direct access of the hardware resources to the one or more clients to process the workloads.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Liwei Ma, Nadathur Rajagopalan Satish, Jeremy Bottleson, Farshad Akhbari, Eriko Nurvitadhi, Chandrasekaran Sakthivel, Barath Lakshmanan, Jingyi Jin, Justin E. Gottschlich, Michael Strickland
  • Publication number: 20240086161
    Abstract: Described herein is a technique for automatic generation of optimized RTL via redundant code removal. By automatically introducing local mutations into the original RTL and using equivalence checking tools to confirm that the functionality it is not affected, optimized RTL can be produced automatically without requiring human intervention.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Theo Drane, Emiliano Morini, Jordan Schmerge, Samuel Coward
  • Publication number: 20240088069
    Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and the conductive segments are included in a tape.
    Type: Application
    Filed: February 26, 2021
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Wenzhi Wang, Xiaoning Ye, Yunhui Chu, Chunfei Ye, James A. McCall
  • Publication number: 20240087077
    Abstract: Embodiments described herein provide a technique to merge partial cache line writes to a cache memory. One embodiment provides a graphics processor comprising a graphics core, a cache coupled with the graphics core, and memory access circuitry to process memory access messages received from the graphics core. The memory access circuitry includes partial cache line write merge circuitry configured to merge a first partial write to a cache line of the cache with a second partial write to the cache line of the cache.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Abhishek R. Appu, Prathamesh Raghunath Shinde, John Wiegert
  • Publication number: 20240088296
    Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Erica J. THOMPSON, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, Biswajeet Guha, William Hsu, Bruce Beattie
  • Publication number: 20240086356
    Abstract: Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.
    Type: Application
    Filed: October 20, 2023
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, Varghese George, Mike Macpherson, Aravindh Anantaraman, Abhishek R. Appu, Elmoustapha Ould-Ahmed-Vall, Nicolas Galoppo von Borries, Ben J. Ashbaugh
  • Publication number: 20240088199
    Abstract: Techniques for a glass core inductor are disclosed. In the illustrative embodiment, an integrated circuit component includes a glass substrate and a fully-integrated voltage regulator (FIVR). The FIVR includes a glass core inductor that is embedded in the glass substrate. Each inductor turn of the inductor includes two angled through-glass vias and a trace on top of the glass substrate connecting the angled through-glass vias, resulting in an inductor with a cross-section in the shape of a triangle or trapezoid. The inductor may have a relatively large inductance per unit area, requiring less space or allowing for a larger inductance.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Brandon Christian Marin, Suddhasattwa Nad, Srinivas V. Pietambaram, Jeremy D. Ecton, Mohammad Rahman, Gang Duan
  • Publication number: 20240086291
    Abstract: An apparatus comprising first circuitry to process a request generated by a first device, the request specifying a memory address range of a second device to monitor for errors; and second circuitry to, based on a determination that a read request targets the memory address range of the second device, compare first data read from the second device with second data read from a memory to determine whether an error has occurred.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Amruta Misra
  • Publication number: 20240088017
    Abstract: Described herein are full wafer devices that include passive devices formed in one or more interconnect layers. Interconnect layers are formed over a front side of the full wafer device. A passive device is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device. In some embodiments, the passive devices are formed in global interconnect layers coupling multiple does of the full wafer device.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Tahir Ghani, Wilfred Gomes, Anand S. Murthy, Pushkar Sharad Ranade, Sagar Suthram