Patents Assigned to Intel Corporation
  • Publication number: 20220148967
    Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Applicant: INTEL CORPORATION
    Inventors: Manish CHANDHOK, Richard SCHENKER, Tristan TRONIC
  • Publication number: 20220149208
    Abstract: Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Yih Wang, Abhishek Sharma, Sean Ma, Van H. Le
  • Publication number: 20220147858
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base and a fin extending away from the base and including a quantum well layer. The device may further include a first gate disposed on a first side of the fin and a second gate disposed on a second side of the fin, different from the first side. Providing gates on different sides of a fin advantageously allows increasing the number of quantum dots which may be independently formed and manipulated in the fin. The quantum dots formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Methods for fabricating such devices are also disclosed.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Ravi Pillarisetty, Hubert C. George, Jeanette M. Roberts, Nicole K. Thomas, James S. Clarke
  • Publication number: 20220149036
    Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
  • Publication number: 20220148261
    Abstract: Methods, systems and apparatuses may provide for technology that determines the size of a graphics primitive, renders pixels associated with the graphics primitive on a per tile basis if the size exceeds a threshold, and renders the pixels associated with the graphics primitive in a mesh order if the size does not exceed the threshold. In one example, the technology discards state data associated with the graphics primitive in response to a completion of rendering the pixels associated with the graphics primitive in the mesh order.
    Type: Application
    Filed: November 15, 2021
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Justin DeCell, Saurabh Sharma, Subramaniam Maiyuran, Raghavendra Miyar, Jorge Garcia Pabon
  • Publication number: 20220149500
    Abstract: Microelectronic assemblies that include a lithographically-defined substrate integrated waveguide (SIW) component, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate portion having a first face and an opposing second face; and an SIW component that may include a first conductive layer on the first face of the package substrate portion, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and a first conductive sidewall and an opposing second conductive sidewall in the dielectric layer, wherein the first and second conductive sidewalls are continuous structures.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Adel A. Elsherbini
  • Publication number: 20220148123
    Abstract: An apparatus and method for scheduling threads on local and remote processing resources.
    Type: Application
    Filed: September 14, 2021
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Ravishankar Iyer, Selvakumar Panneer, Carl S. Marshall, John Feit, Venkat R. Gokulrangan
  • Publication number: 20220147791
    Abstract: Embodiments are generally directed to sparse 3D convolution acceleration in a convolutional layer of an artificial neural network model. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including feature maps. The one or more processors are to provide for sparse 3D convolution acceleration by applying a shared 3D convolutional kernel/filter to an input feature map to produce an output feature map, including increasing sparsity of the input feature map by partitioning it into multiple disjoint input groups; generation of multiple disjoint output groups corresponding to the input groups by performing a convolution calculation represented by the shared 3D convolutional kernel/filter on all feature values associated with active/valid voxels of each input group to produce corresponding feature values within corresponding output groups; and outputting the output feature map by sequentially stacking the output groups.
    Type: Application
    Filed: June 21, 2019
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Anbang YAO, Jiahui ZHANG, Dawei SUN, Dian GU, Yurong CHEN
  • Publication number: 20220148130
    Abstract: Embodiments described herein are generally directed to an end-to-end trainable degradation restoration network (DRN) that enhances the ability of a super-resolution (SR) subnetwork to deal with noisy low-resolution images. An embodiment of a method includes estimating, by a noise estimator (NE) subnetwork of the DRN, an estimated noise map for a noisy input image; and predicting, by the SR subnetwork of the DRN, a clean upscaled image based on the input image and the noise map by, for each of multiple conditional residual dense blocks (CRDBs) stacked within one or more cascade blocks representing the SR subnetwork, adjusting, by a noise control layer of the CRDB that follows a stacked set of a multiple residual dense blocks of the CRDB, feature values of an intermediate feature map associated with the input image by applying (i) a scaling factor and (ii) an offset factor derived from the noise map.
    Type: Application
    Filed: June 21, 2019
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Wenyi TANG, Xu ZHANG
  • Publication number: 20220150533
    Abstract: An embodiment of an adaptive video encoder may include technology to determine headset-related information including at least one of focus-related information and motion-related information, and determine one or more video encode parameters based on the headset-related information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: November 15, 2021
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Yunbiao Lin, Changliang Wang, Ce Wang, Yongfa Zhou, Bo Zhao, Ping Liu, Jianwei Yang, Zhan Lou, Yu Yang, Yating Wang, Wenyi Tang, Bo Qiu
  • Publication number: 20220146667
    Abstract: Some aspects relate to an apparatus, method and/or system of radar tracking. For example, a radar tracker may be configured to generate target tracking information corresponding to a plurality of targets in an environment of a radar device. For example, the radar tracker may include a processor configured to determine the target tracking information based on a plurality of multi-target density functions corresponding to a respective plurality of target types, and to update the plurality of multi-target density functions based on detection information corresponding to a plurality of detections in the environment. For example, the radar tracker may include an output to output the target tracking information.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Leor Banin, Yuval Amizur, Nir Dvorecki
  • Publication number: 20220147316
    Abstract: Embodiments described herein are generally directed to an improved vector normalization instruction. An embodiment of a method includes responsive to receipt by a GPU of a single instruction specifying a vector normalization operation to be performed on V vectors: (i) generating V squared length values, N at a time, by a first processing unit, by, for each N sets of inputs, each representing multiple component vectors for N of the vectors, performing N parallel dot product operations on the N sets of inputs. Generating V sets of outputs representing multiple normalized component vectors of the V vectors, N at a time, by a second processing unit, by, for each N squared length values of the V squared length values, performing N parallel operations on the N squared length values, wherein each of the N parallel operations implement a combination of a reciprocal square root function and a vector scaling function.
    Type: Application
    Filed: September 17, 2021
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Abhishek Rhisheekesan, Supratim Pal, Shashank Lakshminarayana, Subramaniam Maiyuran
  • Publication number: 20220150046
    Abstract: A security processor includes a scheduler to read input data blocks from an input buffer, send the input data blocks to one or more cryptographic circuits in a first random order; and send data blocks having random values in a second random order to one or more of the cryptographic circuits that did not receive the input data blocks.
    Type: Application
    Filed: September 16, 2021
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Dumitru-Daniel Dinu, Emre Karabulut, Aditya Katragada, Geoffrey Strongin, Avinash L. Varna
  • Publication number: 20220147331
    Abstract: An embodiment of a semiconductor package apparatus may include technology to identify workload control variables, add workload flags to respective edges in a static single assignment graph, and propagate constants based on the identified workload control variables and the workload flags. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 26, 2019
    Publication date: May 12, 2022
    Applicant: INTEL CORPORATION
    Inventor: Yuan Chen
  • Publication number: 20220147482
    Abstract: An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.
    Type: Application
    Filed: June 3, 2021
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Jihwan Kim, Ajay Balankutty, Sandipan Kundu, Stephen Kim, Frank O'Mahony, Kai Yu, Bong Chan Kim
  • Publication number: 20220147453
    Abstract: Techniques and mechanisms for metadata, which corresponds to cached data, to be selectively stored to a sequestered memory region. In an embodiment, integrated circuitry evaluates whether a line of a cache can accommodate a first representation of both the data and some corresponding metadata. Where the cache line can accommodate the first representation, said first representation is generated and stored to the line. Otherwise, a second representation of the data is generated and stored to a cache line, and the metadata is stored to a sequestered memory region that is external to the cache. The cache line include an indication as to whether the metadata is represented in the cache line, or is stored in the sequestered memory region. In another embodiment, a metric of utilization of the sequestered memory region is provided to software which determines whether a capacity of the sequestered memory region is to be modified.
    Type: Application
    Filed: November 12, 2020
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Michael Kounavis, Siddhartha Chhabra, David M. Durham
  • Publication number: 20220147393
    Abstract: An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include a field for an identifier of a first source operand, a field for an identifier of a destination operand, and a field for an opcode, the opcode to indicate execution circuitry is to program a user timer, and execution circuitry to execute the decoded instruction according to the opcode to retrieve timer program information from a location indicated by the first source operand, and program a user timer indicated by the destination operand based on the retrieved timer program information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 25, 2021
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Rajesh Sankaran, Gilbert Neiger, Vedvyas Shanbhogue, David Koufaty
  • Publication number: 20220147395
    Abstract: There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Da-Ming Chiang, Kshitij A. Doshi, Suraj Prabhakaran, Mark A. Schmisseur
  • Publication number: 20220147417
    Abstract: A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme and a flit-level forward error correction or parallel-forward error correction (FEC) scheme. Flit-level FEC schemes can provide improved latencies and efficiencies over per-lane FEC schemes. To improve retry probability, flits can contain information indicating whether immediately preceding flits are null flits. Receivers can avoid sending a retry request for a corrupted flit if a seceding flit indicates the corrupted flit is a null fit. Parity flits can be used to protect groups of flits and correct single-flit errors.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 11328988
    Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady, Anand Murthy