Electronic device

- Intel
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Description

FIG. 1 is a perspective view of an electronic device showing the new design;

FIG. 2 is a front view of the electronic device from FIG. 1;

FIG. 3 is a back view of the electronic device from FIG. 1;

FIG. 4 is a side view of the electronic device from FIG. 1;

FIG. 5 is another side view of the electronic device from FIG. 1;

FIG. 6 is a top view of the electronic device from FIG. 1; and,

FIG. 7 is a bottom view of the electronic device from FIG. 1.

The broken lines shown in the drawings represent portions of the electronic device that form no part of the claimed design. Additionally, line shading (including non-oblique line shading and contour shading), is meant to show contour of represented surfaces and not surface ornamentation.

Claims

The ornamental design for an electronic device, as shown and described.

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Patent History
Patent number: D754123
Type: Grant
Filed: Aug 21, 2013
Date of Patent: Apr 19, 2016
Assignee: Intel Corporation (Santa Clara, CA)
Inventors: Douglas Satzger (Santa Clara, CA), Sameer Sharma (Santa Clara, CA), Gadi Amit (San Francisco, CA), Yoshikazu Hoshino (San Francisco, CA)
Primary Examiner: Barbara Fox
Assistant Examiner: Dana K Weiland
Application Number: 29/464,887
Classifications
Current U.S. Class: Pocket Type (D14/341)