Pattern for package
Latest Samsung Electronics Patents:
- INTEGRATED CIRCUIT INCLUDING TEST CIRCUIT
- SPLITTER AND PHOTONIC INTEGRATED CIRCUIT INCLUDING THE SAME
- SUBSTRATE PROCESSING APPARATUS
- METHOD AND DEVICE WITH PATTERN IMAGE GENERATION
- PHASE-LOCKED LOOP CIRCUIT, STORAGE DEVICE INCLUDING THE PHASE-LOCKED LOOP CIRCUIT, AND OPERATION METHOD OF THE STORAGE DEVICE
Description
The file of this patent contains at least one drawing/photograph executed in color. Copies of this patent with color drawing(s)/photograph(s) will be provided by the Office upon request and payment of the necessary fee.
The broken lines in the figures show portions of the packaging box which form no part of the claimed design.
The dot-dash broken lines in the figures represent an unclaimed boundary line and form no part of the claimed design.
Claims
We claim the ornamental design for a pattern for package, as shown and described.
Referenced Cited
Patent History
Patent number: D760595
Type: Grant
Filed: Aug 1, 2014
Date of Patent: Jul 5, 2016
Assignee: Samsung Electronics Co., Ltd. (Suwon-si)
Inventors: Nu-Ri Choi (Suwon-Si), Seok-Young Kang (Hwaseong-Si), Seong-Wook Jeong (Seoul)
Primary Examiner: Sandra Morris
Application Number: 29/498,244
Type: Grant
Filed: Aug 1, 2014
Date of Patent: Jul 5, 2016
Assignee: Samsung Electronics Co., Ltd. (Suwon-si)
Inventors: Nu-Ri Choi (Suwon-Si), Seok-Young Kang (Hwaseong-Si), Seong-Wook Jeong (Seoul)
Primary Examiner: Sandra Morris
Application Number: 29/498,244
Classifications
Current U.S. Class:
D9/661;
D9/432