Electronic device
Latest Intel Patents:
- SEARCHING LOOP TRANSFORMATION SCHEDULE FOR DEEP LEARNING MODEL
- SUBSTRATE ENGINEERING FOR III-N TRANSISTORS
- TECHNOLOGIES FOR BASE DIE THERMAL MANAGEMENT IN HIGH-BANDWIDTH MEMORY SYSTEMS
- INTEGRATED CIRCUIT PACKAGE INCLUDING A SUBSTRATE WITH PACKAGE SUBSTRATE SIDE CONDUCTIVE CONTACTS FIRST APPROACH
- TECHNOLOGIES FOR BASE DIE PLACEMENT IN HIGH-BANDWIDTH MEMORY SYSTEMS
Broken lines shown in the figures depict environment only, and form no part of the claimed design.
Claims
The ornamental design for an electronic device, as shown and described.
| 5103376 | April 7, 1992 | Blonder |
| 5268816 | December 7, 1993 | Abell, Jr. |
| 6067224 | May 23, 2000 | Nobuchi |
| D499727 | December 14, 2004 | Kondo |
| D607882 | January 12, 2010 | Nakada |
| D615539 | May 11, 2010 | Jen |
| 7986517 | July 26, 2011 | Jiang |
| D646677 | October 11, 2011 | Moon |
| 8089748 | January 3, 2012 | Chiang |
| D684155 | June 11, 2013 | Hsu |
| D705774 | May 27, 2014 | Hung |
Type: Grant
Filed: Dec 26, 2014
Date of Patent: Jan 17, 2017
Assignee: Intel Corporation (Santa Clara, CA)
Inventors: Lily Kolle (Hillsboro, OR), Jered H. Wikander (Portland, OR)
Primary Examiner: Freda S Nunn
Application Number: 29/513,117