Folding display notebook computer
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Broken lines in the drawings are included for the purpose of illustrating an environment only and form no part of the claimed design.
Claims
The ornamental design for a folding display notebook computer, as shown and described.
| D588126 | March 10, 2009 | Chiang |
| D690691 | October 1, 2013 | Hoshi |
| D708605 | July 8, 2014 | Yang |
| D709067 | July 15, 2014 | Ahn |
| D717296 | November 11, 2014 | Oh |
| 20030151888 | August 14, 2003 | Chien |
| 20060146488 | July 6, 2006 | Kimmel |
| 20070242421 | October 18, 2007 | Goschin |
| 20100182265 | July 22, 2010 | Kim |
| 20120206896 | August 16, 2012 | Suzuki |
Type: Grant
Filed: Jun 30, 2016
Date of Patent: Jan 30, 2018
Assignee: Intel Corporation (Santa Clara, CA)
Inventors: Joshua L. Zuniga (Damascus, OR), David W. Browning (Beaverton, OR), Aleksander Magi (Aloha, OR), Saara Kamppari (Portland, OR), Audrey C. Younkin (Hillsboro, OR)
Primary Examiner: Freda S Nunn
Application Number: 29/569,870