Electronic device
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The broken line showings of internal edges within the hexagonal holes are for the purpose of illustrating environmental structure or unclaimed portions of the electronic device, and the broken lines form no part of the claimed design.
The shade lines show surface contour and not surface ornamentation.
Claims
The ornamental design for an electronic device, as shown and described.
| D479191 | September 2, 2003 | Peress |
| D620431 | July 27, 2010 | Sasada |
| D628148 | November 30, 2010 | English |
| D705219 | May 20, 2014 | Martin |
| D729163 | May 12, 2015 | Meyer |
| D793958 | August 8, 2017 | Rautiainen |
| D808902 | January 30, 2018 | Qiu |
| D814411 | April 3, 2018 | Lahiri |
| D824381 | July 31, 2018 | Collins |
| D837146 | January 1, 2019 | Kong |
| D851646 | June 18, 2019 | Huebner |
Type: Grant
Filed: Dec 22, 2017
Date of Patent: Nov 19, 2019
Assignee: Intel Corporation (Santa Clara, CA)
Inventors: Stephen D. Berry (Bastrop, TX), David M. Collins (Portland, OR), Randall W. Martin (Conroe, TX)
Primary Examiner: Austin Murphy
Application Number: 29/630,872