Use of a recirculating delay line with a time-to-digital converter
The resolution of a time to digital converter (TDC) is improved by using a gain stage at the input of the fine TDC. A delay line receives a pulse corresponding to the time information and recirculates the pulse in the delay line by coupling an output of the delay line to an input of the delay line. An integrating fine TDC receives a number of pulses from the delay line corresponding to the desired gain.
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This disclosure relates to time to digital converters (TDC) and to improvements in the resolution of TDCs.
Description of the Related ArtA Time-to-Digital Converter (TDC) converts the “time” information between two specified events into a digital number in terms of a given time-base. For example, referring to
The native resolution (TLSB) of the TDC is determined by the smallest measure of the time-base, which represents the smallest unit of time that can be quantified in the system.
Traditionally, in PLLs, phase delay information between a feedback clock (CLKFB) and a reference clock (CLKREF) is stored in voltage mode by using a phase detector followed by a charge-pump and a capacitor.
Thus, the capacitor stores the time information (phase delay) as charge.
Where TDCs are used to convert the time information to digital, TDCs often utilize 2-stages, a coarse TDC and a fine TDC. The coarse TDC typically works with a time base TCLK set by a system clock. The fine TDC is often based on a delay line using N elements with a unit delay of TGATE. The delay line may be locked to one period of the time base TCLK. The overall resolution is determined by the fine TDC. Improvements in the resolution of the TDC is desirable to achieve a more accurate TDC.
SUMMARY OF EMBODIMENTS OF THE INVENTIONEmbodiments disclosed herein improve the resolution of Time-to-Digital Converters (TDCs) by using a gain stage at the input of the TDC. The gain stage uses a “time amplifier” that provides a known fixed PVT invariant gain in the time domain. In embodiments, the time-domain gain is achieved by repetitive addition using a delay line to recirculate time information supplied by way of a pulse, which makes the overall gain PVT invariant.
In an embodiment a method for performing a time to digital conversion includes receiving an input pulse indicative of time information and recirculating a representation of the input pulse in at least one delay line. An output pulse corresponding to the input pulse is generated that is based, at least in part, on a delay line output signal of the at least one delay line. The output pulse is supplied N times to an integrating time to digital converter, where N is an integer greater than one.
In another embodiment an apparatus includes a delay line and input logic coupled to receive an input pulse and coupled to an output of the delay line, the input logic to supply a delay line input signal to the delay line. The delay line recirculates a representation of the input pulse. An integrating time to digital converter is coupled to the delay line to receive N pulse out signals, each pulse out signal corresponding to the input pulse to thereby generate a digital representation of the input pulse multiplied by a gain of N, where N is an integer greater than one.
In another embodiment an apparatus includes a delay line supplying a delay line output signal. A rising edge detector detects a rising edge of an input pulse and supplies a rising edge pulse. A falling edge detector detects a falling edge of the input pulse and generate a falling edge pulse. A first logic circuit logically combines the rising edge pulse, the falling edge pulse, and a feedback signal based on the delay line output signal. A second logic circuit receives an enable signal and an output pulse based on the delay line output signal and passes the output pulse when the enable signal is asserted.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates similar or identical items.
DETAILED DESCRIPTIONThe effective resolution (TLSB,eff) of the TDC can be improved by adding a gain at the input of the fine TDC prior to its quantization. As shown in
Note that the idea described in
In order to avoid the shortcoming of the time amplifier circuit illustrated in
The traditional approach for storing time information as charge as illustrated in
In order to store the time information, embodiments described herein leverage the high precision available in the time domain to “remember” the phase information as a pulse circulating in a delay line loop.
Referring to
The embodiment also includes an optional fast delay path 1353 and slow delay path 1355 formed, e.g., by buffers, that can be used to adjust the pulse width. A multiplexer 1357 selects the fast delay path or the slow delay path based on a select signal from control logic. The control logic 1359 determines whether to increase the pulse or decrease the pulse width. For example, the control logic may increase the pulse width by delaying the falling edge pulse in the slow path 1355 while the rising edge pulse width uses the fast path 1353. Alternatively, the control logic may decrease the pulse width by utilizing the slow path for the rising edge pulse and the fast path for the falling edge path. The control logic determines whether an edge is rising or falling based on whether it is odd or even.
The control logic 1359 that selects the fast or the slow path can be configured to “modulate” the pulse width in the loop. The actual operation depends on how the user wants the pulse width to change with time. Note that using this approach, the phase delay information can be made to be larger/smaller or monotonically increase/decrease by providing different delays in the feedback path. That can be used for noise shaping in a sigma delta loop.
For example, if the user wants the pulse width to monotonically increase, the control logic selects the “fast” path for the rising pulse and the “slow” path for the falling pulse. For that embodiment the control logic has a toggle flip-flop (not shown) clocked by the output of Div-by-2 1358 to control the select line 1360 to the multiplexer 1357. Such a control is useful in a pulse width modulation systems. Note that an extension of this control with a DTC (digital-to-time converter) can also be used to create a successive approximation register (SAR) TDC. In another embodiment, the control logic uses a pseudo-random bit sequence (PRBS) to randomize the selection of the fast/slow paths, which helps in mitigating spurs arising due to deterministic edges of the pulse for a given input.
The multiplication by 3 can be understood as follows. Assume the number of times the GRO has “rolled over” is “A”, then the “effective” number of delay units that toggled during the time the switch (1403) was asserted is given by 3*A+X. Here the term 3*A corresponds to the total delay of “3” unit cells rolling over “A” times. To provide gain, the pulse recirculating gain circuit, examples of which are shown in
In embodiments, the initial state of the delay line can be arbitrary. That is, the GRO can start from any initial state (as long as it is recorded as the initial state). Starting from an arbitrary state works because the “final” output is taken as the difference of the final and the initial state (1st difference) in embodiments. See, e.g., 707 in
Thus, various aspects have been described relating to improving the resolution of TDCs. The description of the invention set forth herein is illustrative, and is not intended to limit the scope of the invention as set forth in the following claims. Other variations and modifications of the embodiments disclosed herein, may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.
Claims
1. A method for performing a time to digital conversion comprising:
- receiving an input pulse indicative of time information;
- recirculating a representation of the input pulse in at least one delay line;
- generating an output pulse corresponding to the input pulse based, at least in part, on a delay line output signal of the at least one delay line; and
- supplying the output pulse N times to an integrator, where N is an integer greater than one.
2. The method as recited in claim 1 wherein recirculating the representation of the input pulse in the at least one delay line further comprises:
- logically combining a first input signal to the at least one delay line with a second input signal based on the delay line output signal.
3. The method as recited in claim 1 further comprising:
- selectively supplying the output pulse to the integrator N times according to an enable signal.
4. The method as recited in claim 1 further comprising:
- determining a polarity of the input pulse.
5. The method as recited in claim 1 further comprising:
- detecting a rising edge of the input pulse and generating a rising edge pulse;
- detecting a falling edge of the input pulse and generating a falling edge pulse;
- logically combining a feedback signal based on the delay line output signal and at least the rising edge pulse to generate a delay line input signal; and
- supplying the delay line input signal to an input of the at least one delay line.
6. The method as recited in claim 5 further comprising selecting one of a first delay path and a second delay path in a feedback path coupled between the delay line output signal and the input of the at least one delay line.
7. The method as recited in claim 5 further comprising logically combining the feedback signal based on the delay line output signal, the rising edge pulse, and the falling edge pulse to generate the delay line input signal.
8. The method as recited in claim 7 further comprising dividing the delay line output signal by two to generate the output pulse.
9. An apparatus comprising:
- a delay line;
- input logic coupled to receive an input pulse and coupled to receive an output of the delay line, the input logic to supply a delay line input signal to the delay line, wherein a representation of the input pulse is recirculated in the delay line; and
- an integrating time to digital converter coupled to the delay line to receive N pulse out signals, each pulse out signal corresponding to the input pulse to thereby generate a digital representation of the input pulse multiplied by a gain of N, where N is an integer greater than one.
10. The apparatus as recited in claim 9 wherein the input logic comprises an OR gate to logically combine the delay line input signal with a feedback signal corresponding to the output of the delay line to recirculate the input pulse.
11. The apparatus as recited in claim 10 further comprising:
- a first delay path and a second delay path in a feedback path between the output of the delay line and the input logic; and
- a selector circuit to select the first or the second delay path.
12. The apparatus as recited in claim 10 further comprising:
- a monostable multivibrator circuit coupled to the output of the delay line to generate the feedback signal.
13. The apparatus as recited in claim 9 further comprising:
- output logic coupled to an output of the delay line to supply a pulse out signal according to an enable signal.
14. The apparatus as recited in claim 9 further comprising:
- sign logic to determine a polarity of the input pulse and supply a sign indication.
15. The apparatus as recited in claim 9 further comprising:
- a rising edge detector to detect a rising edge of the input pulse and supply a rising edge pulse;
- a falling edge detector to detect a falling edge of the input pulse and generate a falling edge pulse; and
- a logic circuit to logically combine a feedback signal based on the output of the delay line, the rising edge pulse, and the falling edge pulse to generate the delay line input signal.
16. The apparatus as recited in claim 15 further comprising a divide by two circuit to divide the output of the delay line by two to generate a pulse out signal.
17. The apparatus as recited in claim 16 further comprising a gating circuit to selectively pass the pulse out signal N times according to an enable signal, to thereby effectively supply the input pulse N times to the integrating time to digital converter.
18. The apparatus as recited in claim 9 further comprising:
- a second delay line;
- a rising edge detector to detect a rising edge of the input pulse and supply a rising edge pulse;
- a falling edge detector to detect a falling edge of the input pulse and generate a falling edge pulse;
- a first logic circuit to logically combine an output of the delay line and the rising edge pulse to generate the delay line input signal;
- a second logic circuit to logically combine an output of the second delay line and the falling edge pulse to generate a second delay line input signal; and
- a logic circuit to combine the output of the delay line and the output of the second delay line into an output pulse supplied to the integrating time to digital converter as the representation of the input pulse for each of the pulse out signals.
19. An apparatus comprising:
- a delay line supplying a delay line output signal;
- a rising edge detector to detect a rising edge of an input pulse and supply a rising edge pulse;
- a falling edge detector to detect a falling edge of the input pulse and generate a falling edge pulse;
- a first logic circuit to logically combine the rising edge pulse, the falling edge pulse, and a feedback signal based on the delay line output signal; and
- a second logic circuit coupled to receive an enable signal and an output pulse based on the delay line output signal and to pass the output pulse when the enable signal is asserted.
20. The apparatus as recited in claim 19 comprising:
- a divide by two circuit coupled to receive the delay line output signal and supply the output pulse to the second logic circuit.
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Type: Grant
Filed: Dec 18, 2019
Date of Patent: Sep 14, 2021
Assignee: Silicon Laboratories Inc. (Austin, TX)
Inventor: Raghunandan Kolar Ranganathan (Austin, TX)
Primary Examiner: Luke S Wassum
Application Number: 16/718,854
International Classification: G04F 10/00 (20060101); H03K 5/159 (20060101); H03K 3/033 (20060101); H03K 5/1534 (20060101);