Delay circuits using negative resistance CMOS circuits
- IBM
A negative resistance circuit constructed of complementary field effect transistors has several applications. A voltage change at an input to the negative resistance circuit alters the current at the input node in a direction inverse to that normally caused by such a voltage change. The circuit can be used to speed up the charging or the discharging of a circuit node capacitance.
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Description
Patent History
Patent number: T955006
Type: Grant
Filed: Jun 14, 1976
Date of Patent: Feb 1, 1977
Assignee: International Business Machines Corporation (Armonk, NY)
Inventors: Joseph Richard Cavaliere (Hopewell Junction, NY), David Barry Eardley (Stanfordville, NY)
Application Number: 5/695,716
Type: Grant
Filed: Jun 14, 1976
Date of Patent: Feb 1, 1977
Assignee: International Business Machines Corporation (Armonk, NY)
Inventors: Joseph Richard Cavaliere (Hopewell Junction, NY), David Barry Eardley (Stanfordville, NY)
Application Number: 5/695,716
Classifications
Current U.S. Class:
307/251;
307/205
International Classification: H03K 1704; H03K 1760; H03K 1908; H03K 1920;
International Classification: H03K 1704; H03K 1760; H03K 1908; H03K 1920;
