Abstract: A thin film transistor which can be used in an LCD display panel includes an insulator substrate, a gate electrode located on the insulator substrate, an insulator film provided on the insulator substrate and the gate electrode, and a polycrystalline silicon film located on the insulator film. A channel is defined in a first portion of the polycrystalline silicon film over the gate electrode, and a drain and a source are defined in second and third portions of the polycrystalline silicon film over the insulator substrate. Grain sizes of the drain and source are equal to or greater than a grain size of the channel.

Abstract: An organic electroluminescent device comprises a pair of electrodes and a layer structure provided between the paired electrodes and including, at least, an emission layer comprising a specific type of oligomer. The layer structure may further comprise an electron injection layer and an electron transport layer, one of which comprises a specific type of oligomer. Alternatively, the layer structure may be of the type which comprises an organic layer having a charge transport interference layer in the inside thereof along with an emission layer.

Abstract: A semiconductor device includes a plurality of shallow trench isolation bands, a plurality of channels, a source electrode, a drain electrode, and a gate electrode. The shallow trench isolation bands are formed in a band-like shape within an element formation region defined by a shallow trench isolation region. The plurality of channels are isolated from each other by the shallow trench isolation bands and extend parallel to each other. The source electrode is formed at one end of each channel. The drain electrode is formed at the other end of each channel. The gate electrode is formed on the channels across the shallow trench isolation bands. A method of manufacturing this device is also disclosed.

Abstract: A method for growing nitride semiconductor crystals according to the present invention includes the steps of: a) forming a first metal single crystal layer on a substrate; b) forming a metal nitride single crystal layer by nitrifying the first metal single crystal layer; and c) epitaxially growing a first nitride semiconductor layer on the metal nitride single crystal layer.

Abstract: The power semiconductor element has an emitter region and a stop zone in front of the emitter region. The conductivities of the emitter region and of the stop zone are opposed to one another. In order to reduce not only the static but also the dynamic loss of the power semiconductor foreign atoms are used in the stop-zone. The foreign atoms have at least one energy level within the band gap of the semiconductor and at least 200 meV away from the conduction band and valence band of the semiconductor.

Abstract: A heterojunction bipolar transistor and its fabrication method is disclosed. The heterojunction bipolar transistor includes a substrate; a collector layer formed to have a ledge or MESA on the substrate; a collector electrode formed on the collector layer surrounding the ledge; a base layer formed on the ledge of the collector layer; an ohmic cap layer on the emitter layer; an emitter layer formed in the center of the base layer; an emitter electrode formed on the ohmic cap layer; a base electrode formed on the base layer surrounding the emitter electrode; an insulating layer formed to cover the base electrode and to overlay on the insulating layer; a metal wire formed to cover the emitter electrode; and an air bridge brought in contact with the metal wire and electrically connected to an external pad lying on an ion-implanted isolation region.

Abstract: It is an object of the present invention to provide a capacitor and a method of manufacturing the same having an electrode made of material(s) capable of carrying a fine work through etching while withstanding a high temperature thermal treatment for crystallizing dielectric materials such as ferroelectric materials and the like. The capacitor comprises a dielectric material composed by using at least a ferroelectric material or a high-dielectric material, and an electrode composed by using a material containing a noble metal, the electrode being formed on at least one side of the dielectric material, and the material of the electrode contains rhenium (Re). The capacitor is fabricated by patterning the material of the electrode contains rhenium (Re) using dry-etching method by introducing either of fluorine gas or chlorine gas.

Abstract: A memory circuit includes a plurality of word lines connected to a plurality of memory cells, a plurality of row address decode circuits having address input terminals, first wafer burn-in signal terminal, and second wafer burn-in signal terminal. The row address decode circuits activate all of the word lines when the first wafer burn-in signal and the second wafer burn-in signal are in an enable state. On the other hand, the row address decode circuits activate a subset of the word lines when the second wafer burn-in signal is in the enable state.

Abstract: A protective control unit for controlling a highside-output transistor and a lowside-output transistor connected in series is provided. The highside-output transistor has a first main electrode region connected to a power supply, a second main electrode region and a first control electrode. The lowside-output transistor has a third main electrode region connected to the second main electrode region, a fourth electrode region connected to ground and a second control electrode. And an inductive load is connected to a connecting point between the second and the third electrode regions. The protective control unit of the present invention has a highside-drive circuit. The highside-drive circuit pulls out charges stored in the highside-output transistor, through the first control electrode, during the periods when the highside-output transistor is in the end of reverse conducting state and reverse recovery state.

Abstract: A semiconductor device has a construction in which a gate dielectric film is formed on the surface of a semiconductor substrate having source regions and drain regions, a plurality of FG (Floating Gates) are formed on the gate dielectric film, an intergate dielectric film is formed on the FG, and CG (Control Gates) are formed on the intergate dielectric film. Mounds are formed on both sides of the FG. An interlayer dielectric film is formed between the gate dielectric film and the intergate dielectric film and covering these mounds. The FG are constituted by upper FG and lower FG, and the upper FG are formed to spread toward the areas where the mounds are formed and cover a portion of the interlayer dielectric film. The gate dielectric film is formed in a shape that does not rise in a direction that is substantially perpendicular to the surface of the semiconductor substrate at least above the upper FG.

Abstract: The invention provides a semiconductor device that has a fully depleted MOSFET and a partially depleted MOSFET having excellent characteristics on the same substrate without effecting control by means of the impurity concentration of the channel region. In FIG. 2E, semiconductor device 10 is provided with fully-depleted SOI MOSFET 12 and partially-depleted SOI MOSFET 14 on the same SOI substrate through isolation by element isolation film 4. SOI substrate includes buried oxide film 2 and SOI layer 3 provided in succession on silicon substrate 1. Film thickness TOX1 of gate oxide film 5 is 8 nm, film thickness TSOI1 of SOI layer 3 is 56 nm, and boron concentration NA1 of the channel region is 3×1017cm−3 in fully-depleted SOI MOSFET 12. In contrast, film thickness TOX2 of gate oxide film 5 is 12 nm, film thickness TSOI2 of SOI layer 3 is 59 nm, and boron concentration NA2 of the channel region is 5×1017cm−3 in partially-depleted SOI MOSFET 14.

Abstract: In a semiconductor device having a first terminal 101 (source terminal) and a second terminal 102 (drain terminal), the substrate main surface of a semiconductor chip is on the (110) face, the main contact face of an n-type region 2 and a p-type region 4 is the {111} face perpendicular to the (110) face, elongated n-type regions 2 and elongated p-type regions 4 which are arranged alternately and adjacently form a voltage holding area, said first terminal 101 is connected to said p-type regions through wiring, and said second terminal 102 is connected to said n-type regions 2. Also, said p-type region is formed to cover the bottom corners of a gate polycrystalline silicon layer 8.

Abstract: A recess is produced in a material layer by creating at least a first and a second structure in various steps. The layers define each other laterally and extend to the bottom of the recess. The first structure and the second structure are so narrow that they can be made by creating conformally produced layers that have an independent thickness and are smaller than the depth of the recess. The conformally produced layers are formed in an appropriate deposition process. A covering structure can be produced on top of the first and second structure. An opening can be made in the covering structure, through which the first structure and the second structure can be removed in an etching step.

Abstract: A method of manufacturing a semiconductor device including the steps of: (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a first mask on the interlayer insulating film, the first mask having a plurality of stripe patterns parallel to a first direction, and etching the interlayer insulating film from a surface thereof to a first intermediate depth to form a groove; and (c) forming a second mask on the interlayer insulating film, the second mask having a plurality of stripe patterns parallel to a second direction crossing the first direction, and etching the interlayer insulating film by a remaining thickness thereof in an area corresponding to the groove and not covered with the second mask to form an opening, and in an area other than the area corresponding to the groove to form a second groove reaching a second intermediate depth from a surface of the interlayer insulating film.

Abstract: A spiral inductor fabricated above a semiconductor substrate provides a large inductance while occupying only a small surface area. Including a layer of magnetic material above and below the inductor increases the inductance of the inductor. The magnetic material also acts as barrier that confines electronic noise generated in the spiral inductor to the area occupied by the spiral inductor. Inductance in a pair of stacked spiral inductors is increased by including a layer of magnetic material between the stacked spiral inductors.

Abstract: A bipolar transistor has a lightly doped n-type single crystal silicon layer epitaxially grown in a recess formed in a heavily doped n-type impurity region after a selective growth of a thick field oxide layer, a base region, an emitter region and a collector contact region are formed in surface portions of the lightly doped n-type single crystal silicon layer, and the single crystal silicon layer is not affected by the heat during the growth of the thick field oxide layer, and has a flat zone constant in dopant concentration regardless of the thickness thereof.

Abstract: A power semiconductor components has stop zones. In order to optimize the static and dynamic losses of the power semiconductor components, the stop zone is provided with donors which have at least one donor level which lies within the band gap of silicon and is at least 200 meV away from the conduction band edge of silicon.

Abstract: A semiconductor device includes a F-doped interlayer insulation film and a high-refractive index insulation film having a refractive index higher than a refractive index of the F-doped interlayer insulation film, such that the high-refractive index insulation film is disposed at least one of a top side and a bottom side of the F-doped interlayer insulation film.

Abstract: A method for fabricating an integrated circuit chip includes the steps of:

Abstract: A method and apparatus for delivering electrical power to a semiconductor die is provided in which a metal frame (104) is applied to the top surface of a semiconductor die. The metal frame include two voltages leads (106, 108), each adjacent to each series of bond pads (116) formed on the top surface of the semiconductor die. Each voltage lead includes a longitudinal portion (122) adjacent bond pads (116) in the center of the semiconductor die and corner portions (124) or arm portions (125) adjacent bond pads (116) located in the quadrants (114) of the semiconductor die.

Abstract: Disclosed is a wafer-level package.

Abstract: An electronic apparatus of the present invention comprises an electronic circuit board; an electrically conductive casing for encasing the electronic circuit board; a semiconductor element module electrically connected to the electronic circuit board; and a resin fixture intervening between the electrically conductive casing and the semiconductor element module, the resin fixture mounted with the semiconductor element module and fitted to the electrically conductive casing. As a result, the resin fixture can suppress a transfer of heat generated in the electronic circuit board to the semiconductor element module.

Abstract: The present invention provides a method and apparatus for fabricating densely stacked ball-grid-array packages into a three-dimensional multi-package array. Integrated circuit packages are stacked on one another to form a module. Lead carriers provide an external point of electrical connection to buried package leads. Lead carriers are formed with apertures that partially surround each lead and electrically and thermally couple conductive elements or traces in the lead carrier to each package lead. Optionally thin layers of thermally conductive adhesive located between the lead carrier and adjacent packages facilitates the transfer of heat between packages and to the lead carrier. Lead carriers may be formed of custom flexible circuits having multiple layers of conductive material separated by a substrate to provide accurate impedance control and providing high density signal trace routing and ball-grid array connection to a printed wiring board.

Abstract: Disclosed herein is a technique which performs the thinning of a wafer and the separation thereof from a support substrate with high yields and in a short time. Described specifically, a hole-free support substrate is bonded to a second surface of a support substrate having holes with an adhesive layer melted by heating so as to bloc the holes. A wafer is bonded to a first surface of the support substrate having the holes with an adhesive layer melted by solvent. The wafer is thinned by grinding and etching. The adhesive layer is melted by heating and the support substrate having the holes is slid with respect to the hole-free support substrate to thereby separate the support substrate having the holes from the hole-free support substrate. Further, the adhesive layer is melted by solvent from the holes defined in the support substrate having the holes to thereby separate the wafer from the support substrate having the holes.

Abstract: A microelectronic assembly includes a microelectronic element having a front face including contacts, a back surface remote from the front face and edges extending therebetween. A mass of a dielectric material at least partially encapsulates the microelectronic element. The microelectronic assembly includes conductive units embedded in the mass of dielectric material at at least one edge of the microelectronic element, whereby at least some of the conductive units are exposed on oppositely-facing exterior surfaces of the mass of dielectric material. Conductive elements extend through the mass of dielectric material and electrically interconnect the contacts with the conductive units.

Abstract: A method for fabricating an integrated circuit chip includes the steps of:

Abstract: A direct contact through hole type wafer structure. Both sides of a wafer have devices and contacts. The contacts are coupled with the devices. Bumps are formed on the contacts, respectively.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a conductive structure that couples a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card. The conductive structure includes a first conductive body and a second conductive body. The first conductive body is attached to the first substrate and the second conductive body is attached to the second substrate. The first conductive body may include a solder bump, while the second conductive body may include a eutectic alloy, such as a eutectic alloy lead and tin. Alternatively, the second conductive body may include a non-eutectic alloy whose melting point is below the melting point of the first conductive body.

Abstract: An arrangement for an electrical control circuit. The arrangement comprises a single-layer circuit board includes a first printed circuit; a circuit carrier substrate associated with the single-layer circuit board; a first bonding wire that electrically connects the first printed circuit and the circuit carrier substrate; and a second printed circuit that crosses with respect to the first electrically conductive path at a point. The first bonding wire and the first printed circuit define a first electrically conductive path; and the second printed circuit is electrically insulated from the first electrically conductive path at the point. Because of this arrangement, a potential-free intersection of printed circuits can be made in an especially simple manner.

Abstract: A memory device is described which is fabricated as an integrated circuit and uses distributed bond pads for electrical connection to an external conductive lead. The distributed bond pads are attached to a external lead, thereby eliminating bus lines on the integrated circuit memory. Distributed buffer circuits are described which can be included with the distributed bond pads to increase data communication time between the memory device and an external processor.

Abstract: In a semiconductor device, a plurality of wiring films are formed on a front surface of a base comprising an insulating resin and having electrode-forming holes, the surfaces of the wiring films and the surface of the base being positioned on the same plane and at least parts of the wiring films overlapping with the electrode-forming holes; a conductive material is embedded into the electrode-forming holes to form external electrodes on the back surface, away from the wiring films, of the base; a semiconductor element is positioned on the front surface of the base with an insulating film therebetween, the back surface of the semiconductor element being bonded to said front surface of the base; wires bond the electrodes of the semiconductor element to the corresponding wiring films; and a resin seals the wiring films and the wires.

Abstract: A semiconductor package capable of quickly and satisfactorily dissipating to the outside the heat generated from a semiconductor chip mounted in it and in turn capable of contributing to an improvement of the operational reliability of the semiconductor chip, provided with an interconnection substrate, a heat dissipation plate bonded to one surface of the interconnection substrate, a cavity formed in another surface of the interconnection substrate for with mounting a semiconductor chip, a plurality of external connection terminals arranged in a grid on the other surface of the interconnection substrate around the cavity, and through holes formed with conductor layers on their inside walls formed at a periphery of the interconnection substrate and penetrating through the interconnection substrate so as to reach the heat dissipation plate, and a semiconductor device using the same.

Abstract: In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.

Abstract: A surface of an external electrode 3 of an electronic part 4 is formed with a coating containing resin ingredient. Thereby, adhesion strength and reliability may be significantly improved in mounting an electronic part onto a circuit board 1 through the medium of a conductive adhesive. Further, it will be able to mount an electronic part to an element to be mounted by utilizing a conductive adhesive forming an external electrode 3 as a connecting element.

Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.

Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

Abstract: One embodiment of the present invention is a multiple seed layer structure for making metallic interconnect including: (a) a patterned insulating layer on a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least one opening; (b) a barrier layer disposed over the field and inside surfaces of the at least one opening; (c) a first seed layer disposed over the barrier layer using a first deposition technique; (d) a second seed layer disposed over the first seed layer using a second deposition technique, the first and second deposition techniques being different, one producing a substantially conformal seed layer and the other producing a substantially non-conformal seed layer; and (e) an electroplated metallic layer disposed over the second seed layer, the electroplated metallic layer including a material selected from a group consisting of Cu, Ag, or alloys including one or more of these metals.

Abstract: An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed to a height or thickness equal to or preferably exceeding the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer formed above the first dielectric layer; one or more local interconnects formed in the second dielectric layer; and a thin third dielectric layer formed over the second dielectric layer and the local interconnects therein. The thin third dielectric layer has a thickness not exceeding about 2000 Å, and preferably ranging from about 1000 Å to about 1500 Å. A first layer of metal interconnects is formed over the thin third dielectric layer.

Abstract: An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors 202 over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

Abstract: A three-dimensional semiconductor integrated circuit apparatus which permits ready electrical connection and is resistant to deformation and easy to fabricate and a manufacturing method therefor are provided. A second semiconductor substrate is stacked over a third semiconductor substrate, and a first semiconductor substrate is stacked over the second semiconductor substrate. A second integrated circuit is formed over the surface layer of the second semiconductor substrate, and the integrated circuit side of the second semiconductor substrate is bonded to the integrated circuit side of the first semiconductor substrate, resulting in the electrical connection of the first integrated circuit formed over the surface layer of the first semiconductor substrate and the second integrated circuit.

Abstract: A resin sealed semiconductor device includes a semiconductor chip having a main surface, a plurality of surface electrodes formed on the main surface of the chip, a plurality of projection electrodes formed the main surface, each projection electrode being connected to respective one surface electrodes, and a resin shield covering the main surface, the surface electrodes and side surfaces of the projection electrodes, the resin having a thermal expansion coefficient in the range of 8-10 ppm/° C. and a Young's modulus in the range of 1.8-2.0 Gpa.

Abstract: A method and apparatus for fabricating composite structures are disclosed. A method for fabricating composite structures is provided that includes providing a skin (20) that has at least one layer (160) of uncured composite material, and providing a flexible hinge tool (100) that has first and second tooling portions (110, 120) coupled with a flexible hinge (140). The first and second tooling portions (110, 120) of the hinge tool (100) each have a molding surface (112, 122), and the tooling portions (110, 120) are configured to form at least a portion of a stiffening member (10). The method further includes laying up at least one layer (160) of uncured composite material on the molding surfaces (112, 122) to form the stiffening member (10).

Abstract: A two-stage, electrically-powered injection unit for an injection molding machine includes an extruder for plasticating material, and a separate melt accumulator to receive the plasticated material. The accumulator includes an injection plunger that is slidably positioned to inject the plasticated material from the accumulator into a mold. The plunger is rotated and translated by an electrically-driven linear actuator, such as a roller screw mechanism. The plunger extends outwardly of the accumulator barrel at the commencement of an injection stroke and is peripherally supported by a bushing at the outer end of the accumulator barrel. The outwardly-extending portion of the plunger can also be supported by a movable intermediate support member to minimize lateral deflection of the plunger and enable a longer injection stroke to be employed.

Abstract: The present invention relates to an innovative cooling pin for cooling molded articles, a system which incorporates same, and a method for cooling a molded article which utilizes the cooling pin. The cooling pin of the present invention has a central pin structure with a head portion, a cooling fluid channel within the central pin structure terminating in an outlet in the head portion, and a plurality of fins positioned along the length of the central pin structure. Adjacent ones of the fins are preferably separated by a spacer. Each of the fins is preferably formed from a flexible material such as a flexible plastic material. The fins force and maintain cooling fluid introduced into the interior of the molded article in close proximity to the interior surfaces of the molded article.

Abstract: The invention provides for conferring a cup shape to the terminal junction segment (2) of pipes that are bi-axially oriented longitudinally and circumferentially and hence very sensitive to diameter and length reduction through heat by means of passage into a furnace (4) which heats the segment (2) to a differentiated temperature, increasing towards the end of the segment (2), whose inner diameter progressively drops down to a controlled value, as temperature increases (whilst length is simultaneously reduced, with a corresponding increase in thickness). Preferably then, in an appropriate station (33), an additional heating is executed to a plastic deformation temperature suited to obtain a correct preliminary dilation of the terminal segment (2), introducing a rigid element (34) which acts as inner contrast, thereby inhibiting any retraction thereof. Here the segment (2) undergoes a thickening of the dilated wall both during the introduction of the rigid element (34), and during its extraction therefrom.

Abstract: A self-pumping hydropneumatic spring strut with internal leveling is provided for use in motor vehicles having an oil filled working cylinder, which is under the pressure of at least one gas cushion arranged in a high pressure chamber and acting as a spring. The high pressure chamber is connected to a working space, wherein a bleed opening forms a flow connection between the working space and the low pressure chamber. The bleed opening can be closed as a function of the position of the working piston in the working cylinder. The spring strut is assigned an actuator which displaces the spring strut in the vertical direction. The actuator can displace the motor vehicle to a plurality of displacement distances without requiring any electrical or electronic control, complex external leveling devices, or displacement detection systems.

Abstract: A holder for accurate positioning of a workpiece in the working area of a machine tool, especially an erosion machine, which includes a vibration damper to make the holder insensitive to vibrations such as those caused by variable rinse fluid pressure while machining the workpiece. At least one of the holder and workpiece is provided with a vibration damper.

Abstract: A finisher for finishing papers sequentially driven out of an image forming apparatus includes a plurality of trays selectively movable to a single paper outlet. The finisher reduces a period of time necessary for designated one of the trays to reach the paper outlet, increases the number of papers which can be stacked on the trays, and determines the number of papers stacked with a simple configuration. Papers are prevented from returning from the tray to the paper outlet without complicating the configuration of the outlet. An outlet roller protrudes from the paper outlet, but does not interfere with the tray moving past the paper outlet. The trays protect the operator from injury and protect the structural elements of the finisher from damage despite their movement.

Abstract: A removable chuck has a chuck member for holding a drill bit. Also, a mechanism is coupled with the chuck body to retain the chuck body to a drill spindle. The retention mechanism, in a first position, retains the chuck on the drill spindle and in a second position the chuck is enabled to be removed from the spindle.

Abstract: A skateboard scooter comprises a main board and a blade releasably attached to the main board. In an embodiment, the main board includes several through-holes. An attachment base is mounted below the main board and has several through-holes aligned with the through-holes of the main board. Bolts are extended through the through-holes of the main board and the through-holes of the attachment base and engaged with nuts. The attachment base includes two parallel ribs defining a compartment therebetween for holding an upper longitudinal edge of the blade. In an alternative embodiment, the main board includes two parallel ribs extended downward therefrom. The ribs include at least one pair of aligned transverse holes. The blade includes at least one hole. At least one bolt is extended through the transverse holes of the ribs and the hole of the blade and engaged with a nut.