Abstract: A polished glass disk medium substrate table for use as a substrate for a hard disk, a hard disk containing the substrate and methods for making the substrate. Glass forming raw materials are formed into a disk having a diameter between about 70 mm and about mm, a thickness between about 0.7 mm and about 0.9 mm, a flutter of less than 90 nm at 10,000 rpm.

Abstract: An actuator beam that can be incorporated into an actuator arm assembly of a hard disk drive. The actuator beam may include a dynamic absorber that extends from a distal end of the beam. The dynamic absorber may attenuate any resonant displacement in the actuator beam induced by a shock load that is applied to the hard disk drive.

Abstract: A negative pressure air bearing slider including a first air bearing surface formed on the bottom of the slider body at the upstream position so as to extend in the lateral direction of the slider body, and a pair of second air bearing surfaces formed on the bottom of the slider body separately from the first air bearing surface at downstream positions spaced in the lateral direction so as to define an air stream passage therebetween. The second air bearing surfaces serve to generate positive pressures that are spaced apart at downstream positions where a transducer element is embedded in the slider body, so that the slider's stiffness to rolling action can be enhanced. The cooperation of the front and rear rails enables for the creation of a higher negative pressure.

Abstract: A HGA includes a magnetic head slider having at least one thin-film magnetic head element, an IC chip having a circuit for the at least one thin-film magnetic head element, and a suspension for supporting the magnetic head slider and the IC chip. All surfaces of the IC chip are coated by additional insulation layers. (FIG.

Abstract: A flexure design is provided that can focus the lifting force on a slider device at its leading edge. For sub-ambient pressure sliders, this results in an rapid increase in pressure in the sub-ambient pressure area causing the slider device to quickly lift off from the disk surface in a ramp unload disk drive. In one embodiment, first and second outriggers are provided in the flexure that each include a section that extends distally and a section that extends proximally. The sections of the outriggers that extend proximally can be joined and coupled to a tab section slider which would be located at the leading edge of the slider.

Abstract: A head assembly for an information storage device that includes a head slider with a read/write element for reading/recording information to/from a disk and a suspension for supporting the head slider. The suspension includes a generally planar sheet that extends in a longitudinal direction from a first end to second end and an arm attaching portion located near the first end of the generally planar sheet of said suspension. The arm attaching portion is adapted to be attached to a head arm. The suspension also includes a slider attaching portion positioned near the second end of the generally planar sheet of the suspension, where the slider attaching portion extends generally in the longitudinal direction and is surrounded by a generally U-shaped opening in the generally planar sheet. The slider attaching portion faces a securing surface of the head slider.

Abstract: A helical scan drum design for use in non-tracking tape devices which assures 70% coverage of a track to be read by overscanning with at least two read heads at approximate 1× speed. The present invention further provides a simulation method for evaluating potential drum designs for such overscan applications. The preferred drum design uses pairs of like-azimuth read heads positioned on the rotating drum such that in combination they overlap the scan of a track by 130% the track width. These dimensions assure at least 70% coverage of each track by at least one of the pair of heads at up to 1× speed while assuring no overlap with another like-azimuth recorded track. The simulation method allows for evaluation of potential drum designs by accepting parameters describing the intended drum application and then simulating track read operations over a plurality of simulated tracks to determine the efficacy of the design over a range of tape speeds and gap widths.

Abstract: There are provided a magnetic head for vertical magnetic recording capable of suppressing noises due to a magnetically soft layer and improving the lowering of efficiency, and a magnetic recording and/or reproducing system using the same.

Abstract: An earth leakage detection device (14) includes a housing (52) and an earth leakage detection circuit (114) mounted within said housing (52) for detecting earth leakage in the electrical distribution circuit. A dielectric test switch (115) is arranged between the electrically conductive strap (18) and the earth leakage detection circuit (114). Pressing the button (84) causes said dielectric test switch (115) to stop the flow of electrical current from said electrically conductive strap (18) to said earth leakage detection circuit (114) to protect the circuit (114) during dielectric testing. A lever arm (605), pivotally secured within said housing (52), causes said trip/reset mechanism (116) to actuate the circuit breaker (12) when said button (84) is pressed. The trip/reset mechanism (116) is resiliently mounted within said housing (52), independently from said transformer (182).

Abstract: A current limiter is provided to protect a fieldbus network from electrical shorts in the wiring of the spur cables and network devices attached to the spur cables. In the event of an electrical short, the impedance of the current limiter and the spur connection increases permitting the remainder of the network to continue to function. To facilitate repairs, the current limiter includes an indicator that signals excessive current in the spur. A method of connecting a spur cable to the network is provided where the spur cable is connected to a separate current limiter module that is plugged into a connector block.

Abstract: A power semiconductor circuit drives a load connected an output terminal. An output switch switches the output terminal to either one of an on-state and an off state. An internal state signal terminal produces an internal state of the circuit as a signal. An internal state signal switch switches the internal state signal terminal to either one of an on-state and an off-state. An internal state sensor detects the internal state of the circuit. A logic circuit is given with a control signal from an external control circuit, a detecting signal of the internal state sensor, and the signal from the internal state signal terminal, and switches the output switch and the internal state signal switch to either one of the on-state and the off-state on the basis of the given signals.

Abstract: A surge suppressor conducts heat from a surge protection component (SSC) through a heat conductive element, such as a copper pad, on a printed circuit board, to at least one thermal fuse to cause the thermal fuse to open when the resistance of the SSC begins to decrease, resulting in an increase of heat generated by the SSC.

Abstract: A dielectric ceramic composition contains 100% by weight of main component composed of about 35 to 55% by weight of SrTiO3, about 10 to 35% by weight of PbTiO3, about 5 to 12% by weight of CaTiO3, about 8 to 25% by weight of Bi2O3 and about 5 to 13% by weight of TiO2, and about 0.02 to 0.5% by weight of MnO, about 0.05 to 2% by weight of an oxide of at least one element selected from the group consisting of La, Ce, Nd, Pr, Sm, Dy, Er and Y, and about 0.02 to 0.8% by weight of CuO. The dielectric ceramic composition can provide a capacitor which exhibits a low loss and a high dielectric constant, and which can be used in the high frequency region, thereby permitting the advance in miniaturization of the capacitor.

Abstract: A capacitive element for a circuit board or chip carrier having improved capacitance and method of manufacturing the same is provided. The structure is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured or softened followed by being fully cured or hardened. The lamination takes place by laminating a partially cured or softened sheet to at least one other sheet of dielectric material and one of the sheets of conductive material. The total thickness of the two sheets of the dielectric component does not exceed about 4 mils and preferably does not exceed about 3 mils; thus, the single dielectric sheet does not exceed about 2 mils and preferably does not exceed about 1.5 mils in thickness.

Abstract: A computer housing or case contains computer system components including a display unit, a processor, and a computer power supply unit. One or more handles are positioned at a side of the case to allow a user to hold the encased computer system while viewing the display. A case has a support interface structure to hold the case steady in an upright position. The support interface structure of the case mates with a complimentary support interface in the weight-supporting base unit and mates with guides to align a power supply port in the case to contact a power supply port in the base unit. A base unit has a keyboard guide to receive a keyboard by lifting the keyboard above a support surface. A modular computer system comprises a tablet computer, a base unit, and a remote keyboard. A first infrared communication device couples the tablet computer to the remote keyboard and other input peripherals. A second infrared communication device couples the tablet computer to a remote printer.

Abstract: A notebook computer has a base housing with a heat-generating microprocessor therein, and a lid housing pivotally connected to the base housing. Operating heat from the microprocessor is transferred to the lid housing, for dissipation therefrom, via a specially designed thermosyphoning heat pipe structure formed from first and second heat pipes. The first heat pipe representatively has a rectangular cross-section, an evaporating portion thermally communicated with the microprocessor, and a coiled condensing portion centered about the lid hinge line and having a circularly cross-sectioned interior side surface portion defined by flat sides of the first heat pipe. The second heat pipe has a circular cross-section, an evaporating portion pivotally received within the coiled first heat pipe portion, and a condensing portion thermally communicated with the lid housing.

Abstract: The double-sided edge lighting-type display sign of the present invention comprises at least two illuminating light sources; two or one display signages; and a light-directing panel. Preferably, a display sign housing accommodates and supports the other elements of the present invention. Namely, the light box housing supports at least two light sources, the display signages and the light-directing panel. The light-directing panel of the present invention is at least partially light reflective and at least partially light passing. The light directing panel directs and redirects light from the included at least two edge lighting-type light source to the included display signages. The light ultimately incident on the display signages is greater than it would normally be without the light-directing panel.

Abstract: A keyboard is provided having illuminating keys. The keyboard includes a light channeling membrane and key members constructed at least partially of translucent material so that light produced from a light source is channeled upwardly to the upper surfaces of the key members. The light source may include LED or LEC systems in adjoining relationship to the light channeling membrane. However, in a preferred embodiment, the light source is constructed of a substantially planar illuminescent sheet which underlies the light channeling membrane.

Abstract: A double lamp table or floor lamp lighting system has a pair of compact fluorescent lamps (CFLs) or other lamps arranged vertically, i.e. one lamp above the other, with a reflective septum in between. By selectively turning on one or both of the CFLs, down lighting, up lighting, or both up and down lighting is produced. The control system can also vary the light intensity from each CFL. The reflective septum ensures that almost all the light produced by each lamp will be directed into the desired light distribution pattern which is selected and easily changed by the user. In a particular configuration, the reflective septum is bowl shaped, with the upper CFL sitting in the bowl, and a luminous shade hanging down from the bowl. The lower CFL provides both task lighting and uniform shade luminance. Planar compact fluorescent lamps, e.g. circular CFLs, particularly oriented horizontally, are preferable. CFLs provide energy efficiency.

Abstract: A novel decorative apparatus is disclosed that depicts various symbols including sports, school, or holiday symbols by providing a frame in the shape of the desired symbol. The frame is provided with connection devices that orient small electric lamps in a predetermined direction whereby the small electric lamps outline the symbol.

Abstract: A flood light includes a lamp that is located at a focus of a reflecting mirror having a reflecting surface whose cross-section is oval and partially arcuate. A concave lens having negative refracting power is disposed between first and second foci about which an elliptical reflecting surface of the reflecting mirror is disposed. Some light rays from the lamp pass directly from the lamp through the lens while other rays from the lamp are reflected by the mirror before passing through the lens. Generally speaking, on the upstream side of the lens, the reflected rays enter the lens outboard of the rays that pass directly from the lamp to the lens. This construction provides a small flood light that has a high optical output, and effectively uses bundles of rays emitted from the lamp to produce a luminous intensity distribution desirable as light for range finding.

Abstract: The electric lamp/reflector unit has a molded reflector body (1) comprising a hollow neck-shaped portion (5). An electric lamp (10) having a lamp vessel (1), having a space (12) in which an electric element (13) is arranged, and provided with a first (14) and a second, opposed end portion (15) is fixed at its end portion (14) within the neck-shaped portion (5). Outer current conductors (16, 17) extending from the electric element (13) are connected each to a respective contact member (9, 29) provided on the outer surface (23) of the molded reflector body (1).

Abstract: A system and method of cooling a bulb of a type that requires cooling in one part, but not in others. A deflector assembly is coupled through a reflector, to the bulb, to cool only one part.

Abstract: A lighting fixture has a canopy formed thereon. Electrical wiring for a lamp socket of the fixture is routed through the canopy. One end of each wire electrically connects to the socket, and the other end of each wire extends through the canopy. A mounting plate fits in opening defined by the canopy and is secured to the canopy. The plate has a central opening through which the free ends of the wires extend. The mounting plate includes a swivel bar attached to the plate on its side to connect it to an outlet box. By attaching the outlet box to the swivel bar, and then the mounting plate to the fixture, the fixture can be adjusted to any orientation regardless of the orientation of the outlet box. In one embodiment, the swivel bar is replaced with arcuate slots through which fasteners extend to allow the plate (and hence the fixture) to be set to a desired orientation with respect to the outlet box.

Abstract: A vehicle lamp device supporting structure 5 for supported by a front end of a vehicle, comprises a fragile portion 21 breakable in vehicle collision. The fragile portion is provided in mount brackets 7, 8 and 9 which protrude from a housing 10 of the lamp device 5. A shroud panel 4 supporting the lamp device 5 includes an opening 2 to allow the lamp device 5 to be displaced rearward when the mount brackets 7, 8 and 9 are broken up.

Abstract: A room lamp fixing structure having a temporary fixing means provided for a room lamp and a ceiling trim and a permanent fixing means provided for the room lamp and a ceiling framework of a car body. This construction includes a ceiling trim having a recess for accommodating the room lamp, the recess having its side surface inclined so as to become gradually narrow from the opening portion to the bottom portion, and a room lamp having in its side surface a guide projection for positioning the room lamp and the ceiling trim by abutting against the slant side surface of the recess during the permanent fixing. This structure allows the guide projection to abut against the slant side surface, and thereby the room lamp and the ceiling trim are positioned.

Abstract: The truck rearview mirror assembly of the present invention is used on a truck having a coupling status system for sensing trailer coupling status. The rearview mirror assembly includes a mirror housing adapted for mounting to a truck, a mirror disposed within the mirror housing, and a display carried by the housing. The display is coupled to the coupling status system for displaying trailer coupling status information to a driver of the truck.

Abstract: An active clamp circuit is provided on the primary side of a composite resonance type switching converter which has a voltage resonant converter on its primary side and a parallel resonance circuit on its secondary side, wherein a parallel resonance voltage pulse generated across a primary parallel resonance capacitor is clamped so that the level thereof is suppressed. Consequently, the withstand voltage requisite relative to any of the component elements such as switching elements and the primary parallel resonance capacitor employed in the power circuit can be selectively lowered.

Abstract: DC/DC conversion circuit (1), comprising a transformer (2) having a primary winding (3), a secondary winding (4), and an auxiliary winding (5); a switching transistor (T), comprising a series circuit with the primary winding (3) between first and second direct current input terminals (6; 7); a start circuit (R1, C1) connected to a control electrode of the switching transistor (T) for switching the switching transistor (T) on by powering the direct current input terminals (6; 7); a control transistor connected to the control electrode of the switching transistor (T) for switching off the switching transistor (T) in dependence on a current flowing through the series circuit during operation.

Abstract: In a PDP power circuit, a rectifier circuit is connected to an external commercial power source, and a high voltage power circuit is connected to the rectifier circuit and outputs a first voltage. A first capacitor is connected between an output terminal of the high voltage power circuit and the ground potential. A low voltage power circuit is also connected to the rectifier circuit and outputs a second voltage lower than the first voltage. The input terminal of a DC/DC converter is connected to the high voltage side of the first capacitor, while the output terminal of the DC/DC converter is connected to the output terminal of the low voltage power circuit. A voltage detector circuit is also connected to the output terminal of the high voltage power circuit. The first voltage is supplied to a PDP drive circuit, while the second voltage is supplied to a PDP control circuit.

Abstract: A voltage boosting device having a charge pump circuit formed by a plurality of voltage boosting stages cascade-connected together.

Abstract: A power conversion device according to the invention of the present application includes: an active current controller that calculates a phase angle reference value for determining the ON/OFF phase with reference to the AC power source voltage phase, from the deviation of the input active current with respect to an active current reference value; and a fixed pulse pattern generator that controls the self-excited voltage type power converter by generating switching signals of fixed pulse pattern whose fundamental frequency is synchronized with the AC power source frequency, based on the phase angle reference value calculated by this active current controller.

Abstract: An AC power is rectified in a rectification circuit, and a pulsating voltage is output via a noise filter. The pulsating voltage is input to a switching circuit, and an AC voltage having a pulse width corresponding to a control signal is output. The AC voltage is transformed and rectified. The pulsating voltage is smoothed in a smoothing condenser, and a DC voltage is output. A voltage change detecting circuit detects a change of the DC voltage in a period longer than a period of ripple included in the DC voltage, and a detection signal is output. The detection signal is input to a control circuit, and a negative feed-back control is executed so that the DC voltage becomes constant.

Abstract: A semiconductor memory device arrangement that provides improved sensitivity of a sense amplifier that reads data from a memory cell. This sensitivity increase is accomplished by increasing a voltage difference between a data I/O line an a complementary data I/O line. A plurality of memory cells stor data. A data input/output (I/O) line pair (including a data I/O line and a complementary data I/O line), coupled to the memory cells, transfers the data. A sense amplifier senses and amplifies a voltage difference between the data I/O line and the complementary data I/O line. A capacitor has a first of its terminals coupled to the data I/O line. A first switching unit transfers the data applied to the data I/O line pair to two terminals of the capacitor in response to a first control signal. A second switching unit couples the second terminal of the capacitor to the data I/O line in response to a second control signal.

Abstract: A memory system comprises a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings and module power wirings respectively. The module data wirings of each memory module are connected in series form through series paths lying within the connectors. Each individual module data wirings do not constitute branch wirings to system data wirings on the system board. Thus, such signal reflection as caused by branching from the data wirings on the system board is not developed. Since the power is supplied in parallel from the system board through parallel paths lying within the connectors, the supply of the power is stabilized.

Abstract: Disclosed are semiconductor devices having terminal arrangements in which mirrored pairs of the semiconductor devices can be tested by a common test device.

Abstract: A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each the block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connecting to an external power terminal and a power supply terminal of each the boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.

Abstract: A magnetic storage cell includes an active layer and a reference layer which is structured to minimize disruptions to magnetization in its active layer. The reference layer is structured so that a pair of its opposing edges overlap a pair of corresponding edges of the active layer. This may be used minimize the effects of demagnetization fields on the active layer. In addition, the reference layer may be thinned at its opposing edges to control the effects of coupling fields on the active layer and balance the demagnetization field.

Abstract: A logic test having less over-head for testing a logic circuit in a chip is implemented by constituting a test circuit in the chip without introducing a novel device process of FPGA. A memory of a self-configuration type is provided in the chip and a test circuit is constituted in the memory of a self-configuration type or an ordinary memory through a tester HDL, thereby testing other memories and logic circuits in the chip. The test circuit is reconstituted such that the memory used in the structure of the test circuit can be operated as an ordinary memory.

Abstract: A semiconductor memory device invention having a data latch circuit disclosed in the present invention, comprising a plurality of bit lines to which a reprogramable memory cell is connected, a data bus on which data is transferred, a latch circuit having latching the data transferred on the data bus, a read our circuit connected to the data bus and a data transfer circuit group having an ability to directly transfer the data latched in the latch circuit, to the read our circuit without transferred to the memory cell.

Abstract: It is provided a delay locked loop for obtaining a reduced jitter and a stable time delay adjustment to thereby perform a bi-directional time delay with a small area even at low frequency applications. The delay locked loop includes an input unit for receiving a clock signal and a non-clock signal and comparing received signals to produce an internal clock signal, a controller for receiving the internal clock to produce a control signal, a bi-directional oscillator, responsive to the control signal from the control means, for performing a ring oscillation in a first or second direction and fulfilling an addition and subtraction adjustment function for a time delay, a counter for receiving an output signal of the bi-directional oscillator and counting the number that the signal is passed therethrough, and an AND gate for performing a combination operation on the outputs of the bi-directional oscillating means and the counting means, to produce the result as a final internal clock signal.

Abstract: A memory repair circuit uses an antifuse of MOS structure, capable of repairing defective cells by constructing the antifuse by MOS transistors and programming the antifuse circuit properly. The memory repair circuit comprises a plurality of antifuse devices, each programmed when a power voltage and a negative voltage are supplied respectively to a first electrode and a second electrode thereof; a latch for detecting and latching program states of the antifuse devices; and a redundancy block for replacing a defect cell with a redundancy cell depending on the output of the latch.

Abstract: In a semiconductor memory device having redundancy capability, a control signal generating circuit is included respectively for each of a predetermined number of redundant column select signal lines, to generate a predetermined number of block control signals by dividing a plurality of memory cell array blocks into a predetermined number of groups. A predetermined number of defective enable signal generating circuits are included for each of the redundant column select signal lines, to generate a predetermined number of redundant enable signals when defective addresses are input. The redundant column select signal lines are established for defective addresses based on the block control signals. A selection circuit is included respectively for each of the redundant column select signal lines to generate a select signal for selecting a redundant column select signal line corresponding to each of a predetermined number of redundant enable signals, in response to the block control signals.

Abstract: The present invention provides a semiconductor memory device comprising: memory cells; main decoders decoding address signals; sense amplifiers for reading out informations from the memory cells; and word drivers for driving the memory cells, wherein a row address controlled by a single main word line in a basic cell in the word driver, and two of the main word line of the row address are made correspond to a half of lower-order 2-bits of the row address, and a word driver signal is placed inside of the basic cell of the word driver to prevent the word driver signal from being commonly used to adjacent two of the basic cell.

Abstract: A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to coupl

Abstract: The present invention provides a semiconductor memory device capable of simplifying a test process for a memory circuit containing a nonvolatile memory while reducing an overhead of its chip area and a system incorporating the same semiconductor memory device.

Abstract: A semiconductor has eight banks that can be accessed simultaneously. Within each bank, there are disposed two fixed spare row decoders and two mapping spare row decoders. Within each bank, two fixed fuse sets are provided corresponding to the fixed spare row decoders. Eight mapping fuse sets are provided at the outside of each bank, for example, with no association with the mapping spare row decoders. Each mapping fuse set stores mapping data for determining a correspondence of the mapping fuse set to a specific mapping spare row decoder within a specific bank.

Abstract: A circuit transfers data in an array of memory cells arranged in rows and columns. The circuit includes a plurality of row lines, a plurality of pairs of complementary digit lines, and an array of memory cells, each memory cell having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell. A plurality of sense amplifiers are included in the circuit, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states.

Abstract: A read timing circuit regulates the step of reading from a multi-level non-volatile memory, which circuit is of a type adapted to generate and issue an equalization signal to a sense amplifier placed downstream of a dummy path including at least one dummy wordline, the latter being applied a supply voltage and associated with a dummy decoding circuit portion which receives an ATD signal. The circuit comprises a differential cell comparator having a first input connected downstream of the dummy path and a second input to receive a reference signal, thereby generating an electric signal on an output upon the dummy wordline attaining a potential which is a predetermined percent of the supply voltage.

Abstract: The present invention is directed to a logic circuit for controlling the read latency time of a memory circuit. The logic circuit comprises a first circuit for producing a plurality of values derived from a read enable signal. Each of the values represents the read enable signal delayed by a predetermined period of time. The logic circuit also comprises a second circuit for selecting one of the plurality of values in response to at least one control signal. The selected value enables a read operation of the memory circuit. A method for controlling the read latency time of a memory circuit is also disclosed.