Abstract: A TFT array substrate has a PAI pattern, and the PAI pattern has an over-etched portion of the pure amorphous silicon layer. This over-etched portion prevents a short between the pixel electrode and the pure amorphous silicon layer (i.e., the active layer). The over-etched portion also enables the aperture ratio to increase.

Abstract: A sensor device has a semiconductor sensor chip mounted on a resin package with which insert pins are insert-molded. The sensor chip and the pins are electrically connected to each other by bonding wires. An electrically insulating protective member covers the chip, the pins, and the wires. The protective member has a saturated swelling coefficient of approximately 7 wt % at most when the protective member is immersed into gasoline having a temperature of 20° C. Accordingly, bubbles are prevented from being produced in the protective member.

Abstract: Provided with a solid state image sensor, which is adapted to simplify the process with enhancement of the morphology of the device and has photo-diodes formed on a semiconductor substrate, and transfer gates disposed around the photo-diodes to transfer signal charges generated from the photo-diodes, the solid state image sensor including: an insulating layer forming on the whole surface of the semiconductor substrate and having a contact hole exposing a defined portion of the transfer gates; a metal line formed to include the inside of the contact hole; and a light-shielding layer formed in the same layer with the metal line without overlapping the upper parts of the photo-diodes.

Abstract: A capacitor including a capacitor lower electrode, a capacitor dielectric film of a highly dielectric film or a ferroelectric film and a capacitor upper electrode is formed on a semiconductor substrate. A protection film is formed on the semiconductor substrate so as to cover the capacitor. A first TEOS film having a relatively large water content is formed on the protection film through first TEOS-O3 CVD where an ozone concentration is relatively low. A second TEOS-O3 film having a relatively small water content is formed on the first TEOS-O3 film through second TEOS-O3 CVD where the ozone concentration is relatively high.

Abstract: A dynamic random access memory (DRAM) integrated circuit (10). The DRAM (10) includes a recessed region (20) defined in a semiconductor substrate (22). This recessed region has substantially vertical sides (34) extending from a bottom surface (32). A field effect transistor (18) is defined adjacent to the recessed region (20). A capacitor structure, including a lower capacitor plate (26), a capacitor dielectric (28), and an upper capacitor plate (30), is defined in the recessed region (20) and over the field effect transistor (18), thereby providing a greater capacitor surface.

Abstract: A fuse configuration for a semiconductor apparatus is described. The fuse configuration has a semiconductor material disposed underneath the fuse and is made porous by implantation and subsequent etching, so that it provides a thermal insulation. The thermal insulation protects the semiconductor body when the fuse is blown due to a decreased energy requirement for blowing the fuse.

Abstract: A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed above the electrodes; and an opposing electrode formed above the dielectric films, wherein the shape of a side wall of the insulating film includes a shape reflecting the outer peripheral shape of a side wall of the electrode facing the side wall of the insulating film. The semiconductor device of high integration, low cost and high reliability can be realized.

Abstract: A vertical gain memory cell including an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and p-channel junction field-effect transistor (JFET) transistors formed in a vertical pillar of semiconductor material is provided. The body portion of the p-channel transistor is coupled to a second source/drain region of the MOSFET which serves as the gate for the JFET. The second source/drain region of the MOSFET is additionally coupled to a charge storage node. Together the second source/drain region and charge storage node provide a bias to the body of the JFET that varies as a function of the data stored by the memory cell. A non destructive read operation is achieved. The stored charge is sensed indirectly in that the stored charge modulates the conductivity of the JFET so that the JFET has a first turn-on threshold for a stored logic “1 ” condition and a second turn-on threshold for a stored logic “0” condition.

Abstract: A semiconductor device wherein in formation of the wiring connection, an opening is made up to the middle of the insulating film, a side wall is formed, a burying wiring with the lower portion is arranged, a pad is formed, and a pad is formed in a polyplug contact without a masking step. Further, a conductive material is filled in the hole in the insulating film, a hole is opened in this material, a side wall is formed on the inner wall, a shrunken contact is opened by using this as a mask, and the conductive material is filled.

Abstract: A semiconductor device has a structure in which a gate electrode formed on a semiconductor substrate is buried in an interlevel insulating film so that the upper surface of the gate electrode is exposed, and an insulating film not containing boron and phosphorous is formed on this gate electrode. In this structure, the film thickness of the interlevel insulating film is small. This reduces the aspect ratio of a contact hole and improves the quality of burying of the contact hole. Since no interlevel insulating film which usually contains boron and phosphorous exists on the gate electrode, a shape change of the contact hole caused by annealing can be suppressed. This can improve the reliability of contact.

Abstract: First and second gate electrode layers located in a first conductive layer, first and second drain-drain connecting layers located in a second conductive layer, and first and second drain-gate connecting layers located in a third conductive layer become conductive layers for forming a flip-flop. First and second contact-conductive sections are formed in a region from an interlayer dielectric between the first and second conductive layers to an interlayer dielectric between the second and third conductive layers. The first drain-gate connecting layer is connected to the second gate electrode layer with the first contact-conductive section interposed. The second drain-gate connecting layer is connected to the first gate electrode layer with the second contact-conductive section interposed.

Abstract: In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.

Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.

Abstract: A trench field-effect transistor with a self-aligned source. At least a portion of the source implantation dose (604) is implanted underneath the gate (610) of a trench transistor by implanting an a non-orthogonal angle to the sidewall (608) of the trench. In one embodiment, a slow diffuser, such as arsenic, is implanted to minimize the post-implant diffusion. The resulting structure ensures gate-source overlap, and a consistent, small, gate-source capacitance with a lower thermal budget for the resultant device. The narrow depth of the source, in conjunction with its unique L-shape, improves device ruggedness because the source doping does not compensate the heavy body doping as much as with conventional devices. In one embodiment, the substrate is rotated 90 degrees within the implanter to implant both sidewalls of a trench.

Abstract: A semiconductor device includes a first region of semiconductor material, which is doped to a first concentration with a dopant of a first conductivity type. A gate trench formed within the first region has sides and a bottom. A drain access trench is also formed within the first region, which also has sides and a bottom. A second region of semiconductor material is located within the first region and adjacent to and near the bottom of the gate trench. The second region extends to a location adjacent to and near the bottom of the drain access trench. The second region is of the first conductivity type and has a higher dopant concentration than the first region. A gate electrode is formed within the gate trench. A layer of gate dielectric material insulates the gate electrode from the first and second regions. A drain region of semiconductor material is located within the drain access trench. The drain region is of a first conductivity type and has a higher dopant concentration than the first region.

Abstract: A MOS transistor of the present invention comprises a gate insulating film disposed on the surface of a silicon substrate, a p-type gate electrode formed on the gate insulating film, and sidewalls formed on both sides of the gate insulating film and the gate electrode. A pair of p-type source/drain areas is provided in surface portions of the silicon substrate, and a channel area is located between the source/drain areas. The gate insulating film comprises a central portion and both end portions located on both sides of the central portion. The central portion is formed of a nitride insulating film containing at least nitrogen, and both end portions are each formed of an oxide insulating film containing oxygen and no nitrogen. The source/drain areas comprise lightly doped source/drain areas located on inner sides in contact with the channel area and deeply doped source/drain areas located on the outer sides of the lightly doped source/drain areas to form an LDD structure.

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of a source and a drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometaric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequity: (X/Y)>(X0/Y0).

Abstract: When sidewalls (10) are formed by anisotropic etching, an insulating film (9) serves as a protective film for a major surface of a semiconductor substrate (100) and therefore prevents the major surface from suffering etching damage. That relieves an electric field concentration in a pn junction, to effectively take advantage of an LDD structure. Since a portion of the insulating film (9) extending off the sidewalls (10) is removed, there is no need for etching of the insulating film (9) when the contact holes (12) are formed and only an insulating film (11) is etched. That prevents a short circuit between main electrodes (13) and a gate electrode (7) and makes it possible to determine the spacing between the contact holes (12) narrower than the width of the gate electrode (7).

Abstract: A semiconductor device of SOI structure comprises a surface semiconductor layer in a floating state, which is stacked on a buried insulating film so as to construct an SOI substrate, source/drain regions of second conductivity type which are formed in the surface semiconductor layer, a channel region of first conductivity type between the source/drain regions and a gate electrode formed on the channel region through a gate insulating film; wherein the surface semiconductor layer has a potential well of the first conductivity type formed therein at and/or near at least one end of the channel region in a gate width direction thereof.

Abstract: A semiconductor circuit is disclosed which contains a driving circuit which is integrated into a semiconductor substrate of a first conductivity type and includes positive voltage switching transistors for switching positive and/or zero voltage levels and negative switching transistors for switching negative and/or zero voltage levels. In addition, the driving circuit contains a control circuit which is positioned upstream from the driving circuit and is also embodied in the semiconductor substrate, which is connected to a substrate voltage. A negative voltage switching transistor of the driving circuit is configured inside an outer well which is embedded in the semiconductor substrate and is of a second conductivity type which is opposite to the first, and the outer well is connected to a supply voltage.

Abstract: In a semiconductor device including a semiconductor substrate, a well formed on the semiconductor substrate, and a thick field insulating layer for surrounding an active area of the well, a contact structure is buried in a contact hole provided in the thick field insulating layer and connected to the well, so as to fix a voltage at the well.

Abstract: A method for interconnecting bit contacts and digit lines of a semiconductor device. A mask, through which portions of sidewall spacers of the digit lines located proximate the bit contacts are exposed, is positioned over the digit lines. Dopant is directed toward the semiconductor device at a non-perpendicular angle to a plane of the semiconductor device so as to dope portions of the sidewall spacers on one side of each of the digit lines while sidewall spacers opposed thereto and adjacent bit contacts are shielded from the dopant. Doped regions of the sidewall spacers may be removed with selectivity over undoped regions thereof to expose connect regions of each conductive element of each digit line. A conductive strap may then be formed to electrically link each connect region to its corresponding bit contact. Semiconductor devices including the conductive straps are also disclosed.

Abstract: To improve a shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15b) of the gate electrode 15G.

Abstract: A semiconductor chip having circuits which are produced in at least one layer of a semiconductor substrate and are arranged in at least one group. The semiconductor chip has at least one conductive protective layer which is arranged above at least one such circuit group and is electrically connected to at least one of the circuits. The substrate has at least one protective sensor, and the detection connection(s) of the protective sensor/protective sensors is/are connected to the conductive protective layer or to at least one of the conductive protective layers. Output connections of the protective sensor/protective sensors are connected to at least one of the circuits such that the circuit(s) cannot operate properly if there is a defined, nonvolatile level at the output of the protective sensor(s).

Abstract: In one aspect, the invention includes a semiconductor processing method comprising a) forming a metal silicide layer over a substrate; b) depositing a layer comprising silicon, nitrogen and oxygen over the metal silicide layer; and c) while the layer comprising silicon, nitrogen and oxygen is over the metal silicide layer, annealing the metal silicide layer.

Abstract: A semiconductor device with digital and analog circuits has a structure for preventing noise penetration from the digital circuit to the analog circuit. The semiconductor device has a semiconductor substrate, first and second wells independently formed at a surface of the semiconductor substrate, the digital circuit formed at a surface of the first well, and the analog circuit formed at a surface of the second well. The specific resistance of the semiconductor substrate is at least 1000 times as large as the specific resistance of the first well. A conductive guard-ring may be formed in the surface of an area that is between the digital circuit and the second well or between the first well and the second well.

Abstract: The present invention is a semiconductor device having an element isolation structure of STI, in which after the formation of the STI trench, a silicon nitride film is left over only on the side wall portion of the trench, to form a side wall. Further, ions are implanted from the bottom surface of the trench on which the side wall is formed, and thus a high-concentration punch-through suppression region having the same conductivity as that of the substrate (or well) and a concentration higher that the impurity concentration of the other section close to the substrate (or well), is formed selectively only in the section of the substrate (or well) which is near the bottom surface of the trench. In this manner, the punch-through suppression region can be formed only in the bottom portion of the STI in a self-alignment manner by the thickness of the side wall.

Abstract: The structure of a high-Q inductor applied in a monolithic circuit according to the invention comprises a plurality of spiral metal lines and a plurality of dielectric layers, each dielectric layer formed between two adjacent spiral metal lines. Furthermore, via plugs are formed in each dielectric layer to electrically connect two adjacent spiral metal lines. A spiral air trench is formed along the spacing of the spiral metal lines in the dielectric layers. Therefore, the 3D-structure of the inductor of the invention can greatly reduce the series resistance thereof without widening the spiral metal lines. In addition, the spiral air trench, filled with air which has a lower dielectric constant, can efficiently reduce the parasitic capacitance between the spacing of the spiral metal lines. As a result, the inductor of the invention has a higher quality factor at a proper RF operating frequency region.

Abstract: A patterned polysilicon film is formed over a silicon substrate with an interlayer insulating film therebetween. Then heavily doped regions as well as a lightly doped region are formed on the polysilicon film. The entire polysilicon film is covered with an SiO2 film. The polysilicon film is hydrogenated, while an SiNx film is formed over the entire SiO2 film, by LPCVD using a gas comprising nitrogen and hydrogen.

Abstract: A semiconductor passivation technique uses a plasma enhanced chemical vapor deposition (PECVD) process to produce a silicon-rich nitride film as a passivation layer on a Group III-V semiconductor device. The silicon-rich film has a nitrogen to silicon ratio of about 0.7, has a relatively high index of refraction of, for example, approximately 2.4, is compressively stressed, and is very low in hydrogen and oxygen content.

Abstract: The semiconductor device includes a semiconductor chip, a tape for mounting the semiconductor chip thereto, an adhesive resin layer interposed between the semiconductor chip and the tape, and solder balls attached to the tape. The method of fabricating the semiconductor chip comprises the step of forming at least one hole in the tape, after fixing the semiconductor chip to the tape through the adhesive resin layer. Also, the TAB tape is made of polyimide having high water permeability.

Abstract: The invention relates to an electronic device and methods for producing it, the device having at least one microscopically small contact area (1) for an electronic circuit having interconnects (2) on a surface (3) of a substrate (4), and furthermore the contact area (1) additionally comprising a three-dimensionally extending microscopically small contact element (5) which is connected to the contact area (1) in one piece and integrally.

Abstract: Concerning a plurality of second bonding pads that are electrically connected with a plurality of first bonding pads provided on an IC chip and having a predetermined narrow pitch, a technique is disclosed that allows the plurality of second pads to be provided on the IC chip. This makes it possible to provide the second pads at desired positions. Accordingly, it becomes possible to form, by printing with a low accuracy, respective interconnections that connect the plurality of second pads with a plurality of electrodes provided on a substrate. Also, matching of positions is executed between the plurality of second pads and the plurality of electrodes formed on the substrate by printing. This matching makes it possible to electrically connect the second pads with the electrodes provided on the substrate in a such a manner that they are opposed to each other.

Abstract: In a stacked-type semiconductor unit having a plurality of semiconductor devices stacked on a base board including a base electrode, each semiconductor device has a wiring board including an external electrode provided in an end portion thereof. The semiconductor devices are stacked on the base board such that the external electrodes are aligned with one another. Then, the external electrodes are electrically connected to the base board by solder.

Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a bump projecting from a first surface of a semiconductor chip; and forming a conductive layer so that part of the conductive layer is exposed at a position depressed from a second surface of the semiconductor chip opposite to the first surface, wherein the exposed part of the conductive layer and the bump become electrical connecting sections.

Abstract: The present invention provides a cooling apparatus which can increase air flow. A plurality of blades 25 are provided with extending portions 25b of the blades which extend outwardly in the direction of the diameter of the axis 9a of the motor 9 and rotate at such a space that is outside and surrounds the opening 13 in the space 17. The extending portions 25b of the blades are integrally formed with the blades 25. The rim portions 25c of the extending portions 25b of the blades which are disposed on the side of the first wall part and extend along the first wall part are sloped so as to be gradually away from the first wall part 15 as they extend toward the edges.

Abstract: A semiconductor device according to the invention is provided with square first semiconductor chip and second semiconductor chip laminated with each one main surface opposite, a supporting lead a part of which is arranged between one main surface of the first semiconductor chip and one main surface of the second semiconductor chip and a resin sealing body that seals the first semiconductor chip, the second semiconductor chip and the supporting lead and is characterized in that the respective one main surfaces of the first semiconductor chip and the second semiconductor chip are bonded to a part of the supporting lead via an adhesive layer and a part of the supporting lead is formed so that it has smaller width than the respective sides of the first semiconductor chip and the second semiconductor chip.

Abstract: A semiconductor device includes a semiconductor element having an electrode formation surface on which an electrode terminal and a re-wiring portion are formed. The re-wiring portion is electrically connected to the electrode terminal. An external terminal made of wire has a base end connected to the re-wiring portion and a distal end extending therefrom. An electrically insulating resin covers the electrode formation surface in such a manner that at least the distal end of the external terminal is exposed outside the insulating resin. During a fabricating process, the electrode formation surface is coated with an electrically insulating resin and then a part of the electrically insulating resin is removed from the distal end of the external connecting terminal to expose the same outside the insulating resin.

Abstract: The main subject of the present invention is a semiconductor device with a semiconductor element bonded on a circuit substrate by a bump comprising a solder alloy. Here, the solder alloy is an Sn—Ag-based alloy having a 90 (wt %) or more Sn content, a 0.01 or less (cph/cm2) &agr; ray amount in Sn, and a 1.5 (wt %) to 2.8 (wt %) Ag content. Accordingly, a solder alloy capable of preventing generation of a needle-like projection generated in a solder alloy at the time of bonding a semiconductor element on a circuit substrate for coping with frequent generation of a soft error accompanying the fine pitch, in executing the flip-chip bonding in a Pb-free solder alloy mainly containing Sn, with a long fatigue life without causing deterioration of the insulation resistance, and without generation of a soft error by &agr; rays, and a semiconductor device using the same are realized.

Abstract: A resin sealed type semiconductor device, is provided with a semiconductor chip which has a pad formed on a main surface thereof, an insulating film which is formed on a part of the pad and on the main surface of the semiconductor chip, an interconnection which is formed on a part of the insulating film and which is electrically connected to the pad, a sealing resin which seals the interconnection and the insulating film, a post formed on the interconnection which has a surface exposed to outside of the sealing resin which is electrically connected to the interconnection, a bump electrode which is mounted on the exposed surface of the post and a radiation post which is formed on the insulating film and which has a surface exposed to outside of the sealing resin.

Abstract: A contact device of the present invention is able to contact with a spherical test terminal. The contact device has a spring and a contact part. Also, the contact part has one end on which two or more protruded portions are formed and the other end on which a top end of the sprig is attached. The protruded portions are able to contact with a spherical surface of the spherical test terminal except for the top thereof with a high degree of precision and a high degree of the contact reliability.

Abstract: An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches therein; a first level of digit lines residing at least partially in the trenches; a second level of digit lines residing on the surface of the layer, the second level extending in generally parallel relation to the digit lines in the first level. The first level of digit lines are in alternating positions with the second level of digit lines and the alternating positions comprise a repeating pattern of a first complementary pair of digit lines at the first level adjacent a second complementary pair of digit lines at the second level.

Abstract: In the semiconductor device, an opening 3 having a high aspect ratio is made from the back surface of a GaAs substrate 1 by anisotropic dry etching. After an Au film 4 is deposited on the entire back surface of the Gabs substrate inclusive of the inside of the opening 3, the entire back surface is subjected to Ni alloy non-electrolytic plating so that an Ni film 9a can be also deposited on the inner wall and bottom of the opening 3 can be obtained. An IC substrate or FET with the Ni film 9a left only at the area corresponding to a via hole. The back surface of the IC substrate or FET and the front surface of a package substrate are bonded to each-other by AuSn solder having poor wetting for the Ni film 9a.

Abstract: A semiconductor device comprises a memory unit, a selecting signal terminal, and an identifying unit. The selecting signal terminal receives a memory unit selecting signal which is commonly transmitted to a plurality of memory units. The identifying unit distinguishes the memory unit from other memory units on the basis of the memory unit selecting signal, and includes an identifier generating circuit and a memory unit selecting circuit. A plurality of semiconductor devices are laid one over after another, thereby constituting a semiconductor module.

Abstract: In the present semiconductor device, a chip with an LSI circuit is secured to a board 3 (with the chip flipped) so as to be level. The LSI circuit on the chip is specified to operate normally only when the chip is level. Further, the back of the chip is processed so as to give stress to the chip. The chip has a reduced thickness of 50 &mgr;m or less (alternatively 30 &mgr;m to 50 &mgr;m). Therefore, when the chip is detached from the board, it deforms and is no longer level due to the stress, which prohibits the LSI circuit from operating normally. This way, the present semiconductor device ensures that no analysis can be conducted on the LSI circuit once the chip is detached.

Abstract: The present invention is directed toward an apparatus and method of reinforcement of lead bonding in microelectronics packages. In one embodiment, a microelectronics package includes a microelectronics device having a bond pad, a conductive lead having a first end bonded to the bond pad to form a lead bond, an encapsulating material at least partially disposed about the conductive lead, and a reinforcement portion at least partially disposed about the lead bond and at least partially coupling the first end to the bond pad. The reinforcement portion has a greater modulus of elasticity and/or a greater bond strength than the encapsulating material.

Abstract: A method and structure is provided for preventing wetting or bleed of an adhesive, such as an epoxy, onto noble metal wire bond pads on the surface of a dielectric substrate when attaching an I/C chip to the substrate. The method includes treating the wire bond pads with a chemical composition which prevents bleeding onto the surfaces of the wire bond pads by a component of the epoxy. The chemical composition is a chemical which will provide “Self-Assembled Monolayers” (SAMs) on the surface of the gold. These compositions are characterized by a molecule having at least one group, such as a mercaptan or disulfide, connected to a hydrocarbon moiety, such as a (CH2)x chain. The affinity of the thiol or sulfur-containing portion of the molecule chemically bonding with the noble metal provides a relatively strong attachment of the molecule to the metal surface.

Abstract: An apparatus and method for use in raising cattle, and in particular bulls, wherein bulls are:

Abstract: The invention relates to a device for supplying substances to be dispensed into air or air mixtures, especially scents, with a flat disk-shaped or plate-shaped base body with multiple separate channels running through it essentially parallel to its top and/or bottom sides, with the channels accommodating the substances to be dispensed and containing an inlet port and an outlet port, respectively, so that a stream of gas supplied to the inlet port can flow through it, with the inlet and outlet ports of at least one channel being sealed in a gastight manner until the substance is released and/or the substance is placed with an airtight seal in at least one channel in a reservoir which does not release this substance until the time of dispensation thereof.

Abstract: In order to prevent global warming, technology is developed for dissolving carbon dioxide gas in waste gas containing carbon dioxide, which is discharged in large quantities from stations gas generating facilities such as thermal power plants, in sea water and isolating it deep in the sea.