Abstract: Provided are methods for preparing non-corrosive, electroactive, conductive organic polymers, such as for use in electrochemical cells, wherein the non-corrosive polymers are formed by treatment of electroactive, conductive organic polymer compositions, comprising corrosive anions, with sulfide anions. Also provided are non-corrosive conductive organic polymers prepared by such methods, composite cathodes comprising such polymers, electrochemical cells comprising such cathodes, and methods of preparing such composite cathodes and cells.

Abstract: A safety jack, comprising a gear housing having a base wall connected to a rear wall, the base wall having a hole formed therein and the rear wall including an opening. A leg housing, formed from a hollow tube of rectangular cross section, has a connecting end and an open end, the connecting end being bonded to the base wall of the gear housing in co-axial alignment with the hole formed in the base wall of the gear housing. The leg housing accommodates a support leg that is free to slide in and out of the leg housing. The support leg is a hollow tube of rectangular cross section having an upper end and a lower end with a ball nut bonded inside the upper end of the support leg. There is a stabilizing foot attached to the lower end of the support leg and the ball nut has internal threads.

Abstract: In a vineyard or the like, a system for positioning and tensioning the wires which form the trellis disposed between and among an array of metal posts upon which vines are trained, including retainers for selectively positioning wires relative to the metal posts and each other and further including a subsystem for applying the appropriate tension to the various wires making up the trellis.

Abstract: A roller lifting device for lifting a track roller of a vehicle equipped with tracks, each track being formed by a plurality of chain links connected in twos by means of connectors. This roller lifting device includes a lifting arm, one end of which co-operates with the axis of rotation of a roller mounted in rotary manner on a rocker and the other end of which is mounted pivotally on a shoe fixed temporarily to a connector located on the inside of the said track. This device also includes a second shoe fixed temporarily to that connector which is axially opposed to the connector to which the first shoe is fixed, and a coupling between the first and second shoes to keep the axial spacing between the shoes constant once the latter have been positioned on their respective connector and throughout the lifting operation so that the safety of the operation is ensured.

Abstract: A portable fencing system for creating a temporary or semi-permanent barrier or boundary comprising a selected, substantially continuous section of generally flat, flexible fencing material being a selected length and width and a selected number of supports parts having a length and a base at one end, said fencing material comprising at least one reflective strip along said length and an active lighting. The system may further comprise a power source, and a container for transportation and/or storage of the system. In some embodiments, the system may comprise these parallel reflective strips equally spaced across the width. In some embodiments, the active lighting may comprise a single lighting element comprising a number of interconnected light emitting sources, and in other embodiments, a number of discrete light emitting sources. In any case, the lighting may be processed by a suitable power source such as alternating or direct current, one or more batteries, a generator, photo-cells and the like.

Abstract: The invention relates to a process for providing semiconducting device comprising the steps of depositing a semiconducting layer onto a substrate by heating a gas to a predetermined dissociation temperature so that the gas dissociates into fractions, whereby these fractions subsequently condense on the substrate to build up a semiconducting layer.

Abstract: A display device has an array of pixels (10) comprising light emitting display elements (20), for example EL elements, carried on a substrate (50) and associated light sensing elements (40) responsive to light emitted by the display elements. The light sensing elements each comprise a gated photosensitive thin film device such as a TFT structure or a lateral gated pin device having a semiconductor layer (52) with contact regions (53, 54) laterally spaced on the substrate and separated by a gate controlled region (55). A part of the associated display element (20) extends over the gate controlled region with an electrode (70) of the display element serving as the gate of the photosensitive device thereby ensuring good optical coupling between the display element and the photosensitive device and enabling the gate to be appropriately biased. Such an arrangement enables, for example, the provision of electro-optic feedback control in the pixel in comparatively simple manner.

Abstract: Two charge transfer passages of one TFT, which comprise two areas with island layers of p-Si intersecting at right angles and running from respective drain areas ND, PD to source areas NS, PS through an LD area LD and a channel area CH, are arranged non-parallel to each other. Even if a defective crystallization area R, which is caused due to uneven intensity in an irradiated area in laser annealing for forming p-Si of a p-Si TFT LCD, passes across the TFT area, and either of the transfer passages is defective, the remaining one operates normally, and the component characteristics are maintained as desired.

Abstract: A read data line pair is arranged for every four memory cell columns. Column selection in data reading is carried out by four sub read source lines. A write data line pair is arranged for every eight memory cell columns. Column selection in a data write operation is carried out by eight sub write activation lines. By differentiating the number between the read data line pairs and the write data line pairs and the corresponding memory cell columns, the wiring pitch of the data lines can be alleviated to suppress parasitic capacitance while avoiding significant increase of the signal lines to execute column selection.

Abstract: There are provided the steps of preparing a conductive foil and then forming a plurality of conductive paths by forming isolation trenches, which are shallower than a thickness of the conductive foil, in the conductive foil except at least areas serving as the conductive paths, fixing respective photo semiconductor chips (65) to desired conductive paths, molding a light transparent resin (67) serving as a lens to cover respective photo semiconductor chips (65) individually and to fill the isolation trenches, and removing the conductive foil on the side on which the isolation trenches are not provided. Therefore, a light irradiating device (68), in which back surfaces of the conduction paths can be connected to the outside to thus eliminate through holes and which has the good radiation characteristic, can be implemented.

Abstract: A semiconductor device facilitates preventing hot carriers from being injected into the insulation film so that the characteristics and the reliability of the active region thereof may not be impaired. The device includes an alternating-conductivity-type drain including heavily doped p-type breakdown voltage limiter regions in the portions of p-type partition regions in contact with the well bottoms of p-type base regions. Since the electric field in the central portion of breakdown voltage limiter regions reaches the critical value in advance to the electric field at the points E beneath gate insulation films the electric field at the points E is relaxed and hot carrier injection into gate insulation films is prevented.

Abstract: In a SDRAM, there is introduced a control signal going active low following a passage of a predetermined period of time after a sense amplifier activation signal goes active high. When a signal going high during a burst period goes low and the control signal also goes low, a word line is dropped, non-selected low. As such, paired bit lines can have a potential difference sufficiently amplified to allow data to be satisfactorily rewritten into a memory cell.

Abstract: In a semiconductor integrated circuit device including a plurality of semiconductor devices formed on a substrate, the principal plane of the substrate is partitioned into a plurality of device regions and into a plurality of routing regions each crossing a boundary between the plural device regions. A device group including one or more semiconductor devices among the plural semiconductor devices and a local interconnect for connecting the semiconductor devices included in the device group are disposed within the plural device regions. A global routing for connecting the device groups to each other is disposed within each of the plural routing regions.

Abstract: Image sensors are known in the art and are for example used in cameras to collect the image.

Abstract: A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight.

Abstract: Grey scale linearity and power efficiency in active matrix (O) LEDs are enhanced by storing the grey value in a memory circuit, coupled to an adjusting circuit, preferably via a current mirror.

Abstract: A source region and a drain region are formed in a silicon substrate, a dielectric film is formed above a region of the silicon substrate between the source region and the drain region, a ferroelectric film is formed on the dielectric film, and a gate electrode is formed on the ferroelectric film. The ferroelectric film and the silicon substrate have a first conductivity type, and the source region and the drain region has a second conductivity type.

Abstract: A ferroelectric or high dielectric constant capacitor having a multilayer lower electrode comprising at least two layers—a platinum layer and a platinum-rhodium layer—for use in a random access memory (RAM) cell. The platinum layer of the lower electrode adjoins the capacitor dielectric, which is a ferroelectric or high dielectric constant dielectric such as BST, PZT, SBT or tantalum pentoxide. The platinum-rhodium layer serves as an oxidation barrier and may also act as an adhesion layer for preventing separation of the lower electrode from the substrate, thereby improving capacitor performance. The multilayer electrode may have titanium and/or titanium nitride layers under the platinum-rhodium layer for certain applications. The capacitor has an upper electrode which may be a conventional electrode or which may have a multilayer structure similar to that of the lower electrode. Processes for manufacturing the multilayer lower electrode and the capacitor are also disclosed.

Abstract: A ferroelectric or high dielectric constant capacitor having a multilayer lower electrode comprising at least two layers—a platinum layer and a platinum-rhodium layer—for use in a random access memory (RAM) cell. The platinum layer of the lower electrode adjoins the capacitor dielectric, which is a ferroelectric or high dielectric constant dielectric such as BST, PZT, SBT or tantalum pentoxide. The platinum-rhodium layer serves as an oxidation barrier and may also act as an adhesion layer for preventing separation of the lower electrode from the substrate, thereby improving capacitor performance. The multilayer electrode may have titanium and/or titanium nitride layers under the platinum-rhodium layer for certain applications. The capacitor has an upper electrode which may be a conventional electrode or which may have a multilayer structure similar to that of the lower electrode. Processes for manufacturing the multilayer lower electrode and the capacitor are also disclosed.

Abstract: A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. Subsequently, shallow P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.

Abstract: A memory merged logic (MML) semiconductor device of NMOS and PMOS dual gate structure including embedded memory of a self-aligned structure and a method of manufacturing the same, wherein in the MML semiconductor device, the memory area including n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS) are integrated together, wherein the memory area includes a polycide gate electrode, a hard mask pattern comprised of nitride materials which is formed on the polycide gate electrode, a spacer comprised of nitride materials formed along the sidewall of the polycide gate electrode, and a self-aligned contact which is formed between the adjacent spacers and electrically connected with an impurity implantation region formed on a semiconductor substrate. The logic area includes salicided NMOS and PMOS gate electrodes and salicided source/drain regions, and the height of the polycide gate electrode is smaller than the height of the NMOS and PMOS gate electrodes.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells, said adjacent memory cells being isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual of said adjacent memory cells is ideally equal to less than 8F2, where “F” is no greater than 0.

Abstract: A SOI semiconductor device comprises: a SOI substrate in which a buried dielectric film and a surface semiconductor layer are laminated; at least one well formed in the surface semiconductor layer; and at least one transistor which is formed in the well and has a channel region and source/drain regions in the surface semiconductor layer, wherein the well is completely isolated in the surface semiconductor layer and has a well-contact for applying a bias voltage to the well, the transistor is isolated by a device isolation film formed in a surface of the surface semiconductor layer, the channel region is partially depleted, and the surface semiconductor layer under the source/drain regions is fully depleted.

Abstract: There is proposed a vertical cell transfer transistor comprising a channel region constituted by a monocrystalline silicon layer which is formed by way of epitaxial growth, source-drain regions constituted by n-type diffusion regions which are formed over and below the monocrystalline silicon layer, and an embedded type gate electrode constituted by a word line. In this case, the surface of the insulating film is made flush with the top surface of the n-type diffusion region, i.e. substantially flat and hence free from a stepped portion.

Abstract: A nonvolatile semiconductor memory device featuring a reducing operating voltage while maintaining a good disturbance characteristic and high speed in a write operation, including a gate insulating film and gate electrode stacked on a channel forming region of a semiconductor provided on the surface of a substrate and planarly dispersed charge storing means such as carrier traps in a nitride film or near the interface with the top insulating film, provided in the gate insulating film, the gate insulating film including an FN tunnel film having a dielectric constant larger than that of a silicon oxide film and exhibiting an FN electroconductivity, whereby the thickness of the gate insulating film, converted to that of a silicon oxide film, can be reduced and the voltage can be reduced.

Abstract: The present invention prevents a charge-up during a wiring layer etching in a nonvolatile semiconductor storage apparatus having a floating gate and a control gate to which both of positive and negative voltages are applied during a memory cell operation.

Abstract: A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.

Abstract: A semiconductor device is fabricated by injecting fluorine into a region of a semiconductor substrate other than a region of the semiconductor substrate where a thinnest gate insulating film is to be formed, among a plurality of regions where gate insulating films are to be formed. Then, the semiconductor substrate with fluorine injected therein is oxidized to form an oxide film in the plurality of regions. A surface of the oxide film is nitrided to turn a surface layer thereof into an oxynitride film or form a nitride film on the surface of the oxide film. The semiconductor device has a plurality of gate insulating films of different thicknesses which contain nitrogen in their surface layers.

Abstract: In a semiconductor device which has capacitors means respectively connected to multiple input terminals, and in which the remaining terminals of the capacitors are commonly connected to a sense amplifier, the capacitors and the sense amplifier are formed by utilizing a semiconductor layer on an insulating surface, whereby high-speed, high-precision processing of signals having a large number of bits supplied from the multiple input terminals is realized by a small circuit scale.

Abstract: Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).

Abstract: A partially-depleted Silicon-on-Insulator (SOI) substrate with minimal charge build up and suppressed floating body effect is disclosed, as well as a simple method for its fabrication. A thin Si/Ge epitaxial layer is grown between two adjacent epitaxial silicon layers of a SOI substrate, and as part of the silicon epitaxial growth. The thin Si/Ge epitaxial layer introduces misfit dislocations at the interface between the thin Si/Ge epitaxial layer and the adjacent epitaxial silicon layers, which removes undesired charge build up within the substrate.

Abstract: A method to obtain the same effect as that of burning in at an operating frequency of a high-frequency transistor by burning in at a frequency lowers than the operating frequency.

Abstract: A semiconductor integrated circuit has a logic circuit operated at a small power supply voltage of about 0.5V, wherein a noise margin of the logic circuit can be set at a larger value even if characteristics of the circuit vary depending upon manufacturing process conditions. Satisfactory speed can be ensured during an operation and power consumption can be reduced during a stand-by time. This is attained by controlling individual potentials of first and second conductivity type wells in which a logic circuit is formed. For this purpose, two voltage supply circuits for controlling voltages of the wells and a logic threshold voltage generator are provided.

Abstract: A data storage cell that is stable on standby but upsets on read. Standby stability is achieved without read and restore. In one embodiment, the leakage current is balanced by manipulating the transistor widths and lengths, making the subthreshold current of the pass transistor greater than that of the drive transistor. A write-back during the read cycle compensates for the read upset.

Abstract: A manufacturing method for a semiconductor memory device is provided, which comprises the steps of forming buried layers 2 for bit lines, forming gate electrodes 3 which cross the buried layers 2 at a right angle, and depositing an interlayer insulating film 5 (C). Ion injection windows are opened through the interlayer insulating film on the channel regions of every memory cell using a regular reticule pattern (D). A photoresist film 7 in conformity with the code pattern is formed and ion injected layer 8 is formed at a prescribed channel region for writing information. It becomes possible to form the ion injection windows without being affected by the density of the code pattern and to inject ions at low energy. Therefore, the transverse broadening of the injection ion beam can be prevented, to prevent fluctuations of the threshold voltage of the non-selected cells.

Abstract: A dual-gate semiconductor structure including a first polysilicon layer that has a p-type region and an n-type region. The p-type region overlies the channel region of a p-channel transistor, and the n-type region overlies the channel region of an n-channel transistor. A second polysilicon layer is formed directly on the first polysilicon layer, and exhibits good adhesion with the first polysilicon layer. A metal silicide layer is deposited on the second polysilicon layer. The second polysilicon layer and the metal silicide layer are deposited in different chambers of the same equipment, without breaking vacuum (i.e., in situ). The upper surface of the second polysilicon layer is therefore relatively clean, thereby providing good adhesion between the metal silicide and second polysilicon layers. The second polysilicon layer, which is either undoped or doped with nitrogen, inhibits vertical migration of impurities in the first and second regions to the overlying metal silicide layer.

Abstract: A lower electrode 4 of a substrate 1 is continuously formed from a thin diaphragm portion 3 to a thick region 2, and independently of the lower electrode 4, an auxiliary electrode 8 is formed on the thick region 2 of the substrate 1, whereby a piezoelectric/electrostrictive film 5 is formed across the lower electrode 4 and the auxiliary electrode 8. An incomplete bonding portion of the piezoelectric/electrostrictive film 5 to the substrate 1 is eliminated on the thin diaphragm portion 3, thereby making it possible to reduce significantly a variation in vibration form.

Abstract: A semiconductor pressure sensor includes a SOI substrate composed of first and second silicon substrates. A diaphragm portion is formed by the first silicon substrate as a bottom of a recess portion formed in the second silicon substrate. Strain gauges are formed on the diaphragm portion, and a circuit portion is formed on the first silicon substrate at a region other than the diaphragm portion. ALOCOS film for isolating the strain gauges from the circuit portion is formed on the first silicon substrate outside the outermost peripheral portion of the diaphragm portion.

Abstract: A photosensitive device with a microlens array may be packaged for surface mount packaging and subsequent mass reflow processing without significantly degrading the optical performance of the microlens. The microlens may be formed using a series of heat steps of increasing time and temperature. In addition, the microlens may be bleached to prevent degradation of its optical transmissivity at temperatures normally associated with surface mount techniques.

Abstract: A semiconductor light-receiving element fabricated by using an impurity diffusion, in which a slow tail phenomenon caused in the processing of a digital signal may be suppressed. The semiconductor light-receiving element comprises a substrate including a first impurity diffused region, a first electrode provided on the bottom of the substrate, a second electrode provided on the first impurity diffused region, a second impurity diffused region provided so as to surround the first impurity diffused region with leaving a certain space therebetween, and a third electrode provided on the second impurity diffused region, wherein a reverse vias is applied to a PN junction formed by the substrate and the second impurity diffused region.

Abstract: The invention provides a semiconductor device having an active area with an angled portion. This semiconductor device comprises an active area having an angled portion, in which a semiconductor element is formed, and an isolation region formed adjacent to the active area. The angled portion of the active area includes first and second side walls and a third side wall formed in contact with the first and second side walls. A first angle between the first and third side walls and a second angle between the second and third side walls are obtuse angles.

Abstract: A package with an electrical static discharge resistor. A chip is attached on a carrier with bumps and contacts. The carrier couples with the chip through the bumps. Electrical static discharge resistors between the bumps and the contacts are on the carrier.

Abstract: A semiconductor device having a fuse evaluation circuit is provided. Fuse evaluation circuit (100) can include, a reference voltage generation circuit (110), a fuse circuit (120-n), and a fuse evaluation control circuit (130). Fuse circuit (120-n) can include a fuse (Fn) and evaluation transistor (Tn) arranged in series and providing an evaluation node (Nn) at their connection. Reference voltage generation circuit (110) can provide a reference voltage (VG1) at a control gate of evaluation transistor (Tn). Fuse evaluation control circuit (130) can vary the impedance of the evaluation transistor (Tn) by varying the potential of reference voltage (VG1). Fuse evaluation circuit (100) can evaluate the condition of fuse (Fn) accordingly.

Abstract: A semiconductor device includes a SiGe base bipolar transistor. The SiGe base bipolar transistor includes an emitter layer, a collector layer and a SiGe base layer formed of silicon containing germanium. A Ge concentration of the SiGe base layer is increased from 0% to 10% from a side of the emitter layer towards a side of the collector layer.

Abstract: To provide an evaluation chip which can eliminate the need for developing a microcomputer for mass production in addition to an evaluation chip and operate at high speeds without any limits on a chip size and the number of terminals. A microcomputer and a microcomputer scribed line are provided therein and wiring is not performed on the microcomputer on the evaluation chip. Since the microcomputer can be cut from the evaluation chip, it is not necessary to develop a microcomputer separately. Additionally, since an internal signal of the microcomputer is drawn using a glass substrate, the evaluation chip is applicable as an emulator module.

Abstract: A solid-state imaging device having a gate structure including an oxide film and a nitride film includes upper layer films (for example, a planarization film, an insulating film, and a protective film) allowing ultraviolet rays having a frequency of 400 nm or less to pass therethrough; and a metal made shield film or an organic film capable of absorbing the ultraviolet rays formed in such a manner as to cover a region of the gate structure (for example, an output gate and a reset gate), excluding a light receiving portion and a transfer portion, of the solid-state imaging device. With this configuration, it is possible to prevent the shift of a threshold voltage vth, and hence to enhance the reliability of the transfer or reset of electric charges.

Abstract: A method and apparatus for repair of a multi-chip module, such as a memory module, is provided where at least one redundant or auxiliary chip attach location is provided on the substrate of the multi-chip module. The auxiliary chip attach location preferably provides contacts for attachment of more than one type of replacement semiconductor chip. Accordingly, when one or more chips on the multi-chip module are found to be completely or partially defective, at least one replacement chip can be selected and attached to the auxiliary location to provide additional memory to bring the module back to its design capacity.

Abstract: A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals.

Abstract: A power module package in which a heat sink made of an insulating material is attached directly to a second surface of a lead frame, on which a down set is provided, and exposed to the outside, and a manufacturing method thereof are provided. A general rectangular plate or pre-bent plate may be used as the heat sink. The heat sink may be attached during a sealing process or through a separate process performed after the sealing process. The power module package has an improved heat radiation characteristic.

Abstract: A solid image pickup device is enclosed in an integral package comprising an upper package and a lower package, which are made of a resin and molded together with a lead frame held between the upper and lower packages, the device having outline references provided on lateral sides of the integral package. Tapered surfaces are formed along an overall side periphery of the upper package and an overall side periphery of the lower package. A plurality of holes are formed to penetrate the integral package in the vertical direction. Cutouts are formed on opposite lateral sides of the integral package to make parts of two parallel sides of the lead frame exposed to the outside, and the holes are formed in the parts of the lead frame exposed in the cutouts.