Abstract: An ECL terminating circuit, in which it is prevented that the amplitude of an output signal from an ECL outputting circuit or a PECL outputting circuit is lowered caused by that the supply voltage for the circuit has been lowered, and also it is prevented that the waveform of the output signal is deteriorated caused by that the distance of a transmission line where the output signal being high speed is transmitted is made to be long, is provided. The ECL terminating circuit consists of a PECL outputting circuit, a resistor, a transmission line, a load circuit, and a terminal element. And the terminal element is connected to the resistor in series and the resistance value of the terminal element is about 0 &OHgr; at a direct current (DC), but is made to be large at an alternating current (AC).

Abstract: A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.

Abstract: A reconfigurable device includes a plurality of function cells and a programmable interconnect network which programmably connects the function cells. The programmable interconnect network includes horizontal programmable interconnect ways and vertical programmable interconnect ways. Each horizontal programmable interconnect way includes a short horizontal programmable interconnect channel and a long horizontal programmable interconnect channel, and each vertical programmable interconnect way includes a short vertical programmable interconnect channel and a long vertical programmable interconnect channel. In the horizontal programmable interconnect way, both the short horizontal programmable interconnect channel and the long horizontal programmable interconnect channel are constructed to have “shift structure”, thereby “sector segmentation” and problems related to the sector segmentation are avoided.

Abstract: A P channel MOS transistor and an N channel MOS transistor turned on/off in response to an input signal in an active state as well as an N channel MOS transistor connected between an output node and the N channel MOS transistor and turned on/off in response to a control signal are provided. The input signal is at the L level in a standby state. The control signal is at the L level in the standby state and at the H level in the active state. This suppresses the effect of hot carriers in the active state and decreases a subthreshold current in the standby state.

Abstract: The present invention relates to a bonding option circuit and a multi-level buffer that generates a plurality of selection signals from a single selective condition applied to a bonding pad to reduce the number of required bonding pads and buffers for a semiconductor device. A multi-level buffer according to the present invention can include a variable voltage divider, a comparator circuit and a logic signal generator. The variable voltage divider produces a first voltage, a second voltage, and a third voltage having voltage levels that are changed in accordance with conditions applied to a pad preferably when the variable voltage divider is activated by a power-up signal. The comparator circuit preferably generates a first comparison result and a second comparison result by being activated by the power-up signal and comparing the first to third voltages. The logic signal generator produces a first buffer output signal and a second buffer output signal.

Abstract: An output circuit for a transmission system includes an input terminal receiving an input logical signal, a first output terminal outputting a first output logical signal having a logic corresponding to a logic of the input logical signal, a second output terminal outputting a second output logical signal having a logic corresponding to an inverted logic of the input logical signal, a first constant voltage supply circuit generating a first voltage level, a second constant voltage supply circuit generating a second voltage level, and an output logic formation circuit connected to the first and second constant voltage supply circuits. The output logic formation circuit generates the first and second output logical signals having either the first voltage level or second voltage level based on the logic of the input logical signal.

Abstract: A domino circuit may be provided with additional keeper transistors that are selectively activated when one of the input transistors in a logic structure has a low or inactive signal applied to it during the evaluation stage. Thus, the potential of the output node of the domino circuit may be maintained, improving the soft error rate.

Abstract: A data carrier (1) includes a chip (10) having a supply voltage circuit point (12), from which a supply voltage (V) can be taken, and having at least one supply voltage output (21, 22) for supplying a supply voltage (V1, V2), and having potential control means (35, 49) to which a control signal (S) can be applied and with the aid of which the supply voltage output (21, 22) can be set to different potential values in accordance with the control signal (S), and also includes at least one component (24, 29) which is spatially separated from the chip (10), which component (24, 29) has a supply voltage input (25, 30) for receiving the supply voltage (V1, V2), which the supply voltage input (25, 30) is connected to the supply voltage output (21, 22) of the chip (10) via a connection lead (27, 32).

Abstract: A logic gate includes a low noise current source coupled between a first terminal of a voltage supply and an output terminal. The low noise current source is capable of delivering a preselected voltage signal to the output terminal having a magnitude responsive to a first control signal relatively independent of the magnitude of the voltage on said first terminal of said voltage supply. At least one switching element is coupled between the output terminal and a second terminal of the voltage supply. The switching element is capable of coupling the output terminal to the second terminal of the voltage supply in response to receiving a second control signal.

Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Abstract: A sense amplifier includes a pair of differential input terminals and a pair of differential output terminals. Each of a pair of precharge circuits connects a respective one of the differential output terminals to precharge potential and has a clocking input. The precharge circuits maintains the respective differential output terminals at ground in response to a precharge state of a signal at the clocking input. The sense amplifier also may include a pair of evaluation circuits, each connecting a respective one of the differential output terminals to an evaluation potential and coupled to a respective one of the differential input terminals. The evaluation circuits may transition the respective output terminal to an evaluation voltage in response to an evaluation state of a signal at the respective differential input terminal.

Abstract: According to an embodiment of the invention, a circuit is provided that includes a first differential set and a second differential set each having a first and a second input node and a first and a second output node. The first differential set is referenced to a first supply node, and the second differential set is referenced to a second supply node. The first input node of the first differential set is coupled to the first input node of the second differential set. The second input node of the first differential set is coupled to the second input node of the second differential set. A first load element is cross coupled between the second output node of the second differential set and the first output node of the first differential set. A second load element is cross coupled between the second output node of the first differential set and the first output node of the second differential set.

Abstract: A select signal generating circuit for preventing a malfunction and an increase in the circuit area is provided. The select signal generating circuit includes a select signal generator for generating a plurality of select output signals in accordance with a clock signal in response to a reset signal provided after a predetermined time passes since power on. A power-ON detection circuit detects the power-on, generates a power-ON detection signal, and maintains the power-ON detection signal until the reset signal is provided. The select signal generator includes a clamp circuit connected to the power-ON detection circuit for clamping the plurality of select output signals to predetermined levels in response to the power-ON detection signal.

Abstract: A fractional-N-PLL frequency synthesizer that reduces the spurious caused by a phase error is provided. A reference phase error is determined from a plurality of phase errors generated between a reference signal and a comparison signal when the fractional-N-PLL frequency synthesizer is locked. Then, any phase error equal to or smaller than the reference phase error is canceled.

Abstract: A delay locked loop circuit having a duty cycle correction function and a delay locking method are provided. The delay locked loop circuit includes a delaying portion for generating a first output signal by uniformly delaying an input first clock signal and generating a second output signal by variably delaying the first clock signal and an output signal generator for generating a second clock signal, the voltage level of which increases when the first output signal is transitioned from a first logic state to a second logic state and whose voltage level is reduced when the second output signal is transitioned from the second logic state to the first logic state. Accordingly, jitter that exists in the signal output from the delay locked loop circuit is reduced.

Abstract: The charge pump, having increased precision over known charge pumps, for a self-biasing phase-locked loop and a self-biasing delay-locked loop is disclosed herein. It includes a p-type charge pump and a n-type charge pump. The charge pump has inputs for an up and a down voltage output from a phase and frequency detector and for at least two bias voltage outputs from a bias generator. The p-type charge pump is coupled to the up output of the phase and frequency detector and a first bias voltage output from the bias generator circuit. The n-type charge pump is coupled to the p-type charge pump and has inputs coupled to the down output of the phase and frequency detector and a second bias voltage output from the bias generator circuit. A first capacitor is coupled across the p-type charge pump. This charge pump operates between 1 &mgr;A to 10 &mgr;A. It is a more balanced design than known charge pump designs.

Abstract: A differential charge pump with integrated common-mode control circuitry (100) for a fully differential phase-locked loop is described, having two output lines (OUT+; OUT−) and comprising a charge pump section (103) and a common-mode feedback section (106). In the charge pump section (103), current generating means (111, 112, 113, 114) generate a first current signal having a first magnitude and a certain polarity on said first signal output (OUT+), and a second current signal having a second magnitude and opposite polarity on said second signal output (OUT−).

Abstract: A clock generation circuit includes a clock input circuit receiving complementary external clocks to generate an internal clock, a variable delay circuit delaying the internal clock to generate an internal operation clock, a replica circuit further delaying the internal operation clock by a predetermined time to generate a return clock, a phase comparator directly comparing the phase where potential levels of external clocks cross with the phase of the return clock, and a delay control circuit adjusting the delay amount of the variable delay circuit according to a phase comparison result of the phase comparator.

Abstract: A constant-voltage generation circuit 100 creates a constant voltage.

Abstract: The integrated device comprises a PMOS transistor and a voltage selector having an output connected to the bulk terminal of the PMOS transistor. The voltage selector comprises an input stage supplying a supply voltage or a programming voltage according to whether the device is in a reading step or in a programming step; a comparator connected to the output of the input stage, receiving a boosted voltage, and generating a first control signal, the state whereof depends upon the comparison of the voltages at the inputs of the comparator; a logic circuit connected to the output of the comparator and generating a second control signal, the state whereof depends upon the state of the first control signal and of a third-level signal; and a switching circuit controlled by the first control signal, by the second control signal, and by the third-level signal and supplying each time the highest among the supply voltage, the boosted voltage, and the programming voltage.

Abstract: A charge pump circuit capable of preventing coupling and charge injection without increasing a layout area and power consumption is provided. The charge pump circuit includes a pull-up current source, a pull-down current source, a first switching device, and a second switching device. The pull-up current source sources pump-up current to the output node. The pull-down current source includes a current mirror and sinks pump-down current from the output node. In particular, the first switching device is connected between a supply voltage node and the pull-up current source and is switched in response to a pump-up control signal. The second switching device is connected between the second current source and a ground voltage node and is switched in response to a pump-down control signal.

Abstract: A charge-pump circuit has means biasing electrical potential of a substrate of a MOS transistor for control M2 so that forward direction current does not flow substantially through a parasitic diode Dp1. In the concrete, the substrate of the substrate of a MOS transistor for control M2 is biased by voltage of a connecting point of the substrate of a MOS transistor for control M2 and a capacitor 1 at the case that the substrate of a MOS transistor for control M2 is P-channel type. Thus, it is prevented that a parasitic diode is biased to forward direction in a charge-pump circuit carrying out voltage fluctuation with lower voltage step than power source voltage Vdd so as to carry out normally charge-pump operation.

Abstract: By taking advantage of the ability to control the phase relationship between a processor's output (or portions of a processor's output) and the phase of the pre-processed signal, a controlled accentuation or enhancement of the processor's effect can be realized. In one embodiment this is achieved by providing a gain control circuit that receives and selectively amplifies the input signal prior to it being summed with the processor's output.

Abstract: A high performance, high-speed, cost-effective pulse width modulation circuit for the delivery of linear and efficient power to a load. The inventive aspects include: (a) removing certain MOSFET current limiting resistors and reducing impedance paths between components to decrease switching transition time; (b) providing an ultra-fast transient protection circuitry between the Gate and the Source, and between the Drain and the Source of the MOSFETs; (c) providing a hermetically sealed Faraday cage over the circuit; (d) providing a temperature sensor to monitor the temperature of the circuit; (e) providing an electrically and geometrically symmetrical circuit, having multiple pieces of interconnected substrates to reduce electrical and mechanical stress across the junctions and matching thermal coefficient of adjoining components; (f) using costly BeO material only for the substrate in the MOSFETs where most heat is generated and less costly Alumina substrate for the rest of the circuit.

Abstract: Methods and apparatus are described for generating or amplifying a differential signal. The output of a first op amp corresponds to one end of the differential signal. The output of a second op amp corresponds to the other end of the differential signal. The inverting input of the first op amp is coupled to the noninverting input of the second op amp.

Abstract: A power amplifier having a predistortion linearizer for improving the non-linear property of the power amplifier is disclosed. The powers amplifier includes a predistorter for outputting a distortion compensating signal to the high power amplifier, a delay line for delaying an input signal for a prescribed period of time and outputting a reference signal, a distortion component detection circuit for detecting a distortion component by comparing the output signal of the power amplifier with the reference signal of the delay line, and an adaptive controller for controlling the properties of the predistorter in order to minimize the detected distortion component.

Abstract: Generally, the invention relates to a method and apparatus to improve the performance of radio frequency power amplifiers. More particularly, the present invention discloses the use of a power booster in conjunction with a radio-frequency linear power amplifier to reduce intermodulation distortion of an amplified signal.

Abstract: An operational amplifier circuit includes a first differential pair, which includes first and second transistors, and a second differential pair, which includes third and fourth transistors. A fifth transistor is connected to the first and third transistors. A sixth transistor is connected to the second and fourth transistors. A first current source is connected to the first differential pair to provide a first bias current. A second current source is connected to the second differential pair to provide a second bias current. A third current source is connected to the fifth transistor to provide a third bias current. A fourth current source is connected to the sixth transistor provide a fourth bias current. A control circuit controls the first to fourth current sources such that the sum of the first and second bias currents is constant and the second to fourth bias currents become substantially equal.

Abstract: An input buffer circuit 11X is a source follower circuit and comprises a load 114 and enhancement FETs 111 and 112A connected in series between power supply lines VDD and VSS. A DC bias VB1 is applied to the gate of the FET 112A to act it as a current source, and an AC current component of the drain potential VD of the FET 111 is provided through a capacitor 113 to the gate of the FET 112A. If an inductor as an matching circuit is connected in series to the capacitor 113, a band pass filter is constructed, and the gain of the circuit 11X becomes especially high at the resonance frequency thereof. At high frequencies, the interconnection coupled to the capacitor 113 has a parasitic inductance, and the output waveform of the circuit 11X has a high frequency noise. In this case, a damping transistor is connected between the capacitor 113 and the gate of the FET 112A to obtain a flat gain by adjusting the gate potential thereof.

Abstract: The object of the present invention is to provide a bipolar transistor which is excellent in uniformity of current distribution in spite of a small ballast resistance, and can constitute an amplifier showing high efficiency and low distortion with little deterioration of distortion even when a digital modulation wave is input thereto. A high frequency power amplifier of the present invention comprises a plurality of transistor blocks having a bipolar transistor, wherein each of the transistor blocks includes a resistance connected to an emitter of the bipolar transistor, a reference voltage generation circuit for generating a reference voltage as a base bias of the bipolar transistor, and a bias generation circuit connected to a base of the bipolar transistor, the bias generation circuit generating a base bias voltage by converting the reference voltage.

Abstract: Realizing a stabilized gain slope without increasing circuit scale or entailing extra time or care for correcting impedance. A resonant circuit that is made up of a capacitor and an inductor is provided in an output stage outside a feedback loop for realizing peaking at a particular frequency and for realizing a gain slope having a desired slope of, for example, 1 dB or more.

Abstract: A phase locked loop (PLL) is used in a radio communication system such as a frequency mixer, a carrier frequency and the like. The phase locked loop (PLL) includes a phase/frequency detector for comparing a phase/frequency of a reference signal and a feedback signal. The phase/frequency detector includes: a NAND gate logic circuit for NANDing a first signal and a second signal to output a NANDed signal; a first latch unit for latching the NANDed signal and outputting the first signal in response to a reference frequency; and a second latch unit for latching the NANDed signal and outputting the second signal in response to a feedback frequency. The phase locked loop (PLL) further includes a filter controller for changing a bandwidth of a low pass filter in response to an output signal of the phase/frequency detector.

Abstract: A frequency synthesizer is provided with a prescaler 2 and a counter 3, which output a signal having a frequency generated by frequency-dividing an output signal of a VCO 1; a reference frequency divider 5 for frequency-dividing a frequency of a reference signal of a reference signal source 4; a frequency adjusting meas 9 operated in such that a frequency error between the output signal of the counter 5 and the output signal of the reference frequency divider 5 is detected, and in response to this detection result, such a signal is outputted by which either a capacitor value or an inductor value employed in a resonant circuit of the VCO 1 is switched; and also a bias control means for applying an arbitrary voltage V1 to a control voltage terminal of the VCO 1 so as to bring an output signal of a charge pump 7 into a high impedance state when the frequency adjusting means 9 is operated.

Abstract: When output signals of an oscillator are binarized by binarization means, a timing signal for driving a sequence controller for controlling a correction portion is rested temporarily. The process for overwriting the contents of an E2ROM of the correction portion side with an RAM is rested temporarily. This can prevent noise produced at the overwriting timing. Binary signals after binarization can be prevented from being varied. The oscillator can be driven stably so as to give an angular speed output with high accuracy.

Abstract: A magnetron has an output comprising a coaxial line 15 which transmits energy from a wanted oscillator mode as a first coaxial waveguide mode and energy from an unwanted oscillator mode as a second cylindrical waveguide mode. Energy in the cylindrical waveguide mode is intercepted by slots 17, 18 in the coaxial line 15 and absorbed by material 19. This enables the modes to be separated. Preferably, the output is taken from the axis of the magnetron and the wanted oscillator mode in the &pgr;-1 mode.

Abstract: A voltage-controlled oscillator (VCO) using a transistor, capable of using a capacitor for DC blocking with small capacitance and achieving a large amount of change in the oscillating frequency. The voltage-controlled oscillator comprises a transistor for oscillation and amplification, first and second nodes, a quartz-crystal element inserted between the first and second nodes, a first capacitor connecting the first node with a base of the transistor, a second capacitor connecting the second node with a collector of the transistor, a first variable capacitance diode connected to the first node, a second variable capacitance diode connected to the second node, and means for applying a control voltage to the first and second variable capacitance diodes.

Abstract: When a PWM signal is generated by PWM generators which are provided for the number of channels, each PWM generator outputs the PWM start schedule data showing the timing of startup of the PWM signal to the CPU. When the number of PWM signals which start at substantially the same time exceeds a predetermined number on the basis of the PWM start schedule data, the CPU outputs delay setting data with respect to a channel corresponding to a portion exceeding the predetermined number to the PWM generator as the one showing that the generation of the PWM signal is to be delayed. The PWM generator delays the PWM signal, when the delay setting data shows a delay. As a result, a multi-channel pulse width modulation apparatus which can prevent a decrease in the operational reliability due to simultaneous start of the pulse width modulation signals can be provided.

Abstract: A material for a bismuth substituted garnet thick film comprising Gd, Yb, Bi, Fe and Al as the main ingredient grown by a liquid phase growing method on a garnet substrate in which the composition of the garnet thickness is represented by the general formula:

Abstract: Various bus trace topologies are provided which allow for shorter stub lengths, reduced motherboard costs, more efficient routing between multiple agents, and bus traces with better matched characteristic impedances.

Abstract: An antenna duplexer has a first filter and a second filter coupled to respective signal terminals and to a common node. The common node is coupled to an antenna terminal. The first filter has a higher-frequency passband than the second filter. A transmission-line circuit, inserted between the first filter and the common node, increases the impedance of the first filter in its lower stopband. The transmission-line circuit includes an internal node, a first transmission line coupling the internal node to the common node, a second transmission line coupling the internal node to the first filter, and a grounding circuit such as a capacitor coupling the internal node to ground. The grounding circuit further enhances the lower stopband impedance of the first filter.

Abstract: A ladder filter comprises series and shunt resonators (2,4). The or each shunt resonator (4) has a static capacitance which is more than four times the static capacitance of the input or output series resonators (2i,2o). This provides increased shunt resonator capacitance which reduces the effective coupling across the a series-shunt section, thereby enabling a smaller number of series-shunt filter sections to used to achieve good stop-band rejection, while still providing good performance in the pass-band. The invention is based on the recognition that filter bandwidth can be traded for improved out-of-band rejection.

Abstract: A plurality of resonators 50 are formed in a dielectric porcelain block 42, wherein each of the resonators 50 is formed by coating an interior surface of a through section with an interior conductor 54, thus constituting a dielectric filter 41. On a side surface 44 of the dielectric block 42 perpendicular to an open end face 43 having the through sections formed therein, there are formed protrusions 45 having a height L lower than that of the through sections. Terminal electrodes 60a and 60b are defined with the protrusions 45 taken as a boundary between the terminal electrodes 60a and 60b, and isolated. from an exterior' conductor 62.

Abstract: The resonator of the present invention includes a cylindrical dielectric and a conductor film covering the surface of the dielectric in close contact therewith. The conductor film is constructed of a cylindrical portion and two flat portions, and is formed by subjecting the surface of the dielectric to metallization or the like. With the conductor film formed in close contact with the dielectric, deterioration of the Q value and the like caused by instability of connection at the corners can be suppressed even when a radio frequency induced current flows from the cylindrical portion over the two flat portions.

Abstract: An electromagnetic actuator includes an external movable plate formed integrally with a semiconductor substrate. A first torsion bar movably supports the movable plate with respect to the semiconductor substrate. An internal movable plate is disposed inside the external movable plate. A second torsion bar rotatably supports the internal movable plate relative to the external movable plate, and is positioned at a right angle relative to the first torsion bar; and further includes a single turn first driving coil extending around the external movable plate; a single turn second driving coil extending around the internal movable plate, and which is connected in series with the first driving coil; magnetic field generating means for applying a magnetic field to the first and second driving coils; and an optical element having an optical axis and located on the internal movable plate.

Abstract: In an electric apparatus, insulating cylinders having different diameters are arranged in a shape of multiple cylinders between the iron core and the low voltage winding, between the low voltage winding and the high voltage winding and on the periphery of the high voltage winding. Spacers are separately arranged between layers of the plurality of insulating cylinders to form a plurality of insulating medium paths. A flow stopping member for stopping the flow of the insulating medium in the insulating medium paths which is made of an insulating material with a low density is arranged at at least one of the upper and lower ends of each of the insulating medium paths.

Abstract: An ignition coil for motor vehicles, comprising:

Abstract: This invention relates to the planarization of inductive components by reducing standard coiled designs to single turn designs from which the required parameters are obtained by scaling the length. Single turn designs having magnetic material encircling the conductors along their full length enable the thinnest form. The single turn form also enables the inductive component to be routed according to any shape in the plane or on any conformal surface. The single turn inductors do not need to coil hence there is no overlap necessary in the plane. The planar form allows integration of inductive components with integrated circuits. These inductive components can be embedded in other materials. They can also be fabricated directly onto parts.

Abstract: An adhesive composition includes a mixture of a ferrite powder and a liquid matrix resin that contains at least one of (A) a polyamic acid and (B) a resin which has an imide bond, is capable of an addition reaction with an amine or capable of self-polymerization, and is capable of dissolving in an organic solvent. The adhesive composition uses a thermally stable polyimide resin and can contain a ferrite powder in a sufficiently high density as to form a satisfactorily closed magnetic circuit structure.

Abstract: The vehicle port control system comprises a capaciflective sensor, a port, a lock securing the port, and a control unit. The capaciflective sensor senses the presence of objects a predetermined distance from the vehicle port. The sensor communicates its readings to the control unit, which controls the actuation of the lock.

Abstract: A pageable electronic badge including a laminate display of electronic ink energized by plastic transistors wearable by a user such that the user can be paged within a wireless LAN conforming to wireless LAN standard IEEE 802.11.