Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure comprising a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

Abstract: An interlayer insulating film and a first via connected to a diffusion layer in a MOS transistor are formed on the diffusion layer. Then, a low dielectric constant film for a first layer copper interconnection, and the first layer copper interconnection connected to the first via are formed. Then, an etching stopper film, an interlayer insulating film, and a low dielectric constant film for a second layer copper interconnection are formed in this order. Then, a via hole is formed in the etching stopper film and the interlayer insulating film, and a groove is formed in the low dielectric constant film for the second layer copper interconnection. A barrier metal layer is then formed. Thereafter, Ar ions are implanted. At the time, the implantation energy is 50 keV, and the dose is 1×1017 cm−2. A second via and the second layer copper interconnection are formed, and annealing is performed at a temperature of 400° C.

Abstract: An embodiment of the instant invention is a method of forming a electrically conductive structure insulatively disposed from a second structure, the method comprising: providing the second structure; forming the electrically conductive structure of a material (step 118 of FIG. 1) that remains substantially conductive after it is oxidized; forming an electrically insulative layer (step 116 of FIG. 1) between the second structure and the conductive structure; and oxidizing the conductive structure by subjecting it to an ozone containing atmosphere for a duration of time and at a first temperature.

Abstract: A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

Abstract: A method for forming a gate stack having a silicide layer that can subsequently undergo a SAC etch is disclosed. The present method provides a layer of insulating material on top of the silicide layer. The insulating material is sufficient to protect the gate stack, including the silicide layer when the low-resistance gate stack is used in subsequent self-aligned contact etch processes.

Abstract: The present invention is a method of fabricating interconnects. A semiconductor substrate having a dielectric layer is provided. The dielectric layer has a via opening therein, which exposes the semiconductor substrate. Next, the surfaces of the via opening is covered with a conformal titanium layer formed by a sputtering process. The surface of the conformal titanium layer is covered with an Al—Si—Cu alloy layer formed by a sputtering process at a temperature of about 0° C. to 200° C. Then, the surface of the Al—Si—Cu alloy layer is covered with an Al—Cu alloy layer formed by a sputtering process at a temperature of about 380° C. to 450° C., which Al—Cu alloy layer fills the via opening. The Al—Cu alloy layer, the Al—Si—Cu alloy layer and the wetting layer on the dielectric layer are patterned by photolithography and etching process.

Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.

Abstract: A method of forming a bump, comprising: a first step of bonding a ball-shaped tip portion of a conductive wire to an electrode by a first tool so that a portion of the tip portion, positioned around a central portion that leads to the conductive wire and avoiding an outer peripheral portion, is pressed and plastically deformed by the first tool; a second step of tearing off the conductive wire in such a manner that the tip portion remains on the electrode; and a third step of pressing at least the central portion of the tip portion by a second tool to cause plastic deformation.

Abstract: A method of manufacturing a metal wiring in a semiconductor device is disclosed. The method comprises forming a photosensitive film so that an underlying metal wiring can be exposed, adhering an chemical enhancer only to the underlying metal wiring, depositing a metal layer by CECVD method so that the metal layer is selectively deposited at the portion in which the chemical enhancer is formed, removing the photosensitive film and chemical enhancer, and forming a diffusion barrier layer spacer at the sidewall of the metal layer to form an upper metal wiring. Therefore, the disclosed method can solve poor contact with an underlying metal wiring due to shortage of processional margin in the process of forming an upper metal wiring in a high integration semiconductor device.

Abstract: Improved methods for manufacturing semiconductor devices incorporating barrier layers at metal/dielectric interfaces include the use of nitrogen-rich plasma, ion beam implantation and/or electromagnetic radiation to form regions of nitrided metal. The barrier layers decrease the diffusion of dopants such as fluorine, phosphorous and boron from the dielectric material into the metal, thereby decreasing the formation of metal salts. By decreasing the formation of metal salts, the barrier layers of this invention decrease the formation of voids and areas of delamination, and thereby decrease the loss of electrical reliability during manufacture and during use. Additional aspects of this invention include methods for monitoring the deposition of thin metal films using sheet resistance measurements, and further embodiments of this invention include methods for monitoring the surface texture of films that undergo phase transitions.

Abstract: According to a method of manufacturing a MIS semiconductor device of the present invention, a gate insulating film is formed on a silicon substrate, and a silicon thin film is deposited on the gate insulating film, whereafter a silicon film containing germanium is deposited on the silicon thin film and an amorphous silicon film is deposited on the germanium-containing silicon film. Further, heat treatment is performed to diffuse the germanium in the germanium-containing silicon film into the silicon thin film, and a metal film is deposited on the amorphous silicon film and heat treatment is performed to cause a silicidation reaction to occur with the metal film to form a silicide film. Therefore, the germanium-containing silicon film which can control gate depletion can be formed stably with a good reproducibility. Further, since the silicide film on the gate electrode is formed on the silicon film, it can be formed with a low resistance.

Abstract: A method for manufacturing a copper interconnection includes the steps of preparing an active matrix provided with a substrate, an insulating layer and an opening formed with a predetermined shape through the insulating layer, forming a first aluminum oxide layer on surfaces of the opening and the insulating layer, forming a first conductive barrier layer on the first aluminum oxide layer, forming a copper layer into the opening and on the first conductive barrier layer, polishing back the copper layer to a top surface of the insulating layer, thereby obtaining a copper interconnection within the opening and a first double diffusion barrier layer provided with the first aluminum oxide layer and the first conductive barrier layer, and forming a second diffusion barrier layer on the copper interconnection and the insulating layer.

Abstract: A method of manufacturing a copper metal wiring in a semiconductor device, by which a plasma process is performed before a diffusion barrier layer is formed and a chemical pre-process using a chemical enhancer is performed so that copper is deposited to form a metal wiring by a chemically enhanced chemical vapor deposition (CECVD) method. The method allows the chemical enhancer to be adhered on the diffusion barrier layer uniformly and stably; therefore, improving the deposition property of a copper thin film.

Abstract: A process for removing photoresist material without any residues left and damage to the in-process substrate is described. The present process for removing photoresist on an in-process substrate comprises the steps of providing a cover layer which is to be etched on the in-process substrate and providing a layer of photoresist material thereon. The photoresist layer is patterned, exposed and developed. Then, the developed photoresist layer is further exposed without using a mask. The cover layer is etched with the use of the patterned photoresist layer. After etching, the photoresist material is removed by a solvent.

Abstract: A charged particle beam uniformly removes material, particularly crystalline material, from an area of a target by compensating for or altering the crystal orientation or structure of the material to be removed. The invention is particularly suited for FIB micromachining of copper-based crystalline structures. Uniformity of material removal can be improved, for example, by passing incoming ions through a sacrificial layer formed on the surface of the material to be removed. The sacrificial layer is removed along with the material being milled. Uniformity of removal can also be improved by changing the morphology of the material to be removed, for example, by disrupting its crystal structure or by altering its topography.

Abstract: A chemical-mechanical polishing apparatus has a surface formed on a solid aggregate comprising a solid suspension of abrasive particles in a light sensitive material. An ultraviolet light source exposes a thin top layer of the surface and a developing fluid develops the exposed surface. The developing fluid dissolves the UV-exposed top portion of the aggregate and a polishing slurry is formed of the developing fluid and the released abrasive particles. The aggregate surface remaining after developing acts as a polishing surface. The polishing slurry is used during chemical-mechanical polishing of a processed semiconductor wafer. After polishing, a rinsing fluid is dispensed to remove used slurry from the polishing aggregate.

Abstract: SOI substrates are fabricated with sufficient quality and with good reproducibility. At the same time, saving of resources and reduction of cost are realized by reuse of wafer and the like.

Abstract: A system of etching using quantum entangled particles to get shorter interference fringes. An interferometer is used to obtain an interference fringe. N entangled photons are input to the interferometer. This reduces the distance between interference fringes by n, where again n is the number of entangled photons.

Abstract: Disclosed is a process for removing doped silicon dioxide from a structure selectively to undoped silicon dioxide. A structure having both doped and undoped silicon dioxide regions is exposed to a high density plasma etch having a fluorinated etch chemistry. Doped silicon dioxide is preferably removed thereby at a rate 10 times or more greater than that of undoped silicon dioxide. The etch is conducted in a chamber having an upper electrode to which a source power is applied and a lower electrode to which a bias power is applied sufficient to generate a power density on a surface of the structure such that the source power density is in a range less than or equal to about 1000 W per 200-mm diameter wafer surface. The high density plasma etch has an ion density not less that about 109 ions/cm3. A variety of structures are formed with the etch process, including self-aligned contacts to a semiconductor substrate.

Abstract: A method for etching material which does not readily form volatile compounds in a plasma includes providing a plasma etch chamber including a wafer electrode at an initial temperature. The wafer electrode supports a wafer, and the wafer includes a layer of the material which does not readily form volatile compounds in plasma. The wafer is bombarded with charged particles from a plasma generated in the plasma etch chamber to impart thermal energy to the wafer. A reactive gas flow is provided to react with etch products of the material. Bias power is applied to the wafer electrode to impart bombardment energy to the charged particles incident on the wafer from the plasma such that a predetermined temperature is generated on a surface of the wafer wherein the wafer electrode is maintained at about the initial temperature.

Abstract: The invention describes a method for lowering particle count after tungsten etch back, in which method a plasma ashing step is performed after a brush cleaning step to eliminate polymer residues that remain on the metal barrier layer after tungsten etch back. Another tungsten etch back process is further performed to remove a tungsten oxide film that is formed by reacting the tungsten layer with an O2 gas used in the plasma ashing step.

Abstract: In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the insulative layers sandwiched between layers of metal wiring—in integrated circuits. Accordingly, the inventor devised several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization and methods of modifying metal layout patterns to facilitate formation of dielectric layers with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.

Abstract: A crystalline silicon thin film transistor having an LDD (lightly doped drain) structure and a process for fabricating the same, which comprises introducing a catalyst element for accelerating crystallization at a concentration of 1×1015 cm−3 or more but less than 2×1019 cm−3 to the impurity region in an amorphous silicon film, crystallizing the amorphous film thereafter, and after forming gate electrode and gate insulating film, implanting an impurity in a self-aligned manner to establish an LDD structure.

Abstract: The present invention relates to a semiconductor device manufacturing method for forming an interlayer insulating film having a low dielectric constant by coating a copper wiring. In configuration, in a semiconductor device manufacturing method of forming an insulating film 25 having a low dielectric constant on a substrate 21, the insulating film 25 is formed by plasmanizing a film forming gas containing any one oxygen-containing gas of N2O, H2O, and CO2, ammonia (NH3), and at least one of an alkyl compound having a siloxane bond and methylsilane (SiHn(CH3)4-n: n=0, 1, 2, 3) to react.

Abstract: In a method of manufacturing an aluminum oxide film using atomic layer deposition, alcohol is delivered as an oxygen source instead of water vapor into a reactor via a different delivery line from an aluminum source. Thus, the disclosed method can prevent degradation of an aluminum oxide thin film in uniform fashion by a chemical vapor deposition method that is parasitically generated. Also, an activation gas is delivered into the reactor at about the same time an aluminum source and an alcoholic gas is delivered. Therefore, the disclosed method can prevent reduction in the deposition rate and also prohibit degradation in an electrical property by impurity.

Abstract: A method of manufacturing multilayer electronic parts including a processing step asnd an apparatus for manufacturing multilayer electronic parts including a processing apparatus for subjecting a green sheet to a predetermined processing by irradiating it with the laser beam. A green sheet attached to the periphery of one of two drums is subjected to the predetermined processing by irradiating it with the laser beam from a beam irradiation means while allowing the drum to rotate about a drum's centerline as an axis and travel in the direction of the drum's centerline. And while subjecting the green sheet to the processing, processed green sheets are detached from the periphery of the other drum and unprocessed green sheets are attached to it with a sheet attaching/detaching means.

Abstract: The occurrence of defects of a semiconductor device at the time of transportation is prevented by the present invention relates to a transportation method for a semiconductor device which uses, for transportation of a semiconductor device from the departure point to the arrival point, the transportation route B1+B2 wherein the cosmic ray concentration is the smallest among a plurality of transportation routes A and B1+B2 from the departure point to the arrival point.

Abstract: A nitride semiconductor substrate including (a) a supporting substrate, (b) a first nitride semiconductor layer having a periodical T-shaped cross-section, having grown from periodically arranged stripe-like, grid-like or island-like portions on the supporting substrate, and (c) a second nitride semiconductor substrate covering said supporting substrate, having grown from the top and side surfaces of said first nitride semiconductor layer, wherein a cavity is formed under the second nitride semiconductor layer.

Abstract: A controller in which a dead space for wiring is reduced, its input-and-output response time is shortened, and miniaturization and cost reduction is ensured. A RS-232 connector connection unit (6) and a peripheral connector connection unit (7) are lowered than a projection (4) provided with displays (121, to 124) so that a cable connector does not exceed the projection (4) when the connector is mounted on the connector connection units (6) and (7).

Abstract: A method and apparatus for interconnecting at least two devices. Each of the interconnected devices includes a contact structure for electrically and/or physically interconnecting the devices. Preferably, the contact structure for at least one of the devices includes a spring contact. An adhesive, such as a UV-curable adhesive, is applied to at least a portion of one of the devices, and once the adhesive is applied, the devices are assembled, i.e., brought into sufficient proximity so that the contact structures interconnect the devices. The adhesive can be applied directly to contact structures of one of the devices and/or can be applied to other portions of the devices so that the adhesive flows around the contact structures during assembly. The adhesive is then cured to bond the devices together.

Abstract: A connector-with-lever comprising a first connector (11), a second connector (12) and a lever (14) turnably mounted to a connector housing (13) of the first connector (11), in which the first connector (11) and the second connector (12) are connected to each other by operating the lever (14), wherein the connector-with-lever further comprises lever locking means (18A), (23) for temporarily lock the lever (14) with the connector housing before the first connector (11) and the second connector (12) are connected to each other, and unlocking means (28) for unlocking the temporary locking state of the lever (14) when the first connector (11) and the second connector (12) start being connected to each other.

Abstract: The structure of a card connector device is disclosed which is provided with a detector switch of a simple configuration for identifying write inhibit for an IC card and which as a whole can be reduced in thickness and size. The card connector device comprises a header, the header having a plurality of contact pieces to be contacted with contacts of an IC card, a frame provided with a card receptacle portion contiguous to the header, and an electrically conductive cover member attached to the frame so as to cover the receptacle portion, the frame being formed with a switch portion which is operated with insertion and ejection of the card, the switch portion comprising a contact plate which is pushed outwards with insertion of the card and a part of the cover member which is brought into abutment against the contact plate, the contact plate being brought into and out of contact with the cover member with insertion and ejection of the card.

Abstract: The invention provides a panel connector, permitted limited movement in an aperture while simultaneously preventing this connector from falling out. A female connector 20 is supported in a waiting state within a panel 10 by flanges 25 which make contact with edges of an attachment hole 11; contacting plates 52 of upper and lower pairs of resilient contacts 50, and for engagement with retaining members 12; and contacting plates 56 which engage supplementary retaining members 13. If an axis of a corresponding male connector 30 is misaligned relative to an axis of the female connector 20, some of the resilient contacts 50 bend, this causing the female connector 20 to move to align the axes of the two connectors 20 and 30. As the female connector 20 moves, the degree of engagement between some of the resilient contacts 50 is reduced.

Abstract: An interface converter module is provided for converting data signals from a first transmission medium to a second transmission medium. The module is housed within a metallized housing having a first end and a second end. A shielded electrical connector is mounted at the first end of the housing and configured to mate to a corresponding connector associated with a first transmission medium. The housing includes a flexible metallic shielded cable having extending from the second end. The remote end of the shielded cable comprises the media interface which includes and interface connector configured to the connect the flexible shielded cable to the serial transmission medium. A printed circuit board is mounted within the housing and has mounted thereon electronic circuitry configured to convert data signals from a host device transmission medium to the second transmission medium.

Abstract: A customer bridge for a terminating device includes a base defining an interior cavity and a base cap attached to the base and substantially covering the cavity. At least a pair of wire insertion holes formed through the base cap extend into the cavity for receiving twisted-pair tip and ring wires. The customer bridge further includes at least a pair of corresponding insulation displacement contacts disposed within the cavity. An actuating arm pivots between a disconnected position wherein the twisted-pair tip and ring wires do not engage the corresponding pair of insulation displacement contacts and a connected position wherein the twisted-pair tip and ring wires engage the corresponding pair of insulation displacement contacts. The wire insertion holes are located on the top surface of the customer bridge to permit the twisted-pair tip and ring wires to be inserted from immediately above the terminating device.

Abstract: A USB cable fixture for fixing a USB cable with a USB connector to a computer is composed of a base portion, an attaching portion, and a fastening portion. The attaching portion extends from the base portion in a first direction and is attached to a housing of the computer. The fastening portion extends in a second direction orthogonal to the first direction on an opposite side of the base portion to the attaching portion. The USB cable is fixed to the computer by the base portion, the fastening portion, and the USB connector.

Abstract: A circuit and method for connecting data lines to a digital communication system are disclosed. The circuit allows either a balanced data line or an unbalanced data line to be connected to a single input port with no internal reconfiguration of the system. Connection to a balanced data line isolation transformer is provided at the port. A separate connection to ground is provided at the same port. A user connects the system to a balanced data line using a jack wired for connecting the balanced data line pair across the isolation transformer. A user connects the system to an unbalanced data line using a similar jack; however, the jack in this case is wired to short one transformer connection to the ground connection provided at the port, thereby unbalancing the transformer. In one embodiment, this second jack is part of a patch cable which accepts a coaxial connector on one end, appropriately wired to the shorted jack on the second end.

Abstract: In a socket for electrical parts, a number of contact pins contacting a number of terminals of an electrical part are arranged, in grid shape, to a socket body in which the electrical part is accommodated, and a guide member is provided for the socket body for guiding a peripheral edge portion of the electrical part to a predetermined position of the socket body. The guide member is formed with an accommodation space into which the electrical part is guided and accommodated and has first and second mount positions apart by substantially 180° from each other, and the position of the accommodation space with respect to arrangement region of the contact pins on the side of the socket body is made variable by changing the mounting position of the guide member.

Abstract: Disclosed is a coaxial cable connector plug including a connector body having the end of a coaxial cable fixed therein and a housing having an insertion hole to accommodate the connector body. The housing has a cantilever-like engagement nail extending in the insertion hole, thereby permitting the connector body to be caught by the frusto-conical transition in the insertion hole. The housing has a catch hole made in the vicinity of the cable-inlet of the housing. When a wedge-like retainer is inserted into the remaining space between the connector body and the floor of the housing, the wedge-like retainer is caught by the hook end, thus filling the remaining space, and making the coaxial cable to be tightly retained in the housing. With this arrangement the connector body can be removed from the housing to be reused.

Abstract: A USB receptacle connector (1) comprises an insulative housing (10), a plurality of terminals (14) received in the insulative housing and a shell (11 ) covering the insulative housing. The frond end of the shell forms a mating port (111 ) for insertion of a mating plug connector (1′). Either of two sidewalls (112) of the mating port defines a contact tab (115) which makes the shell of the USB receptacle connector always contact with a shell (11′) of the mating plug connector. Thus, the two shells are continuously grounded so as to ensure reliable grounding and EMI shielding.

Abstract: A connector housing has an opening for pressure contacting an insulated wire to an insulation displacing terminal in a terminal accommodating chamber. A housing body has an upper wall and a lower wall one of which defines the opening. A cover is for closing the opening and is connected integrally to the housing body through a hinge. An engagement projection is fixed to an outer surface of the cover at a position opposite to the hinge. When a set of insulation-displacement connectors is joined, the engagement projection is fitted in an engagement recessed part formed on an opposing surface of a mating connector, so that the connector housing and the mating connector are joined with each other. Insulation-displacement connectors are stacked in a vertical direction and each has the engagement projection formed to the cover.

Abstract: The object of the present invention to provide a connector, or a male-female engagement type connector set to be more precise, wherein the contact section of the female connector is invisible from the outside through its insertion opening.

Abstract: A connecting tube has a middle portion in the direction of length thereof, which is preliminarily narrowed, and is fixed by being press-fitted into a mounting hole of a shield wall. At a terminal of a shielded cable, an exposed end portion of the shield layer is turned up and put upon a C-ring for underlaying fitted into an end portion of an outer sheath. The shielded cable, on which such terminal processing is performed, is inserted into the connecting tube. A narrowed portion of the connecting tube is caulked so that the shield layer is sandwiched between the narrowed portion of the connecting tube and the C-ring. At that time, at both the front and rear end portions of the caulked portion of the connecting tube, tapering portions, or bellmouths are formed so that their radial dimensions gradually increase in opposite directions, respectively.

Abstract: A connector (1) for receiving a microcircuit card (4), such that the card is held in a seat (3) of the housing (2) of this connector by a release (20) which overhangs the seat on a first edge (19) and on the other side by a tongue (29) situated on a flexible girder on a second opposite edge (24). The tongue is situated on a flexible girder in such a manner as to allow the passage of the card beneath the tongue. Further, the girder (25) has a lever arm formed by a lug (30) preferably diametrically opposite the tongue (29), to assist girder bending.

Abstract: The present invention provides a removable, “snap-in” ground polarization insert for a power connector that accommodates insertion of a corresponding ground polarization pin therein. The insert is molded from the same insulative material as the surrounding housing. The insert remains separate from the connector until assembly of the final product, enabling the user to determine the requisite combination of a proper insert configuration and a corresponding plug or receptacle that is currently available in the inventory. The ability to delay assembly of the connector and insert thereby allows use of the connector with pre-existing plugs and receptacles in view of available inventory and current customer demands.

Abstract: Terminal covers (51, 52) have terminal accommodation spaces, each of which has an opening of a predetermined shape that permits only one of battery terminals (24, 25), which is of predetermined polarity, to be fitted thereto. Each of the battery terminals (24, 25) is formed in such a manner as to have a predetermined shape enabling the battery terminal to be fitted into the corresponding terminal accommodation space. The battery body (27) has cover fitting holes (54a, 54b (55a, 55b)), which permit only fitting projection pieces (51c, 51d (52c, 52d)) of the terminal cover (51 (52)) accommodating and holding the battery terminal (24 (25)) to be fitted thereinto, in the vicinity of the battery electrode (29 (30)) so that only the battery terminal (24 (25)) is placed at a fastening/fixing position on the battery electrode (29(30)).

Abstract: A main body includes a plurality of holes formed therein a main clip and includes an exterior contact portion positioned exterior to the main body, a first carrier strip connected to the exterior contact portion and located within the main body and a plurality of clips extending from this carrier strip, each position within a corresponding hole formed in the main body. A slave clip includes a carrier strip located within the main body and a plurality of clips extending from the carrier strip, each positioned within a corresponding hole of the main body to make the corresponding one of the clips of the main clip. The pair of the clips formed within each hole form a terminal to allow terminal portions of a grounding wire to be connected therein. A cap having a plurality of holes corresponding in position and size to the holes formed in the main body may be frictionally engaged in a hollow portion of the main body to complete the assembly. The same potential block (e.g.

Abstract: A structure for engaging a connector housing (2) and rear holders (3, 4), which are molded and engaged with each other in a same metal mold, includes terminal retaining holes (7) communicating with terminal receiving chambers (5) formed in the connector housing (2), guide rails (8) for temporarily retaining the rear holders (3, 4), and projections (9) for completely retaining the rear holders. The rear holders (3, 4) are provided with terminal retaining projections (16) adapted to retain terminals (17), and a pair of wings (13, 13). There are further formed tapered surfaces (11, 12, 15, 18) respectively on the guide rails (8), at a backward end of the connector housing (2) for positioning the rear holders, at distal ends of the pair of the wings (13, 13), and on the terminal retaining projections (16).

Abstract: A terminal fitting includes: a first portion which is secured to a cable; a second portion which has a substantially U-shape in which a first end thereof is integrally connected to the first portion, and an electrode post is fitted therein; and a third portion which is extended from a second end of the U-shaped second portion so as to across the first end of the second portion. A locking lever is pivotally supported on the third portion of the terminal fitting. The locking lever includes a cam portion having a cam face which is eccentric with respect to a pivotal center of the locking lever so that the cam face deforms the first end of the second portion of the terminal fitting so as to fasten the electrode post, in cooperation with a pivotal movement of the locking lever. A positioning member is provided on a battery body so as to always retain the first portion of the terminal fitting at a predetermined position.

Abstract: A four stroke internal combustion engine includes a cylinder head having a valve train having reduced profile that permits access to a spark plug assembly located therein.