Abstract: An optical sensor includes a light-emitting element and first to third light-receiving elements. The light-emitting element is arranged on a first side of a transfer path along which a recording sheet is moved. The first light-receiving element is arranged on a second side of the transfer path which is opposite to the first side. The second and the third light-receiving elements are arranged on the first side of the transfer path in the vicinity of the light-emitting element.

Abstract: An inspection method for cream solder for determining whether or not the shape of the cream solder is appropriate based on information on the height of the cream solder by irradiating light from substantially besides in two directions opposing each other through a lighting means to the cream solder so as to obtain at least two images and obtaining a difference between the obtained images.

Abstract: A radiation image conversion panel has a stimulable phosphor layer which is parted into a plurality of cells regularly arranged at least in a main scanning direction by a partition wall and has been exposed to a radiation bearing a radiation image of an object. The radiation image conversion panel is scanned by a stimulating light beam in the main scanning direction and a sub-scanning direction and stimulated emission emitted from the radiation image conversion panel upon stimulation by the stimulating light beam is photoelectrically detected to make up an analog image signal and a digital image signal representing a radiation image of the object is obtained by digitizing the analog image signal.

Abstract: A unitary diaphragm assembly for use primarily in conventional flush valves. The diaphragm assembly has a flexible diaphragm which includes a sealing portion and a mounting portion at the outer peripheral edge. A flow ring is positioned adjacent the sealing portion of the diaphragm. An elongated barrel member extends from the diaphragm in a longitudinal direction and includes a plurality of radial guides positioned circumferentially around the outer surface of the barrel member along a portion of the length of the barrel member. The diaphragm defines an orifice having a ring portion that flexes when a pressure difference is applied across the orifice thereby increasing the flow rate across the diaphragm. The orifice has a smaller diameter at a first end relative to a second end of the orifice. A method of compensating for a pressure difference across the diaphragm is also disclosed.

Abstract: The invention refers to a control device for an actuator (1). The device, controlled by a control valve (20; 71; 80, 81), comprises means (30, 31) to obtain different conditions of the control valve, and these means (30, 31) are activated by means of a two-position fluidics solenoid valve (32, 33) to which a set-point instruction is applied (6). The control device comprises furthermore means (10) to be assured of the response of the solenoid valve depending on the set-point instruction (6) over the full range that the actuator (1) can cover.

Abstract: A barstock body fluid control valve comprising a barstock body of preselected material having an inlet end and an outlet end, and a preselected cross section defining the outer walls; a through machined main flow port located eccentrically on the inlet and the outlet ends wherein the main flow port eccentric location increases the available barstock thickness at one outer wall location and decreases barstock thickness in the opposite wall.

Abstract: Disclosed are ester-containing fluid compositions, methods of making such compositions, and methods of using such compositions. The fluid compositions comprise a mix of branched and linear ester compounds, and the fluid compositions are characterized by certain performance limitations. The preferred method of making the fluid compositions enables the ester mix to be made in a one step process with little finishing required to obtain desirable performance characteristics.

Abstract: A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining.

Abstract: The invention relates to chiral compounds of formula I 1

Abstract: The invention aims to provide a phosphor multilayer eliminating a need for filters, having a satisfactory color purity and useful in white monochromatic EL devices, and an EL panel. Such objects are achieved by a phosphor multilayer comprising at least a first thin film and a second thin film wherein the first thin film is formed of a matrix material comprising barium aluminate as a main component, containing sulfur element and further containing Eu as a luminescent center, and the second thin film is formed of a matrix material comprising zinc sulfide as a main component, and an EL panel using the same.

Abstract: A conductive paste which can form a thick film conductor containing no lead, being able to be fired at a middle temperature, superior in conductivity, and having sufficient adhesive strength to a substrate, and a printed wiring board formed using the conductive paste are provided. The conductive paste contains a Cu containing powder; a glass frit; and an organic vehicle, wherein the glass has a composition represented by xBi2O3—yB2O3—zSiO2, where x, y, and z are indicated in mole %, and a composition ratio (x, y, z) within the range surrounded by point A (15, 35, 50), point B (25, 60, 15), point C (45, 40, 15) and point D (45, 20, 35) in a ternary compositional diagram, and a mean particle diameter of about 0.1 to 1.0 &mgr;m.

Abstract: A technique and apparatus are disclosed for injection molding highly filled conductive resin compositions. These compositions include one or more of unsaturated polyester and vinyl ester resin; a copolymer having a terminal ethylene group; and at least about 50 weight percent of an inorganic particulate conductive filler, an initiator, and a rheological modifier to prevent phase separation between said resin and said conductive filler during molding. The method of the present invention allows these compositions to be molded into highly intricate and thin electrically and thermally conductive specimens without significant post process machining. The method involves the use of an injection molding apparatus that has a hopper with an auger having a vertical component in its positioning to feed into the feed throat of an injection molding machine which has a phenolic screw that has been modified to have a constant inner diameter and a constant flight depth.

Abstract: A bandpass filter containing specific red dyes alone or in combination with other dyes selectively transmits predetermined primary color wavelengths as well as selectively absorbs wavelengths other than the predetermined primary color wavelength. The filter is particularly useful for enhancing the contrast of color plasma displays by absorbing visible light emitted at 590 nm from the display.

Abstract: A cable guide is provided for guiding lines or cables in a guide channel, the guide preferably having a continuous, elongated slide strip, which can be disposed in a curved orientation to form opposite upper and lower strands and a deflection zone between them. The cable guide has a plurality of guide links that can pivot relative to one another and are preferably arranged on the side of the slide strip facing away from the opposite strand and mounted on the slide strip in detachable fashion. In order to improve a generic cable guide such that it has a longer service life and less noise emission, elements are provided, in addition to any existing slide strip, that absorb the tensile forces acting in the longitudinal direction of the cable guide when it is in essentially extended position. The tensile force-absorbing elements are preferably designed as positive locking elements, e.g., in the form of projections protruding into the pivoting plane and corresponding recesses arranged on adjacent guide links.

Abstract: A flexible elongated cap for topping a fence panel. The elongated cap comprises a durable casing surrounding a foam core wherein the casing defines a channel for receiving the upper end of the fence panel. The side walls of the channel are angled inward to provide a clamping affect over the upper end of the fence panel. The cap is aesthetically shaped and is flexible to allow for adaptation to a variety of fence panel shapes.

Abstract: A modular, temporary fencing system for sports arenas comprises a plurality of spike-footed poles and a plurality of mesh fencing panels. The poles each have four longitudinal “key-hole” slots, and opposite side ends of the mesh fencing panels are configured to fit in the slots. To delineate a sports playing field or arena, the side ends of the fencing panels are inserted into the key-hole slots, and the poles are partially inserted into the ground, with the fencing panels supported there between, according to the desired dimensions and shape of the playing field or arena. Further, the poles are composed of a polymer chosen so that the poles are rigid enough to support the fencing panels and to delineate the playing area, yet flexible enough so that when a player falls against the fence, the fence can bend substantially to the ground without injuring the player or breaking.

Abstract: An auxiliary handrail apparatus for use along a stairway is disclosed. The apparatus includes a pivot support fixed to an existing handrail or other support structure in the proximity of an existing handrail to allow positioning of the auxiliary handrail in two positions.

Abstract: A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C.

Abstract: A practical operational amplifier circuit is formed using thin film transistors.

Abstract: A thin film transistor has a structure capable of decreasing deterioration in Vgs-Ids characteristics. The thin film transistor has a source region composed of an N-type impurity-diffused region, a drain region, and a gate electrode, and a channel region formed directly below the gate electrode. To the source region and the drain region are connected a source electrode and a drain electrode, respectively, through a plurality of contact holes. In the channel region are formed a plurality of P-type impurity-diffused regions at constant intervals.

Abstract: A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers includes forming a first doped and activated polysilicon area (either n-type and p-type) on a substrate. An isolation material layer is formed abutting the first activated area. A second doped and activated polysilicon area of opposite conductivity type from the first activated area is formed adjacent to the isolation material layer. The second activated opposite area has a height that does not exceed that of the first doped and activated polysilicon layer. Further processing may be effected to complete the MOS device. The method of the present invention eliminates ion implantation and annealing steps used in previously existing methods.

Abstract: Concave and convex are formed on the substrate 1, the amorphous silicon layer 4 is formed on the metallic catalyst 3 dispersed and arranged in a dotted shape in the concave portion of the concave and convex, the crystal phases 5 having respective orientations from the metallic catalyst 3 are grown, further the crystal phases 5 are integrated with each other by continuing heat treatment and the polycrystalline silicon layer 6 is formed. A crystalline silicon semiconductor device and its method for fabrication which are costly advantageous and capable of efficiently forming the polycrystalline silicon layer of a predetermined thickness needed as a semiconductor device are provided.

Abstract: A semiconductor device with which a panel having a large area or a narrowly margined with the circumferential space minimized can be manufactured stably with a high yield. The semiconductor device comprises a TFT substrate having a plurality of pixels of a plurality of TFT (thin film transistors) provided on the substrate in which a peripheral wire is arranged along the outer periphery of the TFT substrate and connected to a constant potential.

Abstract: A first GaN layer (2) is formed on a substrate (1), mask layer (3) having opening parts (3a) are formed thereon, a second GaN layer (4) is selectively grown in the lateral direction from the opening parts on the mask layer, and further a nitride type compound semiconductor layered part (15) is so laminated as to form a light emitting layer. Recessed parts (3b) are formed in the upper face side of the mask layer. In other words, owing to the recessed parts in the upper face side of the mask layer, the second GaN type compound semiconductor layer (4) is grown as to form approximately parallel gap (3c) between the bottom face of the second GaN type compound semiconductor layer and the mask layer. Further, it is preferable for the mask to be formed in a manner that the opening parts for exposing the seeds are not arranged only continuous in one single direction in the entire surface of the wafer type substrate.

Abstract: A semiconductor laser diode module in which a laser diode and an optical fiber are optically coupled with each other efficiently irrespective of an ambient temperature change within the laser diode module. The laser diode module includes a laser diode, an optical system including an optical fiber and a lens portion, a holder configured to receive a portion of the optical system, a base having a holder mounting member and a fastening member, and a bottom plate configured to support the base. The holder is mounted to the fastening member at a first joint position, and the fastening member is mounted to the holder mounting member at a second joint position, where the first and second joint positions are located at substantially a same distance from the bottom plate. Alternatively, the first and second joint positions are coplanar with an active layer of the diode.

Abstract: In semiconductor light emitting sections capable of effectively improving electric cross-talk and effectively avoiding short-circuit between each of light emitting devices, in which a plurality of semiconductor light emitting sections are formed to a semiconductor substrate, and at least one of electrodes for the semiconductor light emitting sections and bonding pads lead out electrically from the electrodes and connected with external leads are formed on one main surface of a semiconductor substrate, a high resistance isolation region is formed, facing the main surface of the semiconductor substrate, below a portion between adjacent conductor layers for electrical leading from the electrode to the bonding pad.

Abstract: The present invention provides a photoreceiving device that is inexpensive and has good properties as a photoreceiving device for selectively receiving long wavelength light. This is a semiconductor photoreceiving device 10 for selectively receiving long wavelength light from multiplexed light including long wavelength light A and short wavelength light B. This photoreceiving device comprises a multilayered film 22 comprising alternately stacked layers of materials having mutually different indexes of refraction and the thicknesses and number of which are designed so as to transmit said long wavelength light and reflect said short wavelength light; and a first light-absorbing layer 14 composed of a material having a band gap wavelength longer than the wavelength of said long wavelength light.

Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.

Abstract: An electrostatic discharge (ESD) protective structure is configured and arranged to protect an integrated semiconductor circuit that is located between a first potential bus with a first supply potential and a second potential bus with a second supply potential. The ESD protective structure includes a laterally shaped ESD diode having a first region with a first conduction type and a second region of a second conduction type spaced apart from the first region. The ESD protective structure is located between the potential busses and is provided with a gate electrode, such that the first region and the second region are adjusted with respect to the gate electrode, and the spacing between the first region and the second region corresponds to the length of the gate electrode.

Abstract: A compound semiconductor device includes a cap layer formed on a channel layer and an insulating film formed on the cap layer, and a &Ggr;-shaped gate electrode is provided in a gate recess opening, wherein an extension part of the &Ggr;-shaped gate electrode extends over the insulating film toward a drain electrode, and the total thickness of the insulating film and the cap layer being is set such that the electric field formed right underneath the extension part of the gate electrode includes a component acting in a direction perpendicular to the substrate.

Abstract: Provided are a semiconductor device that can obtain more output current without increasing the occupied area of a MOS transistor, and a method for manufacturing the same. MOS transistors (M11, M12) are electrically isolated by a trench isolation oxide film (21). The MOS transistor (M11) has a groove portion (GP) in which the width of the top is 20 nm to 80 nm and the depth is 50 nm to 150 nm. The groove portion (GP) is disposed at the boundary part between a trench isolation insulating film (22) and an active region (AR1) so as to surround the active region (AR1). A gate electrode (31A) is not only disposed above the active region (AR1) but also buried in the groove (GP) with a gate oxide film (30) interposed therebetween.

Abstract: A field effect transistor suited for use as a sensor element or in an acceleration sensor is described. For this purpose, the field effect transistor within a planar substrate has a drain area and a source area, which are separated from each other by a channel region. In addition, a gate electrode is provided which is arranged so as to be substantially self-supporting above the substrate over the channel region. The gate electrode is flexibly supported such that an external force acting upon it which has a component acting parallel to the surface of the substrate causes a deflection of the gate electrode parallel to the surface of the substrate. A method is also described in which, in a first method step, an integrated circuit having a drain area, a source area, and a channel region is manufactured or made available in a CMOS process, and thereafter, in a second method step, the substantially self-supporting gate electrode is produced on the integrated circuit using electroplating additive technology.

Abstract: An anti-reflective layer is formed on the sidewalls of metal interconnects in an integrated circuit containing photodetector devices. After fabricating the photodetector devices, the metal interconnects are formed. An anti-reflective layer is formed over the interconnects and is directionally etched so that a portion of the anti-reflective layer remains covering the interconnect sidewalls, thereby reducing optical cross-talk in the photodetector devices due to sidewall reflection.

Abstract: Ferroelectric memory includes a hollow formed in a first insulation film. A lower electrode is formed in this hollow by sol-gel method including an application process due to a spin coat method. In this application process, a precursor solution is dripped on a surface of the first insulation film and splashed away due to centrifugal force. Due to this, a first conductive film to being formed has an increased film thickness at portion of the hollow where the precursor solution is ready to correct, or portion to be formed into a lower electrode, and a decreased film thickness at portion other than the hollow. Accordingly, it is satisfactory to etch only the hollow portion when forming a lower electrode by dry-etching the first conductive film.

Abstract: A DRAM semiconductor device wherein a substrate plate trench (SPT) memory cell is formed in an N−-type substrate, without an epitaxial layer in which the substrate is biased at circuit ground in order to ensure that the substrate surrounding the trench capacitors is biased into accumulation in order to avoid unacceptable loss of storage node capacitance which would be caused by allowing the substrate to go into depletion.

Abstract: According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode 11 of titanium nitride in the active region of a semiconductor substrate or over the gate electrode, reducing the size of the opening for passing the storage electrode 15 of the capacitor of a stacked structure, and decreasing the line width of a wiring electrode 13. By the common use of the above-mentioned plug electrodes in a CMISFET region in the peripheral circuit and in a memory cell of a static RAM, their circuit layouts can be made compact.

Abstract: A memory cell configuration has memory cells, each with a trench capacitor in a trench and a vertical transistor, which is used as a selection transistor. The trench capacitors in adjacent memory cells are arranged next to a bit line and are connected to the bit line via their selection transistor. Adjacent trench capacitors connected to a bit line are arranged alternately on the two sides of the bit line.

Abstract: A method for fabricating a semiconductor component includes the steps of applying an electrode material and a metal-oxide-containing layer on a substrate surface and selectively etching the electrode material and the metal-oxide-containing layer for forming a first electrode from the electrode material and forming a metal oxide layer from the metal-oxide-containing layer, wherein the metal oxide layer is disposed on top of the first electrode. The method further includes conformally applying a conductive material which has a given material thickness, anisotropically etching the conductive material for fabricating a resistance element in the form of a self-aligned lateral edge web on at least one sidewall of the metal oxide layer and of the first electrode, and applying a further electrode material at least on the resistance element for forming a second electrode.

Abstract: A DRAM cell with a vertical transistor and a deep trench capacitor. In the DRAM cell, a deep trench capacitor is desposed in a substrate; a gate is disposed over the deep trench capacitor; an ion doped layer is disposed between the gate and an upper electrode of the capacitor; an insulating layer is disposed between the gate and the ion doped layer; a gate insulating layer is disposed on a sidewall of the gate; a channel region is located beside the gate insulating layer in the substrate; a source is disposed on a sidewall of the ion doped layer and on one side of the vertical channel region; and a common drain is disposed on the other side of the vertical channel region. The DRAM cell can be applied to an open bitline DRAM, a folder bitline DRAM, and a foler bitline DRAM with bordless bitline contact window.

Abstract: The integrated circuit configuration has at least one buried circuit element and an insulating layer. A multiplicity of insulating regions are in contact with one another to forming a locally delimited insulating layer in the substrate. In this way, trench capacitors implemented as buried circuit elements can be manufactured with a structure size of less than 100 nm in a simple and cost-effective manner.

Abstract: A method for spinning a material onto a semiconductor device structure so as to substantially fill recesses formed in a surface of the semiconductor device structure and to impart the material with a substantially planar surface and semiconductor device structures formed thereby. The thickness of the material covering the surface is less than the depth of the recesses. The surface may remain substantially uncovered by the material.

Abstract: A thin film transistor and a fabricating method thereof are adaptive for increasing a capacitance of a storage capacitor. In the method, a gate electrode and a lower electrode of a capacitor are formed at the transistor area and the capacitor area of an insulating substrate, respectively. A gate insulating film, an active layer and an ohmic contact layer on the insulating substrate is sequentially formed to cover the gate electrode and the lower electrode. The ohmic contact layer and the active layer are primarily patterned in such a manner as to be left only at a portion corresponding to the gate electrode of the transistor area and thus expose the gate insulating film. Then, the ohmic contact layer and the active layer are secondarily patterned in such a manner as to reduce the thickness of the gate insulating film at a portion corresponding to the lower electrode.

Abstract: The invention relates to a low inductance multilayer chip and a method for fabricating the same, the multilayer chip including a plurality of internal electrode layers where the internal electrodes of the predetermined layers are electrically connected to reverse the current directions flowing in the internal electrodes of neighboring layers to thereby offset inductance and performing stable operations at high frequency.

Abstract: When a through hole 17 is transferred on a pair of contact holes 10 putting a data line DL therebetween, even if a pair of through holes 17 putting the data line DL therebetween are deviated, the pair of through holes are connected to the contact hole 10b and not connected to the data line DL. By this manner, a mask pattern formed by a photomask is use so as to be deviated and disposed in a direction separately from the data line DL at a design stage. This results in improvement of an alignment tolerance of the pattern.

Abstract: An EEPROM memory cell comprising a transistor on a first conductivity type semiconductor substrate and a capacitor formed on a second conductivity type semiconductor substrate. The capacitor comprises first and second injector regions of third conductivity type, a channel region of second conductivity type separating the first and second injector regions and a first electrically floating structure disposed above the channel region, wherein a first edge portion of the floating structure overlaps a portion of the first injector region and a second edge portion of the first floating structure overlaps a portion of the second injector region, and a control gate region of fourth conductivity type located within the second conductivity type semiconductor substrate region. The gate structure and first floating structure are electrically connected together. In different aspects of the present invention, the EEPROM memory cell may also include a second capacitor.

Abstract: A semiconductor memory capable of attaining a low voltage, a high-speed operation, low power consumption and a high degree of integration is obtained. This semiconductor memory comprises a floating gate electrode, a first source/drain region having a diode structure employed for controlling the potential of the floating gate electrode and a second source/drain region formed to hold a channel region between the same and the first source/drain region. Thus, when a channel of a transistor is turned on in reading, a large amount of current flows from the first source/drain region having a diode structure to a substrate, whereby high-speed reading can be implemented. Further, a negative voltage is readily applied to the first source/drain region having a diode structure, whereby a low voltage and low power consumption are attained and the scale of a step-up circuit is reduced, and hence a high degree of integration can be attained.

Abstract: A semiconductor device comprising a non-volatile memory cell, for storing at least one bit, in a semiconductor substrate (1) having, in the substrate, a source region (6), a drain region (7) and a channel region (10) between the source (6) and drain (7) regions, and having, on top of the substrate, a floating gate (9) separated from the channel region (10) by a floating gate insulating layer, a select gate (11) adjacent to the floating gate and separated from the channel region by a select gate insulating layer (8), and a control gate (5) separated from the floating gate (9) by a control gate insulating layer, the floating gate being a non-conducting charge trapping dielectric layer (9).

Abstract: A non-volatile semiconductor memory manufacturing method, according to the present invention, is comprised of the process steps that follow. Device isolating layers are formed on predetermined places in a cell region. A layer of floating gate material is deposited next, all over the substrate. Either all the layer of floating electrode material, deposited on the device isolating layers or a part of it, is removed next, by etching, in order to form ditches. To fill the ditches, a first insulation layer is formed next, all over the cell region. A predetermined part of the first insulation layer is removed next, by etching, so the layer of floating electrode material is exposed. Thereafter, the ditches are filled in, on top of the device isolating oxide layers, with insulation layers. A second insulation layer is formed next, all over the cell region. Thereafter, electrode material layers and are deposited on the surface.

Abstract: A semiconductor memory device (100) having an array of ROM cells (101) based on a flat cell architecture has been disclosed. Semiconductor memory device (100) can include a y-selector (103) coupled between a sense amplifier (102) and array (101). During a read operation, the y-selector can electrically connect a selected digit line (D2) and an adjacent digit line (D3) to the sense amplifier. Y-selector (103) can couple a next digit line (D4) to a precharge voltage that may be supplied by a precharge circuit (104). A virtual ground selector (105) can apply a ground voltage level from a main virtual ground line (VG1) to sources of a column of memory cells including a selected memory cell (310). Virtual ground selector (105) can apply a precharge voltage to an adjacent main virtual ground line (VG2). In this manner, a minimum sensing current, when a series of memory cells along a selected word line (WO1) are on-bit cells, can be improved.

Abstract: A trench-gate power semiconductor device and a method for fabricating the same are provided.