Abstract: A power semiconductor device includes a substrate of first conductivity having a dopant concentration of a first level. The substrate is a group III-V compound material. A transitional layer of first conductivity is epitaxially grown over the substrate. The transitional layer has a dopant concentration of a second level and is a group III-V compound material. An epitaxial layer of first conductivity is grown over the transitional layer and has a dopant concentration of a third level. Electrical currents flow through the transitional and epitaxial layers when the device is operating.

Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Abstract: A MIS type semiconductor device comprises a semiconductor layer provided with a recess portion having a side wall with an obtuse angle at least at a portion of the recess portion, a gate electrode formed over a bottom surface of the recess portion, with a gate insulating film interposed, a source region and a drain region formed on sides of the gate electrode with an insulating film interposed, such that boundary planes between the source region and the drain region, on one hand, and the insulating film, on the other hand, are formed in the semiconductor layer at an angle to a surface of the semiconductor layer, and wiring portions for contact with the surface of the semiconductor layer.

Abstract: A DMOS transistor in which a main current flows between first and second main surfaces of a silicon substrate is formed. DMOS transistor has a p-type diffusion region formed in the first main surface, an n+ diffusion region formed in the first main surface in p-type diffusion region, and a gate electrode facing p-type diffusion region sandwiched between n+ diffusion region and n− layer via a gate insulating layer. A dielectric layer is formed in the silicon substrate so as to be adjacent to n− layer, and made of a material having a dielectric constant higher than that of silicon. Therefore, the semiconductor device which can be easily formed while suppressing increase in process cost and has an improved trade-off (effective on-state resistance) between a withstand voltage and on-state resistance by generating an electric field almost uniform in the direction of the thickness of a semiconductor substrate can be attained.

Abstract: High performance asymmetric transistors including controllable diode characteristics at the source and/or drain are developed by supplying impurities with high accuracy of location by angled implants in a trench or diffusion from a solid body formed as a sidewall of doped material. High concentration gradient of impurities to support high performance is achieved by providing for reduced heat treatment after the impurity is supplied in order to limit diffusion previously necessary to achieve the desired location of impurity structures. Damascene or quasi-Damascene gate structures are also provided for high dimensional uniformity, increased manufacturing yield and structural integrity of the transistor.

Abstract: A semiconductor device has a first semiconductor element and a second semiconductor element formed on a semiconductor substrate. The second semiconductor element is operated with a first voltage. The first semiconductor element is operated with a second voltage that is higher than the first voltage. The pairs of impurity regions of the first and second semiconductor elements respectively have first impurity areas and second impurity areas. Each of the first impurity areas indicative of a predetermined impurity concentration by an impurity indicative of a conductivity type opposite to a conductivity type of the semiconductor substrate. The second impurity areas extend toward their corresponding gates from the first impurity areas. The second impurity areas indicate the same conductivity type as the first impurity areas and are indicative of an impurity concentration lower than the concentration of the first impurity area.

Abstract: An integrated circuit device comprises an insulation layer formed on a substrate, a plurality of lattice relaxed SiGe layers each formed in an island form on the insulation layer, wherein a maximum size of the island form thereof is 10 &mgr;m or less, one of a strained Si layer, a strained SiGe layer and a strained Ge layer formed on at least one of the plurality of lattice relaxed SiGe layers, and a field effect transistor having a gate electrode and source and drain regions, wherein the gate electrode is formed on one of the strained Si layer, the strained SiGe layer and the strained Ge layer with a gate insulation film is disposed therebetween, and the source and drain regions is formed to sandwich a channel region formed below the gate electrode with the gate insulation film disposed therebetween.

Abstract: A semiconductor device is provided having angled dopant implantation and vertical trenches in the silicon on insulator substrate adjacent to the sides of a semiconductor gate. A second dopant implantation is in the exposed the source/drain junctions. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

Abstract: A metal-oxide-semiconductor protection transistor is formed in an active region of a semiconductor layer. The active region includes source and drain diffusion layers, which may be partly silicided, and a body region. A gate electrode extends across the active region above the body region. The breakdown voltage in the edge areas of the active regions is increased by increasing the gate length in the edge areas, by increasing the width of the active region below the gate electrode, or by increasing the non-silicided length of the source and drain diffusion layers in the edge areas. The edge areas of the active region are thereby protected from thermal damage during electrostatic discharges.

Abstract: Electrostatic discharge protection device comprising a first highly p-doped region with a base contact, a first highly n-doped region with a collector contact, a second highly n-doped region with an emitter contact and located between the first highly p-doped region and the second highly n-doped region, the first highly p-doped region and the second highly n-doped region being applied in a weakly p-doped region which a has a lateral overlap extending towards the first highly n-doped region, the lateral overlap having a width, the first highly n-doped region being applied in a weakly n-doped region, the weakly p-doped region and the weakly n-doped region being applied in a more weakly n-doped region, and a highly n-doped buried layer located underneath the more weakly n-doped region and extending below at least a portion of the weakly n-doped region and at least a portion of the weakly p-doped region.

Abstract: A semiconductor device comprises a semiconductor substrate, a p-type well formed in the semiconductor substrate, an n-type well formed in the semiconductor substrate and positioned contiguous to the p-type well, an n-type diffused region formed in the p-type well, and a p-type diffused region formed in the n-type well, wherein a corner C1 having the p-type well on the inside is present in a part of the boundary pattern between the p-type well and the n-type well. At least one of the two sides defining the corner C1 extends from a top of the corner to the n-well by a predetermined width d over a predetermined length. The particular structure permits suppressing generation of a difference in a well isolation punch-through voltage between the corner and the straight portion of the well boundary of the semiconductor device, making it possible to provide a fine device structure while ensuring a desired well isolation punch-through voltage without relaxing a design rule.

Abstract: A discriminating method for a trimming error is provided. A fuse is connected between an output terminal and a terminal having a potential at a VDD or VSS level, and an output voltage at the time of the trimming error is fixed. Alternatively, when the trimming error occurs, short circuit is established between VDD and VSS, and a large current is made to flow, thereby making error detection easy.

Abstract: A MOS power transistor formed in an epitaxial layer of a first conductivity type, the MOS power transistor being formed on the front surface of a heavily-doped substrate of the first conductivity type, including a plurality of alternate drain and source fingers of the second conductivity type separated by a channel, conductive fingers covering each of the source fingers and of the drain fingers, a second metal level connecting all the drain metal fingers and substantially covering the entire source-drain structure. Each source finger includes a heavily-doped area of the first conductivity type in contact with the epitaxial layer and with the corresponding source finger, and the rear surface of the substrate is coated with a source metallization.

Abstract: A method comprising over an area of a substrate, forming a plurality of three dimensional first structures; following forming the first structures, conformally introducing a sacrificial material over the area of the substrate; introducing a second structural material over the sacrificial material; and removing the sacrificial material. An apparatus comprising a first structure on a substrate; and a second structure on the substrate and separated from the first structure by an unfilled gap defined by the thickness of a removed film.

Abstract: A white-emitting luminescence conversion LED uses a chlorosilicate phosphor which, in addition to Ca and Mg, contains a europium doping, and also a garnet phosphor of the rare earths, in particular Y and/or Tb. In this way, it is possible to achieve a high color rendering and a high constancy of the lighting properties under differing temperature conditions.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. A thermo-electric device is integrated into the semiconductor structure.

Abstract: On a first region (R1) of a surface (101S1) of an n-type silicon carbide layer (101), a Schottky drain electrode (102) is formed. Further, on a second region (R2), an ohmic source electrode (103) is formed. Furthermore, on a third region (R3), a Schottky gate electrode (104) is formed. Such a structure achieves a state where a Schottky barrier diode is formed between these electrodes (102 and 103). That can achieve a switching element using the silicon carbide layer with high breakdown voltage and low loss, which has both a switching function and a diode function (voltage blocking capability of reverse direction), with no pn junction formed in the silicon carbide layer, and thereby ensures reduction in size an weight of modules.

Abstract: An improved Schottky device, having a low resistivity layer of semiconductor material, a high resistivity layer of semiconductor material and a buried dopant region positioned in the high resistivity layer utilized to reduce reverse leakage current. The low resistivity layer can be an N+ material while the high resistivity layer can be an N− layer. The buried dopant region can be of P+ material, thus forming a PN junction with an associated charge depletion zone in the N− layer and an associated low reverse leakage current. The location of the P+ material allows for a full Schottky barrier between the N− material and a barrier metal to be maintained, thus the device experiences a low forward voltage drop.

Abstract: A two-terminal power diode has improved reverse bias breakdown voltage and on resistance includes a semiconductor body having two opposing surfaces and a superjunction structure therebetween, the superjunction structure including a plurality of alternating P and N doped regions aligned generally perpendicular to the two surfaces. The P and N doped regions can be parallel stripes or a mesh with each region being surrounded by doped material of opposite conductivity type. A diode junction associated with one surface can be an anode region with a gate controlled channel region connecting the anode region to the superjunction structure. Alternatively, the diode junction can comprise a metal forming a Schottky junction with the one surface. The superjunction structure is within the cathode and spaced from the anode. The spacing can be varied during device fabrication.

Abstract: An inductor for an integrated circuit or integrated circuit package comprises a three-dimensional structure. In one embodiment the inductor is arranged on an integrated circuit substrate in at least two rows, each row comprising upper segments and lower segments, with the upper segments being longer than the lower segments. The upper segments in a first row are offset 180 degrees from those in an adjoining row to provide greater coupling of magnetic flux. The materials and geometry are optimized to provide a low resistance inductor for use in high performance integrated circuits. In another embodiment the inductor is arranged on an integrated circuit package substrate. Also described are methods of fabricating the inductor on an integrated circuit or as part of an integrated circuit package.

Abstract: A nonvolatile memory device with a reduced size floating gate and an increased coupling ratio is disclosed.

Abstract: A method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer outwardly from the first oxide layer, removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region, forming a second oxide layer in the trench isolation region, forming a spin-on-glass region in the trench isolation region, annealing the spin-on-glass region, removing a portion of the spin-on-glass region to expose a shallow trench isolation region, and forming a third oxide layer in the shallow trench isolation region.

Abstract: Porous dielectric materials having low dielectric constants, ≧30% porosity and a closed cell pore structure are disclosed along with methods of preparing the materials. Such materials are particularly suitable for use in the manufacture of electronic devices.

Abstract: A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.

Abstract: The invention relates to the laser adjustment or laser programming of laser fuses of an integrated circuit (2) on a chip (1), with laser light (7), the integrated circuit (2) having a plurality of laser fuses (3) and being connected to a plurality of contact pads (4) on the chip (1), and the chip (1) being covered with a polymer layer (5) which has at least windows (16) on the plurality of contact pads, and comprising at least one wiring interconnect (9) on the polymer layer (5) which is electrically connected to at least one of the plurality of contact pads (4) and ends at a predetermined location on a surface of the chip (1).

Abstract: A method of forming a metal-insulator-metal capacitor (see e.g., FIG. 1) in a back end of line structure comprises forming a metal bottom plate 16 in a first metalization layer 14, sputter depositing a high dielectric constant material 18 over the bottom plate 16, and forming a metal top plate 20 in a second metalization layer 22. The metal bottom plate 16 and metal top plate 22 are formed in consecutive metalization layers 14 and 22 in which interconnect structures 12 and 24 are also formed.

Abstract: A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

Abstract: An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island formed in a substrate, a source, a gate and a first and second drain extension. The island is doped with a low density first conductivity type. The source and drain contact are both doped with a high density second conductivity type. The first drain extension is of the second conductivity type and extends laterally from under the gate past the drain contact. The second drain extension is of the second conductivity type and extends laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.

Abstract: A MOSFET that includes short channel regions for a reduced RDSON, and narrowly spaced, relatively deep base regions for an improved breakdown voltage.

Abstract: A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

Abstract: A bipolar transistor using a B-doped Si and Ge alloy for a base in which a Ge content in an emitter-base depletion region and in a base-collector depletion region is greater than a Ge content in a base layer. Diffusion of B from the base layer can be suppressed by making the Ge content in the emitter-base depletion region and in a base-collector depletion region on both sides of the base layer greater than the Ge content in the base layer since the diffusion coefficient of B in the SiGe layer is lowered as the Ge contents increases.

Abstract: A silicon-germanium bipolar transistor includes a silicon substrate in which a first n-doped emitter region, a second p-doped base region adjoining the latter and a third n-doped collector region adjoining the latter, are formed. A first space charge zone is formed between the emitter region and the base region and a second space charge zone is formed between the base region and the collector region. The base region and an edge zone of the adjoining emitter region are alloyed with germanium. The germanium concentration in the emitter region rises toward the base region. The germanium concentration in a junction region containing the first space charge zone rises less sharply than in the emitter region or decreases and, in the base region, it initially again rises more sharply than in the junction region.

Abstract: An element isolation structure of a semiconductor device that prevents travel of ions through an isolation film at the time of ion implantation during an element formation step, and also prevents break of the isolation film in the event of misalignment of a contact hole during an interconnection formation step are provided. The semiconductor device includes an isolation film formed on a main surface of a silicon substrate, and a protective nitride film formed on the isolation film. An upper surface of the isolation film is higher in level than the main surface of the silicon substrate. The protective nitride film is positioned, as seen from above, inner than a portion of the isolation film exposed on the main surface of the silicon substrate.

Abstract: Disclosed is a lead frame, including an inner lead, an outer lead connected to the inner lead, and an insulating film covered on the inner lead, the insulating film having an opening formed on a predetermined area of the inner lead electrically connected to a semiconductor chip.

Abstract: A flexible wiring substrate for coupling between a semiconductor element and a circuit substrate. The flexible wiring substrate comprises a base material layer made of insulating and flexible material, and wiring conductors formed on the base material layer. The wiring conductors are formed of at least one electroless plated layer and at least one electroplated layer formed on the at least one electroless plated layer. The wiring conductors are formed apart from a peripheral edge portion of the base material layer. A power supply line for electroplating used for forming the electroplated layer does not remain on the base material layer. The wiring conductors have, for example, a multi-layer structure comprising an electroless plated copper layer formed on the base material layer, an electroplated copper layer formed on the electroless plated copper layer, an electroplated nickel layer formed on the electroplated copper layer, and an electroplated gold layer formed on the electroplated nickel layer.

Abstract: In a semiconductor IC device, a first IC chip having a plurality of first electrodes and a second IC chip having a plurality of second electrodes are stacked. A plurality of relay electrodes are provided on the first IC chip. The first electrodes are electrically connected to a lead frame via respective first conductive wires. One end of each of the relay electrodes is electrically connected to the respective second electrodes via respective second conductive wires and the other end of each of the relay electrodes is connected the lead frame via third conductive wires. No one of the second conductive wires crosses another one of the other second conductive wires and no one of the third conductive wires crosses another one of the third second conductive wires.

Abstract: The present invention allows multiple IC devices to be placed on the same substrate within a single BGA package. The invention requires minimum distances to be kept between electrical connections of the IC devices to maintain the electrical isolation, so that the devices can be operated at different voltage differentials. Signals between the devices can be connected externally from the package to each other utilizing galvanic isolation techniques. The invention provides the flexibility of choice for the customers to use isolation or not between the devices and takes up less PC board space because only a single package is used on the board.

Abstract: A semiconductor device includes a resin sealing portion which has a plurality of side surfaces and a back surface which is formed between the side surfaces, a semiconductor chip which has a plurality of pads on a main surface thereof, a plurality of leads which are formed of conductor and each of which has a bonding portion, an external connection terminal portion and a cut portion, a plurality of wires which connect a plurality of leads and a plurality of pads of the semiconductor chip to each other, and a tab on which the semiconductor chip is mounted. By making the thickness of the cut portion of the lead smaller than the thickness of the external connection terminal portion, a lead sagging which is generated on the side surfaces of the resin sealing portion when the lead is cut by dicing after molding can be reduced.

Abstract: The semiconductor device includes a first semiconductor chip having first electrodes on a fringe region of a main surface thereof, and a second semiconductor chip smaller in area than the first semiconductor chip and having second electrodes on a main surface thereof. The first semiconductor chip and the second semiconductor chip are connected together by bonding a surface of the second semiconductor chip that is opposite to the main surface thereof to a region of the main surface of the first semiconductor chip other than the fringe region. The first electrodes are connected to the second electrodes by wirings formed over the main surface of the first semiconductor chip, a side surface of the second semiconductor chip and the main surface of the second semiconductor chip.

Abstract: A semiconductor package has a substrate of an approximate planar plate comprising of an insulative layer having a plurality of land holes formed in the vicinity of an inner circumference thereof and a plurality of electrically conductive patterns formed at a surface of the insulative layer, the electrically conductive patterns comprising a plurality of bond fingers formed in the vicinity of a central portion of the insulative layer and a plurality of lands for covering the land holes connected to the bond fingers. A semiconductor die is located at a central portion of the substrate. The semiconductor die has a plurality of bond pads formed at one surface thereof. A plurality of conductive bumps is used for coupling the bond pads of the semiconductor die to the bond fingers among the electrically conductive patterns of the substrate.

Abstract: An improved die stacking scheme is provided. In accordance with one embodiment of the present invention, a multiple die semiconductor assembly is provided comprising a substrate, first and second semiconductor dies, and at least one decoupling capacitor. The first semiconductor die defines a first active surface. The first active surface includes at least one conductive bond pad. The second semiconductor die defines a second active surface, the second active surface includes at least one conductive bond pad. The first semiconductor die is interposed between the substrate and the second semiconductor die such that a surface of the second semiconductor die defines an uppermost die surface of the multiple die semiconductor assembly and such that a surface of the first semiconductor die defines a lowermost die surface of the multiple die semiconductor assembly. The decoupling capacitor is secured to the uppermost die surface and is conductively coupled to at least one of the first and second semiconductor dies.

Abstract: A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The second surface of the intermediate substrate includes a cavity defined therein. The intermediate substrate defines a passage there through. The second semiconductor die is secured to the second surface of the intermediate substrate within the cavity such that the conductive bond pad of the second semiconductor die is aligned with the passage.

Abstract: A semiconductor device includes an active region with a main semiconductor device section, and a junction-termination region therearound. A first diffusion layer of a second conductivity type is formed in a surface of a first semiconductor layer of a first conductivity type, and extends from the active region into the junction-termination region. A second diffusion layer of the second conductivity type is formed in contact with the first diffusion layer, and extends in the junction-termination region. A first contact electrode is disposed in the active region and in contact with the first diffusion layer, and electrically connected to a first main electrode of the main semiconductor device section. A second contact electrode is disposed in the junction-termination region and in contact with the first diffusion layer, and surrounds the active region. A connection electrode electrically connects the first and second contact electrodes to each other.

Abstract: A semiconductor integrated circuit device according to the present invention comprises, a semiconductor chip formed with a semiconductor integrated circuit, at least one pair of previous-stage power supply terminals provided on the semiconductor chip and connected to a power supply line, a plurality of pairs of subsequent-stage power supply terminals provided on the semiconductor chip and connected to the power supply line connected commonly to the at least one pair of previous-stage power supply terminals, at least one previous-stage line providing a connection between the at least one pair of previous-stage power supply terminals, and subsequent-stage lines equal in number to the plurality of pairs of subsequent-stage power supply terminals and each providing a connection between the corresponding one of the plurality of pairs of subsequent-stage power supply terminals, wherein the at least one pair of previous-stage power supply terminals and the plurality of pairs of subsequent-stage power supply terminal

Abstract: A semiconductor chip package and a method of fabricating a semiconductor chip package provide a reduced chip size package. The semiconductor chip package includes a semiconductor chip; a plurality of pads disposed on an upper surface of the semiconductor chip; a thermosetting resin formed on the upper surface of the semiconductor chip such that through-holes in the thermosetting resin expose the pads; a multi-layer wiring pattern formed on the thermosetting resin; a connecting unit electrically connecting the multi-layer wiring pattern with the pads; a solder resist on the thermosetting resin, the multi-layer wiring pattern and the connecting unit, such that at least one through-hole in the solder resist exposes a portion of the multi-layer wiring pattern; and a solder ball mounted on the through-hole of the solder resist in contact with the exposed portion of the metal pattern.

Abstract: A circuit board comprising a first metal layer 14 formed in patterns on a ceramic substrate 11, and a second metal layer 16 formed in patterns at least 0.5 ∥m thick on the first metal layer, wherein the first metal layer is reduced in width by etching. Also, a third metal layer 13 may be formed in patterns on the same plane as the first metal layer. The outermost surface of the second metal layer 16 is a metal such as gold that will not be etched. The circuit board has a fine and high-resolution wiring pattern and makes it possible to realize a miniature high-performance high-output module by mounting at least one high-output semiconductor element thereon.

Abstract: The present invention relates to a leadless surface-mount resin-sealing semiconductor device and a manufacturing method thereof; in a semiconductor device comprising a semiconductor element, a resin package sealing this semiconductor element, a terminal formed on a mount side of this resin package so as to protrude thereon, and a wire electrically connecting this terminal and an electrode pad on the semiconductor element to each other, a heat sink dissipating heat generated in the semiconductor element is provided on an undersurface of the semiconductor element so as to improve a heat-dissipation property.

Abstract: A hermetically sealed wafer scale package for micro-electrical-mechanical systems devices. The package consists of a substrate wafer which contains a microstructure and a cap wafer which contains other circuitry and electrical connectors to connect to external applications. The wafers are bonded together, and the microstructure sealed, with a sealant, which in the preferred embodiment is frit glass. The wafers are electrically connected by a wire bond, which is protected by an overmold. Electrical connectors are applied to the cap wafer, which are electrically linked to the outputs and inputs of the microstructure. The final package is small, easy to manufacture and test, and more cost efficient than current hermetically sealed microstructure packages.

Abstract: A device includes a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic films.

Abstract: A ternary metal silicide layer is formed between a silicon substrate and a barrier layer, in a contact structure including: a substrate having a silicon part; an insulating layer formed on the substrate, and having a connection hole that reaches the silicon part, a barrier layer formed at least on an inner surface of the connection hole; and a conductive member buried inside the barrier layer.