Abstract: An object is to provide a method for manufacturing a semiconductor device in which the value of dielectric loss tangent of the dielectric film forming a storage capacitor is reduced to prevent dielectric loss of stored charge in the storage capacitor. After formation of a stacked capacitor (SC), a silicon substrate (1) is rapidly heated in a nitrogen atmosphere to 500 to 800° C. with, for example, lamp heating, to apply an RTA (Rapid Thermal Annealing) for about 3 to 60 seconds. Subsequently, in order to recover the breakdown voltage reduced in the RTA, the silicon substrate (1) is heated to 300 to 550° C. in an oxidative gas to apply an annealing for 30 minutes to 6 hours.

Abstract: A pick and place machine having both a pick preview look down vision system and a horizontal vision system is employed to sense the top surface of the component before picking it up with the pick preview vision system. After pick up the horizontal vision system is employed while transporting the component to a placement position on a substrate to determine the centroid and zero rotational axis of the component and an offset correction to a desired active feature on the component. The centroid of the desired active feature on the component may then be placed on an exact predetermined point on the substrate in a minimum of time and error.

Abstract: The present invention is directed to an effective and relatively inexpensive way to measuring the depth of a well in a semiconductor device. In accordance with an aspect of the present invention, a method for measuring the depth of a well of a substrate comprises providing a substrate having a well therein and a cut through a depth of the well. The substrate is exposed to an etchant to reveal a discontinuity in a boundary at the depth of the well. The depth of the well is measured at the boundary by scanning electron microscopy (SEM) or other suitable techniques.

Abstract: A method of photolithographically patterning an organic semiconductor device, comprising the steps of protecting the organic layer of the device by depositing a metal layer thereon, depositing and patterning a photoresist layer on said metal layer, and selectively etching the exposed areas to pattern said metal layer and said organic layer. Specifically, the disclosed method provides the photolithographic fabrication of organic light emitting diodes (OLEDs) and organic lasers diodes (OLDs).

Abstract: A TFT array substrate and a process for manufacturing the same are provided. A plurality of TFTs in array are formed on a substrate. A gate insulating layer and a protection layer are sequentially formed to cover a pixel region of the substrate. A plurality of openings each of which has an undercut profile are formed in the gate insulating layer and the protection layer. Then, a transparent conductive layer is formed over the substrate. One of the two parts separated is located in a bottom of the opening and the other is on the protection layer, such that two parts of the transparent conductive layer disconnect and no junction there between occurs. The part of the transparent conductive layer in the bottom of the opening is referred to as a transparent pixel electrode. The part of the transparent conductive layer on the protection layer is connected to a common metal line to form a transparent common electrode. The transparent pixel electrode disconnects to but overlaps the protection layer.

Abstract: An undoped GaAs layer is formed on a GaAs substrate. Thallium is adhered to the undoped GaAs layer to a thickness of at least one atomic layer. After adhesion of thallium, GaInNAs is epitaxially grown on the undoped GaAs layer by chemical vapor deposition.

Abstract: A method of fabricating CMOS image sensor. On a substrate, an isolation layer is formed to partition the substrate into a photodiode sensing region and a transistor element region. Next, on the transistor element region, a gate electrode structure is formed and then, a source/drain region is formed at the transistor element region of the two lateral sides of the gate electrode structure. At the same time, a doping region is formed on the photodiode sensing region. After that, a self-aligned barrier layer is formed on the photodiode sensing region and a protective layer is formed on the substrate. Then, a dielectric layer and a metallic conductive wire are successively formed on the protective layer. Again, a protective layer is formed on the dielectric layer and the metallic conductive wire, wherein the numbers of the dielectric layers and the metallic conductive wire depend on the fabrication process. A protective layer is formed between every dielectric layer.

Abstract: The present invention provides a micromechanical or microoptomechanical structure produced by a process comprising defining the structure in a single-crystal silicon layer separated by an insulator layer from a substrate layer; selectively etching the single crystal silicon layer; depositing and etching a polysilicon layer on the insulator layer, with remaining polysilicon forming mechanical elements of the structure; metalizing a backside of the structure; and releasing the formed structure.

Abstract: In a method for producing a diaphragm sensor array having a semiconductor material substrate on which a plurality of planar diaphragm regions is arranged as a carrier layer for sensor elements, the planar diaphragm regions are thermally decoupled from one another by crosspieces made of a material having clearly better heat conductive properties compared to the diaphragm regions and the lateral surroundings of the crosspieces. Masking for a subsequent step for producing porous semiconductor material is applied at the locations of the semiconductor material substrate at which the crosspieces for the thermal decoupling are formed, and the semiconductor regions not protected by the masking are rendered porous and the diaphragm regions are produced thereupon. Instead of using porous silicon, a plasma etching process may be performed from the backside of a semiconductor material substrate. In particular, high integration densities of diaphragm sensors may be achieved with both methods.

Abstract: The present invention provides a photovoltaic device being capable of generating a large amount of current even with thin joined semiconductor layers, has a high photoelectric conversion efficiency and can be manufactured inexpensively at a low temperature together with a manufacturing method of the same, a photovoltaic device integrated with a building material and a power-generating apparatus. The photovoltaic device is formed by depositing joined semiconductor layers on a substrate, wherein a ratio of projected areas of regions on a surface of the joined semiconductor layers that have heights not smaller than a center value of concavities and convexities to a projected area of the entire surface of the joined semiconductor layers is higher than a ratio of projected areas of regions on the surface of the substrate that have heights not smaller than a center value of concavities and convexities on a surface of the substrate to a projected area of the entire surface of the substrate.

Abstract: In a fabrication method of a microstructure array, such as a mold for forming a microlens array, a first insulating mask layer is formed on a conductive portion of s substrate, an array of openings for the microstructure array and at least an opening for an alignment marker are formed in the first insulating mask layer during a common process to expose the conductive portion of the substrate at the openings, and first plated or electrodeposited layers are grown in the openings and on the first insulating mask layer using the conductive portion of the substrate as a cathode. The opening for the alignment marker is surrounded by the array of openings for the microstructure array, and a pattern of the opening for the alignment marker is determined such that a current density distribution at the time of electroplating or electrodeposition can be oppressed.

Abstract: A method of manufacturing an optical semiconductor module, comprising joining an electronic cooling element to a bottom plate of an optical semiconductor package and mounting an optical semiconductor element on the electronic cooling element, wherein the electronic cooling element is soldered to the bottom plate of the optical semiconductor package in a hydrogen atmosphere. The soldering in a hydrogen atmosphere prevents oxidation of a low temperature solder provided on the uppermost surfaces of the electronic cooling element and conduction of the heat at the soldered joint portion between the electronic cooling element and the optical semiconductor element is improved.

Abstract: A semiconductor package, and a method for fabricating the package are provided. The package includes a plastic body, and a pair of stacked semiconductor dice encapsulated in the plastic body, and wire bonded to separate leadframe segments. A first leadframe segment includes lead fingers configured to support a first semiconductor die of the stacked pair, and to form terminal leads of the package. A second leadframe segment is attached to the first leadframe segment, and includes lead fingers that support a second semiconductor die of the stacked pair. The lead fingers of the second leadframe are in physical and electrical contact with the leadfingers of the first leadframe. In addition, tip portions of the lead fingers of the first leadframe segment are staggered relative to tip portions of the lead fingers of the second leadframe segment to provide space for bond wires.

Abstract: A semiconductor package structure with a heat-dissipation stiffener and a method of fabricating the same are proposed. The proposed packaging technology includes a substrate; a thermally-conductive stiffener mounted over the front surface of the substrate, the stiffener being formed with a centrally-hollowed portion and an outward-extending passage a semiconductor chip mounted on the front surface of the substrate and within the centrally-hollowed portion of the stiffener; an underfill layer filled and cured in a gap between the semiconductor chip and the substrate; and a plurality of solder balls mounted on the back surface of the substrate. Alternatively, the passage can be formed in the front surface of the substrate. During fabrication process, the passage is used for the injection of a cleaning solvent into the gap between the semiconductor chip and the substrate so as to clean away remnant solder flux.

Abstract: A structure of a semiconductor device of a chip scale package structure is provided. In the semiconductor device, the limitation to size reduction due to the bonding tool is small and the bonding pitch of the semiconductor chip can be reduced to 100 &mgr;m or less, and the chip shrink technique of a technique for lowering the cost can be employed and in connection with this compatibility among packages can be kept.

Abstract: The present invention is directed to a method of attaching a leadframe to a singulated good die using a wet film adhesive applied in a predetermined pattern on the active surface of the good die, the lead finger of a leadframe, or both. By applying the adhesive only to identified good dice, time and material are saved over a process that applies adhesive to the entire wafer. By attaching the leadframe to the good die with a wet film, it is possible to remove the leadframe from the good die for rework if the good die subsequently tests unacceptable.

Abstract: An integrated circuit (IC) package includes a package body, such as a transfer molded plastic or preformed ceramic package body, having an IC die positioned therein. A lead frame, such as a peripheral lead, Leads-Over-Chip (LOC), or Leads-Under-Chip (LUC) lead frame, includes a plurality of leads with portions enclosed within the package body that electrically connect to the IC die. A heat sink is positioned at least partially within the package body so a surface of a first portion of the heat sink faces the lead frame in close proximity to a substantial part, such as at least eighty percent, of the area of the enclosed portion of the lead frame to thereby substantially reduce an inductance associated with each of the leads.

Abstract: A method of manufacturing a semiconductor device in which a semiconductor element, such as a diode, is attached to a support plate and provided with a plastic encapsulation. The plate is provided with a flange which is provided with an undercut region in order to improve the connection between the plate and the encapsulation. The plate is made from a ductile material. A step is formed in the surface of the plate by pressing using a first die, and by pressing using a second die, the flange provided with the undercut region is formed at, or near, the wall of the step. The flange should be formed at, or very close to, the wall of the step in the plate.

Abstract: A method for manufacturing integrated circuits is described. A semiconductor wafer having an active side with circuit structures is provided. An electrically insulating intermediate layer and an electrically conductive conductor foil are applied to the active side. Conductor tracks with terminal balls are formed with a relatively large spacing pattern in the conductor foil. The semiconductor wafer is subsequently divided up into integrated circuits.

Abstract: A method of forming an integrated circuit package with a downward-facing chip cavity. A substrate comprising an insulating core layer and a conductive layer is provided. A through-hole is formed in the substrate and an adhesive tape is attached to the surface of the conductive layer. A silicon chip is attached to the exposed adhesive tape surface at the bottom of the first opening. The chip has an active surface and a back surface. The chip further includes a plurality of bonding pads on the active surface. The back surface of the chip is attached to the adhesive tape. A patterned dielectric layer is formed filling the first opening and covering a portion of the adhesive tape, the active surface, the bonding pad and the insulating core layer. The patterned dielectric layer has a plurality of openings that exposes the bonding pads and some through holes. A metallic layer is formed over the exposed surface of the openings and the upper surface of the patterned dielectric layer by electroplating.

Abstract: A method of fabricating a multi-chip module (MCM) package that can fabricate the substrate and the package simultaneously. The bonding pads of a chip are exposed by forming a patterned dielectric layer, and the bonding pads of the chip are electrically connected to the substrate by utilizing to an electroplating to form a metal layer. The present invention provides a fabircating method that can prevent air bubble produced in the patterned dielectric layer and improve the connection ability between the chip and the substrate.

Abstract: A semiconductor memory device comprises: a memory cell array including memory cells arranged in the form of a matrix; a redundant cell array including redundant cells arranged for relieving a defective memory cell of the memory cell array; a defective address memory circuit including first and second memory circuits using different programming methods for storing an address of the defective memory cell of the memory cell array; and a substitution control circuit for controlling the substitution of one of the redundant cells of the redundant cell array for the defective memory cell of the memory cell array on the basis of memory data of the defective address memory circuit. Thus, it is possible to provide a semiconductor memory device capable of reducing the area occupied by a defective address memory circuit and surely carrying out defect relief, and a method for producing the same.

Abstract: In order to realize a semiconductor device of enhanced TFT characteristics, a semiconductor thin film is selectively irradiated with a laser beam at the step of crystallizing the semiconductor thin film by the irradiation with the laser beam. By way of example, only driver regions (103 in FIG. 1) are irradiated with the laser beam in a method of fabricating a display device of active matrix type. Thus, it is permitted to obtain the display device (such as liquid crystal display device or EL display device) of high reliability as comprises the driver regions (103) made of crystalline semiconductor films, and a pixel region (102) made of an amorphous semiconductor film.

Abstract: Contamination of an interface of respective films constituting a TFT due to an contaminant impurity in a clean room atmosphere becomes a great factor to lower the reliability of the TFT. Besides, when an impurity is added to a crystalline semiconductor film, its crystal structure is broken. By using an apparatus for manufacturing a semiconductor device including a plurality of treatment chambers, a treatment can be made without being exposed to a clean room atmosphere in an interval between respective treatment steps, and it becomes possible to keep the interface of the respective films constituting the TFT clean. Besides, by carrying out crystallization after an impurity is added to an amorphous semiconductor film, the breakdown of the crystal structure of the crystalline semiconductor film is prevented.

Abstract: A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800° C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i.e., the resistance remains low when annealing temperatures extend up to and beyond 800° C.

Abstract: A method of manufacturing a vertical transistor. The vertical transistor utilizes a deposited amorphous silicon layer to form a source region. The vertical gate transistor includes a double gate structure for providing increased drive current. A wafer bonding technique can be utilized to form the substrate.

Abstract: Methods of manufacturing semiconductor devices having low resistance reduced channel length transistors. Spacers are formed on each side of trenches that define the location of transistor channels. The spacers are formed with a dimension between the spacers that is less than a dimension available from photolithography systems currently available. A layer of gate oxide and a polysilicon gate are formed within the dimension resulting in transistors having channels length less than that available from standard photolithographic methods of forming gates and channels.

Abstract: Submicron-dimensioned, MOSFET devices are formed using multiple implants for forming an impurity concentration distribution profile exhibiting three impurity concentration peaks at a predetermined depths below the semiconductor surface substrate. The inventive method reduces “latch-up” and “punch-through” with controllable adjustment of the threshold voltage.

Abstract: The invention includes a laterally diffused metal oxide semiconductor transistor comprising a gate electrode and comprising tapered oxide self aligned to the gate electrode and a method of making the transistor.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.

Abstract: A three-dimensional ferroelectric structure and fabrication method are provided. The ferroelectric capacitor structure permits immediate contact between a noble metal capacitor electrode and a transistor electrode. This direct connection minimizes process steps and electrical resistance between capacitor and transistor. A damascene capacitor electrode formation process makes the task of etching the noble metal less critical. Regardless of whether a noble metal capacitor electrode is used, the damascene formation process permits both larger, and more space efficient, capacitors. Further, the damascene capacitor formation process can be used to simultaneously form electrical interlevel interconnections to the transistor drain. Another variation of the invention provides for a dual damascene version of the ferroelectric capacitor.

Abstract: A method of fabricating a semiconductor memory device, including a step of forming first and second side wall insulation films which includes the steps of: depositing a first insulation film on the gate electrode such that the first insulation film covers the first and second side walls of the gate electrode; applying a first anisotropic etching process proceeding generally perpendicularly to a principal surface of the substrate, to the first insulation film to form first and second lower side wall insulation films, respectively, on the first and second side walls of the gate electrode in an intimate contact therewith; exposing the first and second lower side wall insulation films to a nitriding atmosphere; depositing a second insulation film on the gate electrode such that the second insulation film covers the first and second lower side wall insulation films; and applying a second anisotropic etching process proceeding generally perpendicularly to the process proceeding generally perpendicularly to the prin

Abstract: A capacitor in a semiconductor integrated circuit is fabricated having a fixed charge density introduced near an electrode/dielectric interface. The fixed charge density compensates for the effects of a depletion layer, which would otherwise lower the effective capacitance. By shifting the undesirable effect of the depletion capacitance outside of the operating voltage range, the capacitor is effectively converted to an accumulation mode. The fixed charge density is preferably introduced by a plasma nitridation process performed prior to formnation of the capacitor dielectric.

Abstract: The method for manufacturing a Semiconductor Memory according to the present invention comprises a step for forming a gate insulator film on the surface of a semiconductor substrate; a step for forming a mask layer having a through-hole provided in the position where a tunnel window is to be formed, on top o said gate insulator film; a step for forming an impurity region in the vicinity of the surface of said semiconductor substrate by introducing an impurity using the mask layer; and a step for forming a tunnel insulator film on the surface of the semiconductor substrate, using a mask layer. In the present invention, the position in which the source is formed and the position in which the tunnel window is formed are determined by means of the position of the same through-hole. Therefore, the manufacturing error in the distance between the tunnel window and the source can be nullified.

Abstract: A method for fabricating a semiconductor integrated circuit device including a memory cell of a MISFET and a capacitor element formed in a memory cell-forming region of a semiconductor substrate, and an n channel-type MISFET and a p channel-type MISFET in a peripheral circuit-forming region, including: forming a gate insulating film on a semiconductor substrate; forming a polysilicon film and a high melting metal film on the gate insulating film, patterning to form a gate electrode in a memory cell-forming region and in a peripheral circuit-forming region, respectively; removing the high melting metal film from the gate electrode of the peripheral circuit-forming region; and depositing a metal layer over the peripheral circuit-forming region, followed by thermal treatment to form a silicide film on the polysilicon film in the gate electrode and a high concentration diffusion layer of the peripheral circuit-forming region.

Abstract: Methods of fabricating a high power RF lateral diffused MOS transistor (LDMOS) having increased reliability includes fabricating an N-drift region for the drain prior to fabrication of the gate contact and other process steps in fabricating the transistor. The resulting device has reduced adverse affects from hot carrier injection including reduced threshold voltage shift over time and reduced maximum current reduction over time. Linearity of device is maximized along with increased reliability while channel length is reduced.

Abstract: An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable to minimize the overlap capacitance in the device. The RSD construction uses a selective epitaxial process to effectively reduce the drain-source resistance. This improvement is even more significant in thin-film SOI technology. Using an RSD, the film outside the channel area thickens which, in turn, reduces the parasitic resistance.

Abstract: A MOSFET transistor and method of fabrication are described for engineering the channel dopant profile within a MOSFET transistor utilizing a single deep implantation step and solid-phase epitaxy. The method utilizes the formation of an L-shaped spacer having reduced height “cutouts” adjacent to the gate stack. The L-shaped spacer is preferably created by depositing two layers of insulating material, over which a third spacer is formed as a mask for removing unwanted portions of the first and second insulation layers. Amorphization and deep implantation is performed through the L-shaped spacer, wherein the junction contour is profiled in response to the geometry of the L-shaped spacer, such that a single deep implantation step may be utilized. Pocketed steps within the contoured junction reduce short-channel effects while allowing the formation of silicide to a depth which exceeds the junction depth implanted beneath the gate electrode.

Abstract: There are provide a semiconductor device capable of increasing the operating speed of MOS transistors and improving current driving capability, and a method of manufacturing such a semiconductor device. A semiconductor device comprises a silicon substrate (1), an element isolation insulation film (2), a gate structure selectively formed on the main surface of the silicon substrate (1), and a sidewall (6) formed on the side face of the gate structure. The gate structure has a laminated structure with a gate insulation film (3) formed of a silicon oxide film, a gate electrode (4) formed of polysilicon, and a cobalt silicide layer (5) stacked in this order.

Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.

Abstract: Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

Abstract: Floating body effects are substantially reduced by strategically forming source-side stacking faults to create a leakage path from the body to the source of an SOI structure. Embodiments include ion implanting a heavy ion, such as Xe, to form a buried amorphous layer in the source-side of the silicon layer after source/drain implants followed by silicidation, during which the buried amorphous region recrystallizes creating source-side stacking faults.

Abstract: A method of manufacturing a bipolar transistor in an N-type semiconductor substrate, including the steps of depositing a first base contact polysilicon layer and doping it; depositing a second silicon oxide layer; forming in the first and second layers an opening; annealing to form a third thin oxide layer and harden the second oxide layer; implanting a P-type dopant; depositing a fourth silicon nitride layer; depositing a fifth silicon oxide layer and etching it; anisotropically etching the fifth, fourth, and third layers; performing cleanings during which the fifth layer is reetched and takes a flared profile; depositing a sixth polysilicon layer; and implanting an N-type dopant.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a stepped collector dopant profile that reduces emitter-collector transit time and parasitic resistance with minimal increase in parasitic capacitances. The preferred stepped collector dopant profile includes a shallow implant and a deeper implant. The shallow implant reduces the base-collector space-charge region width, reduce resistance, and tailors the collector-base breakdown characteristics. The deeper implant links the buried collector to the subcollector and provides a low resistance path to the subcollector. The stepped collector dopant profile has minimal impact on the collector-base capacitance outside the intrinsic region of the device since the higher dopant is compensated by, or buried in, the extrinsic base dopants outside the intrinsic region.

Abstract: Isolation of a heterojunction bipolar transistor device in an integrated circuit is accomplished by forming the device within a trench in dielectric material overlying single crystal silicon. Precise control over the thickness of the initially-formed dielectric material ultimately determines the depth of the trench and hence the degree of isolation provided by the surrounding dielectric material. The shape and facility of etching of the trench may be determined through the use of etch-stop layers and unmasked photoresist regions of differing widths. Once the trench in the dielectric material is formed, the trench is filled with selectively and/or nonselectively grown epitaxial silicon. The process avoids complex and defect-prone deep trench masking, deep trench silicon etching, deep trench liner formation, and dielectric reflow steps associated with conventional processes.

Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.

Abstract: In one disclosed embodiment, a collector is deposited and a base is grown on the collector, for example, by epitaxially depositing either silicon or silicon-germanium. An emitter is fabricated on the base followed by implant doping an extrinsic base region. For example, the extrinsic base region can be implant doped using boron. The extrinsic base region doping diffuses out during subsequent thermal processing steps in chip fabrication, creating an out diffusion region in the device, which can adversely affect various operating characteristics, such as parasitic capacitance and linearity. The out diffusion is controlled by counter doping the out diffusion region. For example, the counter doped region can be implant doped using arsenic or phosphorous. Also, for example, the counter doped region can be formed using tilt implanting or, alternatively, by implant doping the counter doped region and forming a spacer on the base prior to implanting the extrinsic base region.

Abstract: Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

Abstract: In accordance with the objectives of the invention a new method is provided for the definition and delineation of active regions in the surface of a semiconductor substrate. A layer of pad oxide is grown on the surface of the substrate, the layer of pad oxide is patterned and etched whereby the pad oxide remains in place over areas where the isolation regions are to be created. The underlying silicon substrate is in this manner exposed; the regions of the silicon substrate that are exposed are the regions of the substrate where active devices are to be created. The exposed surface of the substrate is cleaned; the openings in the layer of pad oxide are selectively filled with a deposition of epitaxial silicon. The created structure is heat treated to improve the interface between the patterned and etched layer of pad oxide and the deposited epitaxial silicon. The created pattern of pad oxide can now be used as regions of field isolation over the surface of the substrate.

Abstract: A method for forming a silicon on insulator substrate includes the step of dissociating a plasma of molecules including at least any one of oxygen and nitrogen to obtain ions. The ions are accelerated by passage through gaps between acceleration electrodes at a predetermined acceleration energy for irradiation of the accelerated ions onto a silicon substrate which is heated to form an insulation film within the silicon substrate.