Patents Issued in January 14, 2003
  • Patent number: 6506663
    Abstract: A method for providing an SOI wafer that includes, on a wafer of monocrystalline semiconductor material, forming a hard mask of an oxidation-resistant material, defining first protective regions covering first portions of the wafer; excavating the second portions of the wafer, forming initial trenches extending between the first portions of the wafer; thermally oxidating the wafer, forming a sacrificial oxide layer extending at the lateral and base walls of the initial trenches, below the first protective regions; and wet etching the wafer, to completely remove the sacrificial oxide layer. Thereby, intermediate trenches are formed, the lateral walls of which are recessed with respect to the first protective regions. Subsequently, a second oxide layer is formed inside the intermediate trenches; a second silicon nitride layer is deposited; final trenches are produced; a buried oxide region is formed, and finally an epitaxial layer is grown.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: January 14, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gabriele Barlocchi, Flavio Villa
  • Patent number: 6506664
    Abstract: The present invention provides a method of transfer of a first planar substrate with two major surfaces to a second substrate, comprising the steps of: forming the first planar substrate, attaching one of the major surfaces of the first planar substrate to a carrier by means of a release layer; attaching the other major surface of the first substrate to the second substrate with a curable polymer adhesive layer; partly curing the polymer adhesive layer, disconnecting the release layer from the first substrate to separate the first substrate from the camer, followed by coing the polymer adhesive layer.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: January 14, 2003
    Assignees: IMEC VZW, Alcatel
    Inventors: Eric Beyne, Augustin Coella-Vera
  • Patent number: 6506665
    Abstract: An SOI substrate having on the surface thereof a single crystal silicon film formed on an insulator is heat-treated in a hydrogen-containing reducing atmosphere in order to smooth the surface and reduce the boron concentration without damaging the film thickness uniformity in a single wafer and among different wafers. The method is characterized in that the single crystal silicon film is arranged opposite to a member of non-oxidized silicon for heat treatment.
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: January 14, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobuhiko Sato
  • Patent number: 6506666
    Abstract: A method of fabricating an SrRuO3 thin film is disclosed. The method utilizes a multi-step deposition process for the separate control of the Ru reagent, relative to the Sr reagent, which requires a much lower deposition temperature than the Sr reagent. A Ru reagent gas is supplied by a bubbler and deposited onto a substrate. Following the deposition of the Ru reagent, the Sr liquid reagent is vaporized and deposited onto the Ru layer.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: January 14, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 6506667
    Abstract: A method of growing epitaxial semiconductor layers with reduced crystallographic defects. The method includes growing a first epitaxial semiconductor layer on a semiconductor substrate under conditions of relatively high temperature and low source gas flow to heal defects in or on the surface of the substrate. Subsequently, a second epitaxial semiconductor layer is grown on the first layer under conditions of relatively low temperature and high source gas flow. The first epi layer acts as a low-defect seed layer by preventing defects in the surface of the substrate from propagating into the second epi layer. Optionally, a hydrogen chloride etch may be employed during a portion of the first epi layer growth to increase the efficacy of the first layer.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: January 14, 2003
    Assignee: SEH America, Inc.
    Inventors: Mark R. Boydston, Gerald R. Dietze, Oleg V. Kononchuk
  • Patent number: 6506668
    Abstract: A method of forming interconnects on a semiconductor chip is disclosed which comprises the steps of: depositing a barrier layer and a copper seed layer on the semiconductor chip; depositing on the copper seed layer an enhancement layer; annealing the semiconductor chip a first time after the copper seed layer and the enhancement layer are deposited to form an annealed layer; electroplating a copper layer on the semiconductor chip; and annealing the semiconductor chip a second time after the copper layer is deposited on the annealed layer to form an annealed copper conductive layer.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: January 14, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Connie Pin-Chin Wang, Steve C. Avanzino
  • Patent number: 6506669
    Abstract: There are reduced degradation of the performance of a transistor element, variations in the quality thereof, and the like resulting from the surface roughness of a polycrystalline silicon thin film formed by laser annealing, particularly from the presence of portions in which tramp materials are segregated produced in the rough portions. For this purpose, (1) The projections at the surface portion of the polycrystalline silicon thin film and the portions in which the tramp materials are segregated after laser annealing are chemically, mechanically graded. (2) Likewise, a heat treatment is performed to grow a crystal and planarize the rough portions, while removing the tramp materials in the surface.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: January 14, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keizaburo Kuramasu, Atsushi Sasaki, Tetsuo Kawakita
  • Patent number: 6506670
    Abstract: A method for making a gate in an integrated circuit. A gate layer is formed on a substrate, and a blocking layer is formed on the gate layer. The blocking layer is masked with a photoresist layer, and the photoresist layer is developed to define an exposed gate area. The blocking layer is etched in the gate area to expose the gate layer in the gate area, and the photoresist layer is removed. A metal layer is formed on the blocking layer and on the gate layer in the gate area. The metal layer is selectively reacted with the gate layer in the gate area to form a hard mask over the gate layer in the gate area. The metal layer is removed from the blocking layer. The blocking layer is selectively etched without substantially etching the hard mask in the gate area, to expose the gate layer surrounding the gate area. The exposed gate layer is etched to define a gate in the gate area. The hard mask remains on the gate, and functions as an electrical contact to the gate.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: January 14, 2003
    Assignee: LSI Logic Corporation
    Inventor: Philippe Schoenborn
  • Patent number: 6506671
    Abstract: Dielectric rings to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the rings on semiconductor devices and other substrates. Semiconductor devices including the rings and having contact pads exposed through the rings are also disclosed. One or more of the rings are disposed around the contact pads of a semiconductor device or other substrate before or after solder balls are secured to the contact pads. Upon connecting the semiconductor device face-down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the rings prevent the material of solder balls protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The rings may be preformed structures which are attached to a surface of a semiconductor device or other substrate.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: January 14, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Ford B. Grigg
  • Patent number: 6506672
    Abstract: A electroless plating method re-metallizes aluminum bond pads so that the re-metallized bond pads include layers of aluminum, zinc, nickel, and gold. The re-metallized bond pads are wire-bondable and solder wettable, and therefore can be flip-chip bonded. Applications include the realization of hybrid smart pixel arrays for optical interconnections, where an optical transmitter and optical detector are flip-chip bonded directly to respective CMOS driver chips.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: January 14, 2003
    Assignee: University of Maryland, College Park
    Inventors: Mario Dagenais, Scott A. Merritt, Madhumita Datta
  • Patent number: 6506673
    Abstract: The present invention provides a method that includes defining a dummy gate structure comprising a spin on glass on a semiconductor substrate, forming a dielectric layer over the dummy gate structure, removing the dummy gate structure to form a gate opening within the dielectric layer, and forming a gate material comprising a metal within the gate opening.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: January 14, 2003
    Assignee: Agere Systems Guardian Corp.
    Inventors: Yi Ma, Huili Shao, Joseph A. Taylor, Allen Yen
  • Patent number: 6506674
    Abstract: A hole is formed on an insulating film made of silicon oxide by selectively plasma-etching the insulating film with an etching gas containing C5F8, O2, and Ar firstly under a condition in which the deposition property of a polymer layer is weak and secondly under a condition in which that of the polymer layer is strong.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: January 14, 2003
    Assignees: Hitachi, Ltd., NEC Corporation
    Inventors: Takenobu Ikeda, Masahiro Tadokoro, Masaru Izawa, Takashi Yunogami
  • Patent number: 6506675
    Abstract: Disclosed is a copper film selective formation method capable of reducing the material cost by selectively depositing copper in a necessary region of an undercoat film made of an arbitrary material such as a metal or an insulating material. This copper film selective formation method includes the steps of forming a thin film of a silane coupling agent or a surfactant on an undercoat film on a substrate, making a prospective copper film region of the thin film hydrophilic, and selectively forming a copper film in the hydrophilic prospective copper film region of the undercoat film by CVD of copper.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: January 14, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kayoko Oomiya, Keiji Suzuki, Keisaku Yamada
  • Patent number: 6506676
    Abstract: A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: January 14, 2003
    Assignee: Hynix Semiconductor Inc
    Inventors: Dae Gyu Park, Tae Ho Cha, Se Aug Jang, Heung Jae Cho, Tae Kyun Kim, Kwan Yong Lim, In Seok Yeo, Jin Won Park
  • Patent number: 6506677
    Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH3 and N2, ramping up the introduction of SiH4 and then initiating deposition of a silicon nitride capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH3 plasma diluted with N2, ramping up the introduction of SiH4 in two stages, and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure, N2 flow rate and NH3 flow rate during plasma treatment, SiH4 ramp up and silicon nitride deposition. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: January 14, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven C. Avanzino, Minh Van Ngo, Amit P. Marathe, Hartmut Ruelke
  • Patent number: 6506678
    Abstract: An aluminum layer formed over an integrated circuit structure is patterned to form a plurality of aluminum metal lines. The patterned aluminum metal lines are then anodized in an acid anodizing bath to form anodized aluminum oxide on the exposed sidewall surfaces of the patterned aluminum. The anodization may be carried out until the anodized aluminum films on horizontally adjacent aluminum metal lines contact one another, or may be stopped prior to this point, leaving a gap between the anodized aluminum oxide films on adjacent aluminum metal lines. This gap may then be either filled with other low k dielectric material or by standard (non-low k) dielectric material. A capping layer of non-porous dielectric material is then formed over the porous anodized aluminum oxide.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: January 14, 2003
    Assignee: LSI Logic Corporation
    Inventor: Valeriy Sukharev
  • Patent number: 6506679
    Abstract: A method of manufacturing semiconductor devices using an improved planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer using a fixed flexible planar interface material contacting the deformable material.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: January 14, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Hugh E. Stroupe, Brian F. Gordon
  • Patent number: 6506680
    Abstract: In a semiconductor manufacturing method, etching control is provided by introducing a material containing a material having at least one of an —H, —C, —CH, —CH2, and —CH3 radical component, e.g., Si—O—C, in a lower portion or layer of a dielectric layer formed during a semiconductor manufacturing process. A semiconductor device made by the method includes a first dielectric layer of a material having a given amount of carbon formed on the semiconductor substrate, and a second dielectric layer of a material having a lesser amount of carbon formed on said first dielectric layer wherein the second dielectric layer has an etched pattern formed by etching the second dielectric layer to a depth determined by etching resistance of first dielectric layer.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: January 14, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-Goo Kim, Jae-Sung Hwang
  • Patent number: 6506681
    Abstract: Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of the present invention, a mold compound is interspersed between conductive bumps on the active face of a wafer to provide support and protection for the wafer structure both during and after a process of removing the wafer's inactive backside silicon surface. The mold compound also serves to preserve the integrity of the conductively bumped aspects of the wafer during subsequent processing and may, after the wafer is diced, act as all or part of an underfill material for flip-chip applications.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: January 14, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Ford B. Grigg, Timothy L. Jackson
  • Patent number: 6506682
    Abstract: The present invention relates to non-selective slurries for chemical-mechanical polishing of a metal layer and a method for manufacturing thereof, and further to a method for forming a plug in an insulating layer on a wafer using such a slurry. More particularly, a slurry is provided for polishing chemically and mechanically simultaneously a metal layer, a barrier layer and an insulating layer used in a semiconductor integrated circuit, which maintains a pH in the range of weak acidity to weak alkalinity by including a first oxidizing agent to reduce a second oxidizing agent, the second oxidizing agent originally being reduced by oxidizing a metal layer. The second oxidizing agent is recycled by recovering the oxidizing power of the first oxidizing agent. An additive increases a polishing rate of the barrier layer and an abrasive is provided to the slurry in an aqueous medium.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: January 14, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Lee, Sang Rok Hah
  • Patent number: 6506683
    Abstract: A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) is fabricated by performing a number of process steps in-situ. Semiconductor devices having local interconnect areas are formed on a surface of a semiconductor substrate. An etch stop layer is formed over the surface of the substrate and the devices, and an inter level dielectric layer (ILD) is formed over the etch stop layer. An antireflection layer (ARC) is formed over the insulator layer, and a photoresist layer is formed over the insulator layer. The photoresist layer is photolithographically patterned to form first holes therethrough which overlie the interconnect areas. Using the patterned photoresist layer as a mask, second holes which underlie the first holes are etched using Reactive Ion Etching (RIE) through the antireflection layer to the insulator layer. Third holes are etched through the insulator layer down to the etch stop layer.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: January 14, 2003
    Assignee: Advanced Micro Devices
    Inventors: Angela T. Hui, Yongzhong Hu
  • Patent number: 6506684
    Abstract: A method for etching a surface of an integrated circuit. A layer of photoresist is applied to the surface of the integrated circuit. The layer of photoresist is exposed and developed, and the surface of the integrated circuit is etched with an etchant that contains chlorine. The surface of the integrated circuit is exposed to tetra methyl ammonium hydroxide to neutralize the chlorine, and rinsed with water.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: January 14, 2003
    Assignee: LSI Logic Corporation
    Inventors: David W. Daniel, Dodd C. Defibaugh
  • Patent number: 6506685
    Abstract: The invention relates to a plasma processing reactor apparatus for semiconductor processing a substrate. The apparatus includes a chamber. The apparatus further includes a top electrode configured to be coupled to a first RF power source having a first RF frequency and a bottom electrode configured to be coupled to second RF power source having a second RF frequency that is lower than the first RF frequency. The apparatus additionally includes an insulating shroud that lines an interior of the chamber, the insulating shroud being configured to be electrically floating during the processing. The apparatus further includes a perforated plasma confinement ring disposed outside of an outer periphery of the bottom electrode, a top surface of the perforated plasma confinement ring being disposed below a top surface of the substrate and electrically grounded during the processing.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: January 14, 2003
    Assignee: Lam Research Corporation
    Inventors: Lumin Li, George Mueller
  • Patent number: 6506686
    Abstract: In a plasma processing apparatus that has a vacuum chamber, a process gas supply means of supply gas to a processing chamber, an electrode to hold a sample inside said vacuum chamber, a plasma generator installed in said vacuum chamber opposite to said sample, and a vacuum exhaust system to decrease pressure of said vacuum chamber, a bias voltage of Vdc=−300 to −50 V is applied and the surface temperature of said plate ranges from 100 to 200° C. In addition, the surface temperature fluctuation of the silicon-made plate in said plasma processing apparatus is kept within ±25° C.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: January 14, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Masuda, Kazue Takahashi, Ryoji Fukuyama, Tomoyuki Tamura
  • Patent number: 6506687
    Abstract: A technique of dry etching the surface of a wafer by using a dry etching apparatus in which the distance between a wafer and a surface facing the wafer is set to the half or less of the diameter of the wafer is disclosed. Even in the case of using, especially, a wafer having a large diameter, the incident amount of etching reaction by-products in the peripheral portion of the wafer and that in the center portion of the wafer are uniformed. Thus, a uniform etching process over the whole surface of the wafer can be realized.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: January 14, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masaru Izawa, Shinichi Tachi
  • Patent number: 6506688
    Abstract: A method for removing a photoresist layer on wafer edge is disclosed. The invention uses a light source located under a spin on coated wafer mounted on a supporting mean of a rotatable chuck to expose the photoresist material on the wafer edge. First of all, the spin on coated wafer is mounted on the supporting mean of the rotatable chuck. Then the rotatable chuck is rotated and the wafer is exposed to the light source. Finally, the wafer is developed.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: January 14, 2003
    Assignee: Macronix International Co., Inc.
    Inventor: I-Pien Wu
  • Patent number: 6506689
    Abstract: A method for removing contaminants from a semiconductor wafer having a spin on coating of material. Contaminants are removed by applying a cleaning solution to the periphery, and preferably, the exposed backside of the wafer after the edge bead has been dissolved and removed. The cleaning solution is formulated to react chemically with unwanted coating material residue to form a compound that may be ejected from the periphery of the spinning wafer. Any residual solution or precipitate that is not ejected from the wafer may be rinsed away with water, preferably deoinized water. One exemplary use of this method is the removal of metallic contaminants that may be left on the periphery and backside of a wafer after the formation of ferroelectric film coatings. A cleaning solution comprising a mixture of hydrochloric acid HCl and water H2O or,ammonium hydroxide NH4OH and water H2O is applied to the periphery of the spinning wafer.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: January 14, 2003
    Assignee: Micron Technology, Inc.
    Inventor: J. Brett Rolfson
  • Patent number: 6506690
    Abstract: An intermediary dielectric layer is disposed between two dielectric layers thereby eliminating a flow stabilization step that may produce unwanted deposition that leads to peeling. A wafer is provided having an HDP layer. An undoped silicon glass layer is deposited on top of the HDP layer to improve adherence of a subsequently deposited PSG layer.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: January 14, 2003
    Assignee: Agere Systems Inc.
    Inventor: Jonathon M. Lobbins
  • Patent number: 6506691
    Abstract: A method for high rate silicon nitride deposition at low pressures, including a method of operating a CVD reactor providing a novel combination of wafer temperature, gas flow and chamber pressure resulting in both rapid deposition and a uniform, smooth film surface. According to the method, a wafer is placed in a vacuum chamber wherein a reactant gas flow of silane and ammonia is directed in parallel with the wafer surface via a plurality of temperature controlled gas injectors, the gas being confined to a narrow region above the wafer. The gas is injected at a high velocity, causing the deposition rate to be limited only by the rate of delivery of unreacted gas to the wafer surface and the rate of removal of reaction byproducts. The high velocity gas stream passing across the wafer has the effect of thinning the layer adjacent the wafer surface containing reaction by-products, known as the “boundary layer,” resulting in faster delivery of the desired reactant gas to the wafer surface.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: January 14, 2003
    Assignee: Torrex Equipment Corporation
    Inventors: Robert C. Cook, Daniel L. Brors
  • Patent number: 6506692
    Abstract: A method of converting a hydrophobic surface of a silicon carbide layer to a hydrophilic surface is described. That method comprises forming a silicon carbide containing layer on a substrate, then operating a PECVD reactor to generate a plasma that converts the surface of that layer from a hydrophobic surface to a hydrophilic surface. Also described is a method for making a semiconductor device that employs this technique.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: January 14, 2003
    Assignee: Intel Corporation
    Inventor: Ebrahim Andideh
  • Patent number: 6506693
    Abstract: A semiconductor processing system having a holding chamber coupled to a mainframe processing system and at least one loadlock chamber coupled to the holding chamber in which unprocessed wafers are transferred from the loadlock chamber to the holding chamber for subsequent processing by the mainframe system.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: January 14, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Roger V. Heyder, Thomas B. Brezocsky, Robert E. Davenport
  • Patent number: 6506695
    Abstract: This invention provides breathable composite materials with good liquid barrier properties comprising a laminate of a nonwoven web layer and a breathable film layer wherein breathability of the composite is provided by a plurality of point-like deformations of the film layer. In one embodiment, the composites also have a soft, cloth-like texture at at least one surface thereof. Also provided is a process for making such composites comprising applying a molten film-forming resin composition capable of developing breathability on deformation to a nonwoven web, cooling the molten composition to form a coated web having a web layer bonded to a film layer, and subjecting the coated web to heat and pressure at a plurality of points on a surface thereof wherein the heat, pressure and density of, and proportion of the composite surface occupied by, the deformations are effective to impart breathability to the film without loss of liquid barrier properties.
    Type: Grant
    Filed: April 20, 1999
    Date of Patent: January 14, 2003
    Assignee: Rheinische Kunststoffewerke GmbH
    Inventors: Hugh C. Gardner, Jeffrey H. Mumm, Kam C. Lui
  • Patent number: 6506696
    Abstract: A process for forming a synthetic based nonwoven web bonded with a crosslinkable polymer wherein an aqueous polymeric emulsion containing a crosslinkable polymer is applied to the synthetic based nonwoven web, the water removed, and the crosslinkable polymer crosslinked. The crosslinkable polymer incorporates acetoacetate functionality and carboxylic acid functionality; wherein crosslinking is achieved by the reaction of the acetoacetate with an effective amount of a polyaldehyde and the reaction of the carboxylic acid with an effective amount of a polyaziridine compound.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: January 14, 2003
    Assignee: Air Products Polymers, L.P.
    Inventors: Joel Erwin Goldstein, Ronald Joseph Pangrazi
  • Patent number: 6506697
    Abstract: The present invention provides a textile material comprising a tightly woven paper fabric having a backing applied on only one side. The tight weave allows the backing to be applied as a liquid, whereupon curing cause the liquid to harden. The backing confers additional strength and durability to the paper fabric and allows mass production of paper fabrics by the formation of a continuous sheet that can be cut to desired dimensions and shapes without fraying at the edges. The present invention also provides methods for forming tightly woven fabrics and for applying a backing onto this fabric.
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: January 14, 2003
    Assignee: Merida Meridian, Inc.
    Inventor: Hiram M. Samel
  • Patent number: 6506698
    Abstract: The present invention provides a composite nonwoven fabric with a superior combination of extensibility, tensile properties and abrasion resistance. The composite nonwoven fabric (10) comprises at least one layer containing multipolymer fibers, with a plurality of bonds bonding the fibers together to form a coherent extensible nonwoven web (11). This coherent extensible nonwoven web (11) has a Taber surface abrasion value (rubber wheel) of greater than 10 cycles and an elongation at peak load in at least one of the machine direction or the cross-machine direction of at least 70%. A second extensible layer (12) is laminated to this coherent extensible nonwoven web (11).
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: January 14, 2003
    Assignee: BBA Nonwovens Simpsonville, Inc.
    Inventors: Thomas E. Quantrille, Harold E. Thomas, Barry D. Meece, Scott L. Gessner, J. Darrell Gillespie, Jared A. Austin, David D. Newkirk, William Fowells
  • Patent number: 6506699
    Abstract: A negative thermal expansion glass ceramic having a negative coefficient of thermal expansion, which is a sufficiently large absolute value in a temperature range of −40° C. to +160° C. and a method for producing the same are provided. The negative thermal expansion glass ceramic has a coefficient of thermal expansion of −25 to −100×10−7/° C. in the temperature range of −40° C. to +160° C., and comprises main crystalline phases which are one or more types selected from a group consisting of &bgr;-eucryptite solid solution (&bgr;-Li2O.Al2O3.2SiO2 solid solution), &bgr;-eucryptite (&bgr;-Li2O.Al2O3.2SiO2), &bgr;-quartz solid solution (&bgr;-SiO2 solid solution), and &bgr;-quartz (&bgr;-SiO2), wherein a total amount of crystals of the main crystalline phases can be 70 to 100% in mass percent.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: January 14, 2003
    Assignee: Kabushiki Kaisha Ohara
    Inventors: Ayako Shindo, Naoyuki Goto
  • Patent number: 6506700
    Abstract: This invention concerns glass sheets made from a glass containing, in percentages by weight, from 0.85 to 2% of total iron expressed in the form Fe2O3, the content by weight of FeO being from 0.21 to 0.40%, said sheets having, for a thickness of from 2 to 3 mm, a factor (TLA) of at least 70%, a factor (TE) less than 50% and a factor (TUV) less than 25%. The sheets according to the invention are more especially intended for the production of lateral panes for automobile vehicles.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: January 14, 2003
    Assignee: Saint-Gobain Glass France
    Inventors: Jean-Marie Combes, Michel Lismonde
  • Patent number: 6506701
    Abstract: Novel polymer-supported quenching reagents of Formula I, P—L—Q  I wherein P is a polymer of low chemical reactivity which is soluble or insoluble; Q is one or more quenching reagents, or an acid or base addition salts thereof, that are capable of selective covalent reaction with unwanted byproducts, or excess reagents; and L is one or more chemically robust linkers that join P and Q; are described, as well as methods for their preparation and methods for their use in the rapid purification of synthetic intermediates and products in organic synthesis, combinatorial chemistry and automated organic synthesis.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: January 14, 2003
    Assignee: Warner-Lambert Company
    Inventors: Gary L. Bolton, Richard J. Booth, Mark W. Creswell, John C. Hodges, Joseph S. Warmus, Michael W. Wilson
  • Patent number: 6506702
    Abstract: The invention concerns a process for regenerating a catalyst in a fixed bed, for example a catalyst for reforming or for aromatic compound production, including a step for monitoring and controlling combustion completion which is carried out after the catalyst has undergone all of the combustion steps of the process. The monitoring and control step is carried out by injecting an oxygen-containing gas into the zone where monitoring and control takes place, the monitoring and control step being carried out under conditions which are more severe than those in the combustion steps. The monitoring and control step is carried out with an oxygen consumption of less than 10%. The temperature advantageously remains substantially constant.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: January 14, 2003
    Assignee: Institut Francais du Petrole
    Inventors: François-Xavier Brunet, Emmanuelle Bromet, Jean-Marie Deves, Dominique Humeau, Eric Sanchez
  • Patent number: 6506703
    Abstract: An ion exchange method is provided for loading and uniformly distributing noble metals into a catalyst substrate comprising a zeolite to make a monofunctional, non-acidic reforming catalyst. The catalyst substrate is contacted with an aqueous loading solution comprising noble metal cations and non-noble metal cations. The loading solution is formulated such that the equivalents of non-noble metal cations remaining in the catalyst not ionically bonded to the zeolite when loading is complete is 1.2 to 6.0 times the equivalents of non-noble metal cations displaced from the zeolite when the noble metal cations ion exchange into the zeolite, and simultaneously the endpoint pH of the loading solution is between 10.0 and 11.5. The required 1.2 to 6.0 ratio is achieved when the ratio of moles of non-noble metal cations added to the loading solution to moles of noble metal added to the loading solution is between 1 and 10.
    Type: Grant
    Filed: January 24, 2000
    Date of Patent: January 14, 2003
    Assignee: Exxon Mobil Chemical Patents Inc.
    Inventors: Jar-Lin Kao, Kenneth Ray Clem, Thomas Henry Vanderspurt, Shun Chong Fung
  • Patent number: 6506704
    Abstract: A process for forming neutral late transition metal chelates useful as polymerization catalysts comprising contacting a bidentate ligand forming compound that is free of electron-withdrawing groups with a di(tertiary amine) late transition metal reagent in the presence of an inert liquid, an olefinic monomer or a polar liquid selected from nitrites, ethers, aromatic heterocyclic amines, alcohols, nitroalkanes, nitroaromatics or mixtures thereof. The process provides a solid product or a solution of a storage stable transition metal bidentate ligand containing catalyst product which remains active for an extended storage period. Alternately, the present process can be conducted in situ in a polymerization zone of olefinic polymerization.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: January 14, 2003
    Assignee: Cryovac, Inc.
    Inventors: Donald Albert Bansleben, Eric Francis Connor, Robert Howard Grubbs, Jason Ivan Henderson, Todd Ross Younkin
  • Patent number: 6506705
    Abstract: The present invention relates to a composition based on cerium oxide or on cerium and zirconium oxides, in the extruded form, to a process for the preparation thereof and to the use thereof as catalyst. The process for the preparation of the composition of the invention is characterized in that a cerium hydroxide or oxyhydroxide or cerium and zirconium hydroxides or oxyhydroxides are extruded. The composition of the invention can be used as catalyst or catalyst support, in particular in the treatment of exhaust gases from internal combustion engines, in the process for the dehydrogenation of ethylbenzene to styrene, in the catalysis of methanation or in the treatment of a solution or suspension of organic compounds by oxidation via a wet route.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: January 14, 2003
    Assignee: Rhodia Chimie
    Inventors: Gilbert Blanchard, Eric Quemere
  • Patent number: 6506706
    Abstract: Compositions and methods for selectively binding metal ions from source solutions are disclosed. The composition is comprised of a polyamide-containing ligand covalently bonded to a particulate solid support through a hydrophilic spacer having the formula SS—A—X—L. In this formula, SS is a particulate solid support such as silica or a polymeric bead, A is a covalent linkage mechanism, X is a hydrophilic spacer grouping, and L is a polyamide-containing ligand having three or more amide groups and two or more amine nitrogens separated by at least two carbons with the proviso that when SS is a particulate organic polymer, A—X may be combined as a single covalent linkage.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: January 14, 2003
    Assignee: IBC Advanced Technologies, Inc.
    Inventors: Ronald L. Bruening, Krzysztof E. Krakowiak
  • Patent number: 6506707
    Abstract: Herbicidal compositions containing plant essential oils and mixtures or blends thereof. In addition, the present invention is directed to a method for controlling weeds and grasses by applying a herbicidally-effective amount of the above herbicidal compositions to a locus where weed and grass control is desired.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: January 14, 2003
    Assignee: Ecosmart Technologies, Inc.
    Inventor: Steven M. Bessette
  • Patent number: 6506708
    Abstract: 3-(Heterocyclyl)benzoylpyrazole derivatives of the formula I where: X is O, NH or N-alkyl; R1 is nitro, halogen, alkoxy, haloalkoxy, alkylthio, haloalkylthio, alkylsulfonyl or haloalkylsulfonyl; R2,R3,R4,R5 are hydrogen, alkyl or haloalkyl; R6 is halogen, nitro, haloalkyl, alkoxy, haloalkoxy, alkylthio, haloalkylthio, alkylsulfonyl or haloalkylsulfonyl; R7 is hydroxyl, alkoxy, alkenyloxy, alkylsulfonyloxy, alkylcarbonyloxy, (alkylthio)carbonyloxy, phenylsulfonyloxy or phenylcarbonyloxy, where the phenyl radical may be substituted; R8,R9 are alkyl; R10 is hydrogen or alkyl; R11 is hydrogen or alkyl; and their agriculturally useful salts, compounds for their preparation, and the use of these compounds or of compositions comprising them for controlling undesirable plants are described.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: January 14, 2003
    Assignee: BASF Aktiengesellschaft
    Inventors: Ulf Neidlein, Norbert Götz, Ulf Misslitz, Roland Götz, Ernst Baumann, Wolfgang von Deyn, Steffen Kudis, Klaus Langemann, Guido Mayer, Matthias Witschel, Martina Otten, Karl-Otto Westphalen, Helmut Walter
  • Patent number: 6506709
    Abstract: A high Tc superconducting ceramic material is produced by a method in which a mixture of chemicals in suitable amounts is compacted into a desired form. The compacted mixture is then fired and, at the same time, an electric current is caused to pass through the compacted mixture in a predetermined direction. By virtue of the passage of the current through the material during firing, the orderliness of the molecular arrangement is enhanced and an elevated transition temperature Tc is obtained.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: January 14, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6506710
    Abstract: A method for controlling the rheology of aqueous systems, particularly for those intended for underground use, includes injecting an aqueous viscoelastic fluid containing a surfactant gelling agent into the system. The viscoelastic surfactant composition of the invention comprises, as a gelling agent, at least one fatty aliphatic amidoamine oxide in a glycol solvent. The composition also maintains the levels of free fatty acid and free amine within critical parameters in order to achieve superior performance. The additives may be incorporated in the viscoelastic fluid to tailor its use in stimulation fluids, drilling muds, fracture fluids, and in applications such as permeability modification, gravel packing, cementing, and the like.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: January 14, 2003
    Assignee: Akzo Nobel N.V.
    Inventors: Michael D. Hoey, Ralph Franklin, Douglas M. Lucas, Maurice Dery, Randy E. Dobson, Michael Engel, James F. Gadberry, Ramanair S. Premachandran, Glenda Del Carmen Vale
  • Patent number: 6506711
    Abstract: Methods and compositions for reducing the precipitation of fluoride compounds following the contact of an aluminum containing subterranean formation with an acid solution containing hydrofluoric acid are provided. In accordance with the methods, a hydroxy carboxylic acid is combined with the hydrofluoric acid solution and the subterranean formation is contacted with the resulting acid solution.
    Type: Grant
    Filed: June 20, 1995
    Date of Patent: January 14, 2003
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Chris E. Shuchart, Rick D. Gdanski
  • Patent number: 6506712
    Abstract: Additives useful for reducing the coefficient of friction in lubricants, greases, or cosmetic formulations, and useful as a substitute for talc and as an anti-misting material are obtained by subjecting a raw plant material, such as cotton, to a dosage of radiation from an electron beam source. The irradiated plant material is subsequently fragmented, or micronized, to product the friction-reducing additive with a reduced diameter capable of reducing the coefficient of friction, used for anti-misting or as a substitute for talc in a variety of applications.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: January 14, 2003
    Assignee: React, LLC
    Inventor: Bruce A. Tavares
  • Patent number: 6506713
    Abstract: A cosmetic cleansing article is provided which includes an effervescent cleanser composition held within a sachet having at least one water permeable wall. The effervescent composition is an intimate mixture of an acid material such as citric acid and an alkaline material such as sodium bicarbonate. Water contact causes the combination to effervesce. The powdered mixture of alkaline/acid materials is storage stabilized against premature effervescent action by dispersing therewithin plant solids.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: January 14, 2003
    Assignee: Unilever Home & Personal Care USA, division of Conopco, Inc.
    Inventors: Craig Stephen Slavtcheff, Robert Edward Gott, Alexander Paul Znaiden