Abstract: A computer system and method for enhancing memory-to-memory copy operations includes transmitting from the processor to the source system control unit a plurality of memory-to-memory copy transactions where each transaction includes a source address and a destination address. A lookup operation is performed on the destination address to determine the destination system control unit that controls access to the destination memory which contains the destination address. A number of data blocks located at the source address in the source memory are retrieved and transmitted to the destination address. The number of data blocks are stored at the destination address in the destination memory.

Abstract: A system for reducing network traffic for remote file system accesses receives requests at a local computer system for access to a file on the remote server. If the request is a read operation, and the operation is directed to an unallocated region of the file on the remote server, the system returns a block of null values to the requestor without receiving the block of null values from the remote server. Otherwise, the system sends a request to the remote server to read from the file. If the request is a write operation, and the operation is directed to an unallocated region of the file on the remote server, the system sends a request to the remote server to allocate storage for the write operation. Next, the system writes the data into a local cache. Later, the system copies the data from the cache to the remote storage.

Abstract: Approaches for determining the actual physical topology of network devices in a network are disclosed. To determine a physical topology, a discovery mechanism determines a set of network addresses for identifying devices within a network. Based on the set of network addresses, the discovery mechanism identifies a group of devices that are associated with the network. Layer 2 and Layer 3 configuration information is gathered from the group of devices to identify possible neighboring devices within the network. The configuration information is then processed to generate topology information that identifies true neighboring devices and the actual links that exist between each of the neighboring devices. The approaches eliminate misleading information and prevent generation of incorrect topologies.

Abstract: A method for providing the automatic upgrade of microcode on a computer system connected to a remote system comprises executing a software tool on the computer system to determine the level of the current microcode on the system. The information on the current microcode level and associated system configuration information is sent automatically to the remote system where the microcode level and configuration information are checked against a database. On a determination that the current microcode level is not the latest level, the user of the computer system is notified that a more recent level is available and in response to a request by the user, the more recent microcode level is downloaded from the remote system. The user can then upgrade the microcode in the system.

Abstract: A device control unit 12, in response to a user's instruction to register, registers a network device ID and setting information designated by the user into a device setting information table 31 and an alteration history table 32; reads, in response to the user's alteration instruction, setting information corresponding to the ID designated by the user out of the alteration history table 32; displays it on an input/output unit 2 to let the user alter it; updates the device setting information table 31; adds the alteration to the alteration history table 32; reads, in response to the user's instruction to have it reflected, setting information corresponding to the ID designated by the user out of the device setting information table 31; displays it on the input/output unit 2 to let the user confirm its contents; and transmits the confirmed setting information to the network device to have it reflected therein.

Abstract: A method of displaying capacity information relating to computer resources over a preselected period of time. The computer resource is connected to a communications network and the method includes collecting data relating to capacity of the resource by periodically sampling preselected resource elements at a preselected fixed interval to define a capacity variable for that resource. The periodic sampling takes place from a location on the network that is remote from the computer resource and over a period of time for the resource element. The capacity variable of the resource element is compared with capacity variable(s) collected immediately prior to said capacity variable. The capacity variable is stored, together with an associated timestamp, if said capacity variable falls outside a preselected margin of the average of the prior capacity variables.

Abstract: A content provider manager has been develop for use in an information services such as a portal or desktop application to provide for “pluggable” content that may be modified simply through changes to the set of content provider components encoded in a repository therefor. Content providers served to clients (e.g., browsers) by an information service are dynamically loaded and instantiated within the execution environment of the information service in correspondence with changes in the repository. In some configurations, a single repository provides a mechanism for additions to, removals from and/or changes in the set of content providing components served by multiple information service installations. Although the techniques described are more generally applicable, they are particularly useful in implementations of dynamic content applications, including user customizable web portal and personalized desktop, e.g.

Abstract: A distributed system for the management of distributed resources interconnected by a computer network and comprised of a plurality of limited supply resources (such as those associated with multimedia content servers, e.g., bandwidth, CPU, storage, etc.,). The system comprises a plurality of server resources, preferably with target multimedia content, real time processing engines, etc., and a plurality of intermediary system resources (such as directories and resource monitors). The resources in any particular server are classified or partitioned as global or local, where the ratio of global to local is specified and controlled by the system. The system assigns clients across local and global resources and coordinates the placement of replicas of target content across global resources. The placement is dynamic and performed when necessary based on the analysis of utilization patterns of target content and replicas by pluralities of clients.

Abstract: The invention provides a method and system for correct interoperation of multiple diverse file server or file locking protocols, using a uniform multi-protocol lock management system. A file server determines, before allowing any client device to access data or to obtain a lock, whether that would be inconsistent with existing locks, regardless of originating client device or originating protocol for those existing locks. A first protocol enforces mandatory file-open and file-locking together with an opportunistic file-locking technique, while a second protocol lacks file-open semantics and provides only for advisory byte-range and file locking. Enforcing file-locking protects file data against corruption by NFS client devices. A CIFS client device, upon opening a file, can obtain an “oplock” (an opportunistic lock).

Abstract: A system and method for dynamically switching between different physical layer devices (PHYs) in a network interface. The system comprises a network interface in a network device, e.g., a network card in a computer system which includes a first PHY device and a second PHY device. The first PHY device is coupled to a first transmission medium (such as fiber-optic cable) which requires a continuous connection to the computer system when active. For a SERDES device, this continuous connection is required because the PHY needs constant access to its physical coding sublayer (PCS), which is located external to the PHY. The second PHY device is coupled to a second transmission medium (such as copper cable) which does not require this continuous connection. This second PHY may be, for example, a G/MII device, which includes the PCS internally. The network interface card further includes a link switching unit, a physical layer interface unit, and a control unit.

Abstract: The present invention is a system and method for performing interactive EDI transactions across an Internet/Web based communications platform. The Web-based system and method of the present invention facilitates the communication of data between organizations that use EDI standards. A script for processing EDI data associated with a transaction is executed at a server to process EDI transaction data from another computer. A script execution component processes the EDI transaction data according to instructions provided in the script. The component that executes the script is located in accordance with a uniform resource locator.

Abstract: In a CORBA distributed object system, potential object name ambiguities in the Portable Object Adapter are resolved without using variable-length object identifiers by translating the variable length identifiers into a fixed length compact identifier, such as a integer. The mapping for persistent objects is maintained on an ID server with persistent state and the mappings are ultimately written to a file. A server IDL interface is defined to the ID server which interface includes a method that accepts a variable length fully qualified name and returns the compact identifier. The method assigns an identifier if one does not exist. Another method accepts the identifier and returns the name.

Abstract: A “generic” switch messaging protocol is disclosed for message handling and switch supervision in conjunction with a number of switching engines, each of which is conversant with the generic messaging protocol, each switching engine also being conversant with a specific switch messaging protocol. An object oriented development system is also disclosed utilizing a “generic” switch messaging protocol and a plurality of switching engines, each of which is conversant with the generic messaging protocol and each of which is conversant with a specific switch messaging protocol. Certain switch messages are not “genericized” because their functionality is different from the functionality of other switches. These messages generally include initialization and maintenance messages which are hardware specific and have no counterpart in another switch from a different vendor.

Abstract: According to the present invention, a media manager is provided which incorporates an application program interface (API) for converting high-level generic commands into device-level commands for output to a media device. The inventive media manager includes a high-level command processor which decodes the high-level generic commands and device-specific code mapping modules which convert the high-level generic commands decoded by the high-level command processor into device-level commands. Each of the device-level commands is output from one of the device-specific code-mapping modules to a corresponding one of the media devices. The present invention also encompasses a method of implementing an application program interface (API) for media devices. The method includes receiving high-level generic commands from a computer application, converting the high-level generic commands into device-level commands, and outputting each of the device-level commands to one of the media devices.

Abstract: The present invention describes an improved communication architecture for smart card systems and an improved procedure for communication of the smart card applications using protected data carriers, particularly in the case where smart cards or smart card readers cannot be used. The improved communication architecture has a common virtual smart card interface between the respective smart card applications and the modules which facilitate access to the protected data carriers (smart cards). The modules allow access to either physical smart cards, virtual software smart cards or hardware smart cards. The common virtual smart card interface means that the application is completely independent of the respective module or the respective data carrier. Alternatively, the improved communication architecture additionally contains a virtual smart card adapter which communicates over the common virtual smart card interface with the respective smart card application.

Abstract: A novel method and apparatus for managing communication transactions between electronic appliances is presented. The invention includes a source input/output (I/O) communications function which establishes a first communication link between the apparatus and a source appliance, and a destination I/O communications function which establishes a second communication link between said apparatus and a destination appliance. The apparatus stores and executes a communications program in program memory which manages communications transactions between the source I/O communications function and destination communications function.

Abstract: An information processing apparatus having a device which processes data at a rate exactly adjusted relative to the rate of a data supplying device without requiring a common clock signal. A writing unit writes data into a buffer memory. When a first half of the buffer memory has become filled with data, a starter makes a reading unit start reading data from the buffer memory. A writing time measurement unit and a reading time measurement unit respectively measure the writing time required to write data in the buffer memory and the reading time required to read data from the buffer memory starting from the first storage location to the exact middle storage location of the buffer memory. A controller controls the rate at which data is read from the buffer memory based on the relationship between the writing time and the reading time.

Abstract: A need to store data between a producing stage and a consuming stage commonly arises in digital processing applications. However, factors such as fabrication process limitations and circuit area constraints may restrict the amount of available storage. A novel method and apparatus for data buffering are disclosed which use less data storage than would be required by double buffering techniques.

Abstract: A method of and apparatus for capturing and processing Continuous media-based data streams transmitted over an IEEE 1394 serial bus manages the use of both receive buffers and process buffers in order to minimize the amount of captured data that is discarded due to unavailable process buffers. When receiving a stream of continuous data. the data is captured and stored within a current receive buffer. When the current receive buffer is full. the captured data within the receive buffer is then read out, processed and stored within a process buffer, if a process buffer is available on a cached list of process buffers. When Full of processed data, the process buffer is then transferred to an application for utilization or further processing of the processed data. If the process buffer is not completely filled, then the process buffer is added back to the cached list of process buffers.

Abstract: A processor-based system provides communication among multiple computer devices operating at different frequencies utilizing clock synchronization. Phase relationship is maintained between clock signals running a different frequencies such that a read cycle of a device operated at the faster frequency is initiated when the clock signals are in phase. A write cycle of the faster frequency device is initiated when the clock signals are out of phase. A synchronization signal is generated by sampling the clock signals together to indicate the phase relationship. In addition, a return clock, derived from the faster clock, drives external devices. Information sent from internal devices to external devices are passed through a register driven by the return clock. Timing delays for information presented to the external devices is avoided as the register transmits all information according to the return clock. Return data is clocked into a return register also according to the return clock.

Abstract: Systems, data paths and methods of transferring data. By utilizing the systems, data paths, and methods, data can be transferred at a single or double rate. One embodiment of the present invention provides a system having a data unit, an output register, and a holding register. The output register is coupled to the data unit. The holding register is coupled to the data unit and the output register. Data from the data unit is passed to the output register and the holding register substantially simultaneously and data from the holding register is then passed to the output register. Data can be output from the output register.

Abstract: In a method for time coordination of the transmission of cyclic data values on a bus to which data transmitters and data receivers are connected, each data transmitter is assigned a cycle time in which it periodically transmits its data values, wherein the cycle times are integer multiples of a minimum cycle time. Furthermore, each data value is assigned a delay time related to the start of the cycle time of its data transmitter. A synchronization message is transmitted via the bus to each data transmitter with a period corresponding to the cycle time of the respective data transmitter and has a phase which is specific for the data transmitter with respect to the start of the minimum cycle time. The reception of its synchronization message in each data transmitter initiates the transmission of its data values with the respective delay time.

Abstract: Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter, a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topography dependent parameter for later use by the parameter adjustment circuitry. The parameter adjustment circuitry adjusts a parameter control signal in accordance with the topography dependent parameter, which is coupled to the output driver. Prior to driving an output signal onto a bus, the output driver adjusts the transmit signal characteristic in accordance with the parameter control signal. In a bus receiver, a receive signal characteristic is adjusted in response to a topography dependent parameter. A port associated with the bus receiver receives the topography dependent parameter and stores it in a register.

Abstract: A host adapter integrated circuit that contains data transfer modules has a serial port that uses a single serial port pin to communicate with a slave serial port input-output integrated circuit that interfaces to various resources that are included in a support circuit. The serial port forms a packet from each byte of information to be transferred from a module to the slave device by adding a start bit before the byte, followed by a parity bit at the end of the byte and followed by a stop bit. After transmitting the packet, the serial port waits for an acknowledge packet from the slave serial port input-output integrated circuit, for example for two clock cycles after transmission of the packet. For synchronous operation, a common oscillator drives the clock signal on the slave serial port input-output integrated circuit and host adapter integrated circuit.

Abstract: A method, system and computer program product are provided for detecting the presence of devices, particularly hot plug devices, connected to a bus both during start-up of a computer system and while the system is running. At start-up, and periodically thereafter, all possible device connections are polled by microprocessors, called sub-bus controllers, which include logic for generating a map of components present on each bus. Each map is accessible by the master bus controller. During system run-time, periodic polling, may be continuous thereby providing a real time device status map for every available bus connection.

Abstract: In response to a need to initiate one or more global operations, a bus master within a multiprocessor system issues a combined token and operation request in a single bus transaction on a bus coupled to the bus master. The combined token and operation request solicits a single existing token required to complete the global operations within the multiprocessor system and identifies the first of the global operations to be processed with the token, if granted. Once a bus master is granted the token, no other bus master will be granted the token until the current token owner explicitly requests release. The current token owner repeats the combined token and operation request for each global operation which needs to be initiated and, on the last global operation, issues a combined request with an explicit release. Acknowledgement of the combined request with release implies release of the token for use by other bus masters.

Abstract: A mixed rotative and weighted arbiter for arbitrating the priority of request signals R1-Rn supplied from a plurality of devices is disclosed. The arbiter is composed of a token circuit which delivers a token vector having one position set active. The token vector as well as the plurality of request signals are input to a rotative arbitration circuit. The rotative arbitration circuit processes a round robin algorithm to output a rotative request vector having input requests ordered from a higher to a lower priority configuration according to the active position of the token vector. The arbiter further comprises a weighted arbitration circuit connected to the output of the rotative arbitration circuit for generating a weighted request vector determining a linear priority configuration of the rotative request vector.

Abstract: A system for coupling data between a host computer and a bank of disk drives. The system includes a plurality of directors for controlling the flow of the data between host computer and the bank of disk drives. Each one of the directors has a primary port and a secondary port. The system includes a first I/O section coupled to a first one of a pair of disk drive sections in the bank of disk drives and a second I/O section coupled to a second one of the pair of disk drive sections in the bank of disk drives.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data between a host computer bus and a packet switched network. The network interface device includes a read controller and read offset register that stores read pointer information. The host CPU programs the read offset register to any particular value so that the read controller will read data from a desired starting point. In this manner, the host CPU is able to skip parts of a frame stored in the random access memory.

Abstract: A distributed shared memory multiprocessor computer system is provided, which has a number of processors and is divided into partitions. Each partition has within it one or more of the processors, and may also have memory or cache and other related hardware. Although each partition works together and communicates with other partitions to share computational load, the partitions each are independently operable and execute an independent copy of the operating system. The partitions comprise additional features to enable removal of a partition from the operating computer system, and to enable insertion of hardware into the operating computer system.

Abstract: A common motherboard interface accommodates processor modules of different processor architectures. The system comprises an interface for communicating with a processor module inserted at the motherboard. The interface receives an identifier signal from the processor module. The identifier signal identifies the processor module architecture. An architecture selection circuit selectively exchanges processor architecture specific signals with the processor module based on the identifier signal. In this manner, a multiple of processor modules of completely different processor architectures can share a common motherboard, thereby providing a system that can be field-upgraded by processor modules of different architectures, or simply allowing the same motherboard to be employed in two different products of different processor architectures.

Abstract: A method for docking/undocking a portable computer to/from an expansion unit is disclosed. The portable computer includes a main battery, and the expansion unit includes a second battery. In response to an eject event, the condition of the second battery is determined. If the second battery is in a discharging condition, a power supply route is switched from the second battery of the expansion unit to the main battery of the portable computer. If the second battery is in a charging condition, the charging condition is suspended. At this point, a hot undocking of the portable computer from the expansion unit can be performed.

Abstract: A configuration access request packet is transmitted from a first hub agent onto a hub interface. The configuration access request packet comprises an address formatted in accordance with a peripheral component interconnect (PCI) specification. The configuration access request packet is received from the hub interface by a second hub agent.

Abstract: A method and apparatus for using an interface and concomitant communication protocol to allow a host to control and communicate with a video decoder. More specifically, an interface structure having a status interface line and at least two data interface lines are employed between a video decoder and a host. The interface allows a communication protocol to effect communication and control of timing information, data transmission, and input and output selection.

Abstract: In an electronic system, an arithmetic device is provided between successive bus terminals or between successive modules, respectively, with an identification signal applied to a bus input that is routed from one bus terminal to the next bus terminal until the identification signal has passed through all bus terminals in order to identify the modules. The identification signal is subjected to an arithmetic operation and consequently changed in each arithmetic device before it is forwarded to the next bus terminal, wherein the “results of the operations” are used for identifying the individual bus terminals and the individual modules, respectively.

Abstract: The present invention provides a microprocessor capable of improving the throughput of a CPU. Module like the program ROMs in which instruction accesses are concentrated by a CPU are put together in a first Princeton bus, and modules like the external bus I/F, SDRAM I/F, peripheral bus I/F in which data accesses are mainly concentrated are put together in a second Princeton bus. Therefore, the instruction access and the data access can be carried out in parallel with respect to the buses of the instruction bus and the data bus individually through a bus control unit. Because the buses can be used efficiently, the throughput of the CPU can be improved substantially.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based ache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Since the achievement of coherency is distributed in time and space, the node controller helps to eliminate certain types of snoop collisions by pacing commands selected from its queues in certain circumstances.

Abstract: A computer-implemented method and system for accelerating writes to a storage controller by performing log-based sequential write caching of data to be written on a storage device. The data in the log is moved to the storage array later when the system is less active. As a result, random writes are converted to sequential writes. Overall, performance improves since the performance of sequential writes far exceeds that of random writes. A write command containing data is received in a data storage controller, wherein the data storage controller includes a write cache having a sequential log. The data storage controller also includes an index structure indicating the location of data in the sequential log. If the data does not already exist on the log, the data is written to the log contained in the write cache at a location recorded in the index structure.

Abstract: Included in the system are a memory module, a controller, and a voltage regulator. The memory module stores data indicating a level of voltage needed for operation. The controller obtains the data from the memory module and outputs a signal, based on the data, indicating the level of voltage needed by the memory module. The voltage regulator receives the signal from the controller, and supplies the level of voltage to the memory module in accordance with the signal.

Abstract: A memory device including a balanced switching circuit and methods for controlling an array of transfer gates. The balanced switching circuit comprises a plurality of transfer gates. The plurality of transfer gates are arranged in N rows and N columns with the N transfer gates in each row connected in series between a first signal terminal and a second signal terminal. Each one of N clock terminals is coupled to a respective control terminal of only one transfer gate in each row and only one transfer gate in each column. The transfer gates are selectively clocked or activated in response to clock signals to couple the first signal terminal to the second signal terminal such that the switching speed is independent of the order in which the individual series connected pass transistors or transfer gates are activated.

Abstract: Techniques for the efficient location of free entries for use in performing insert operations in a binary or ternary content addressable memory. As used in data communications and packet routing, such memories often rely on an organization that maintains entries of the same “length” within defined regions. The present invention keeps the free entries (holes) compacted into a contiguous subregion within each region, without requiring hole movement during deletes. These positive effects are accomplished by initially pre-filling the entire memory with a set of hole codes that each uniquely identify the holes in each region. A conventional memory write is then performed to load routing data into the memory. Typically, such routing information will not fill the entire memory, leaving unused entries (containing the region appropriate hole code) in each region. As entries need to be deleted, they are simply replaced by writing in the region-unique hole code.

Abstract: A first plurality of registers are daisy chained together with each register associated with a particular cache line. Similarly, a second plurality of registers are daisy chained together with each register associated with a cache line. The first daisy chain defines a fill order of cache lines and the second daisy chain defines a lock order for the cache lines.

Abstract: A data sharing method and system between information processing systems which enable an information processing system to share data in an internal disk unit possessed by another information processing system. A disk control unit within the other information processing system having an external disk unit or an external disk unit includes a disk data sharing mechanism for creating a read/write request to the internal or external disk unit from a command equivalent to a read/write request to a data in a conventional disk subsystem. This mechanism emulates a CCW command to access data in the disk unit.

Abstract: A method for indexing a cache includes searching on a cache index using a partial physical address, the partial physical address including any bits of the virtual address which are untranslated between the virtual address and the physical address. The partial physical address is used to identify a block of the cache index sets that might contain an address of requested data. The identification is performed prior to translation of the virtual address to the physical address. Once identified, the block is read out into an auxiliary memory structure. After the full physical address becomes available, the block is multiplexed down to one set, and a compare is performed on the ways of the set to determine if the requested data is in the cache and, if so, which way the data is in. A device for achieving the method includes a cache index organized into two arrays, each having a number of sets and a number of ways. One of the arrays may used to store micro-tags for way prediction.

Abstract: A set-associative cache having a selectively configurable split/unified mode. The cache may comprise a memory and control logic. The memory may be configured for storing data buffered by the cache. The control logic may be configured for controlling the writing and reading of data to and from the memory. The control logic may organise the memory as a plurality of storage sets, each set being mapped to a respective plurality of external addresses such that data from any of said respective external addresses maps to that set. The control logic may comprise allocation logic for associating a plurality of ways uniquely with each set, the plurality of ways representing respective plural locations for storing data mapped to that set. In the unified mode, the control logic may assign a first plurality of ways to each set to define a single cache region.

Abstract: In a cache which writes new data over less recently used data, methods and apparatus which dispense with the convention of marking new cache data as most recently used. Instead, non-referenced data is marked as less recently used when it is written into a cache, and referenced data is marked as more recently used when it is written into a cache. Referenced data may correspond to fetch data, and non-referenced data may correspond to prefetch data. Upon fetch of a data value from the cache, its use status may be updated to more recently used. The methods and apparatus have the affect of preserving (n−1)/n of a cache's entries for the storage of fetch data, while limiting the storage of prefetch data to 1/n of a cache's entries. Pollution which results from unneeded prefetch data is therefore limited to 1/n of the cache.

Abstract: A pre-fetch prediction table is provided for storing history of readout access given from a host device. A controller in a disk control device registers entry information including a set of an area address a indicating the access destination of the previous access and concerned prediction address b, having an area address b indicating the access destination of the readout access given from the host device as prediction address b, into a corresponding entry of the pre-fetch prediction table. Thereafter, when a readout access designating the area address a in agreement with the area address a in the concerned entry information is given from the host device, the controller pre-fetches from a HDD to a disk cache according to the prediction address b in the concerned entry information.

Abstract: The invention is directed to techniques for accessing data within a data storage system having a circuit board that includes both a front-end circuit for interfacing with a host and a back-end circuit for interfacing with a storage device. To move data between the host and the storage device, an exchange of data between the front-end circuit and the back-end circuit can occur within the circuit board thus circumventing the cache of the data storage system. Such operation not only reduces traffic through the cache, but also shortens the data transfer latency. In one arrangement, a data storage system includes a cache, a first front-end circuit that operates as an interface between the cache and a first host, a second front-end circuit that operates as an interface between the cache and a second host, a first storage device (e.g., a disk drive, tape drive, CDROM drive, etc.

Abstract: In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation.

Abstract: An address and data transfer circuit includes enable circuit for enabling a single-port memory in accordance with an access requirement from a corresponding port out of a plurality of external ports. An active address selecting circuit selects an address from the corresponding port and transfers the address to the single port memory responsive to activation of the enabling circuit. An active data selecting circuit selects a data from the corresponding port and transfers the data to or from the single port memory, responsive to activation of the enabling circuit.