Abstract: A method for resolving address contention and prioritization of access to resources within a shared memory system includes dynamically creating ordered lists of requests for each contested resource. A new request is added to the lists only after a conflict is recognized. Since the resource conflict does not always exist, there is no impact to a request for an uncontested resources.

Abstract: This invention is a data storage system that includes logic configured for carrying out a method to allow a so-called “re-labeling” of a logical volume. Re-labeling changes the label configuration originally put in place by the host at a first device and replicated to a second device. The re-labeling takes place during a certain operation that takes the second device offline to a host computer in communication with the data storage system. This re-labeling avoids labeling conflicts that could arise when duplicate labels result on two different devices as a result of the replication.

Abstract: A system and method for controlling access to privilege partitioned address space for a model specific register file. A superscalar microprocessor includes a plurality of model specific registers (MSRs). MSRs differ between various implementations of a microprocessor architecture. The MSRs are allocated to access regions within a MSR file. Each access region of the MSR file is assigned access attributes. The MSRs are allocated such that the access region and the access attributes of the MSRs are defined by the address of the MSRs. Access to the MSRs is controlled by comparing the address of the MSR to the current privilege level of the microprocessor. In one embodiment, a validity check circuit is used to control access to the MSRs. If an access is attempted to an MSR that cannot be accessed at the current microprocessor privilege level, access to the register is denied and an exception is generated. In one embodiment, an address checker may be used to verify whether an MSR address is within a valid range.

Abstract: A method and system for extending tTR range of memory devices coupled to a memory devices is described. A first group of memory devices and a second group of memory devices are identified. The first group includes memory devices located close to a memory controller and the second group includes memory devices located a distance away from the memory controller. Commands to access memory devices in the first and second groups are sent. A command to the first group is sent with a transitional delay when the command to the first group follows a command to the second group. In response to the commands, data from the first and second groups is received.

Abstract: A method of operating a data processing system having a main memory divided into memory pages that are swapped into and out of main memory when the main memory becomes short. The data processing system has an operating system that sends page store commands specifying memory pages to be stored in a swap file and page retrieve commands specifying memory pages to be retrieved from the swap file and stored in the main memory. The present invention provides a swap driver that utilizes compression code for converting one of the memory pages that is to be swapped out of main memory to a compressed memory page. The data processing memory includes a compressed page region that is used to store the compressed memory pages. A page table in the compressed page region specifies the location of each compressed page and the page address corresponding to that page.

Abstract: A data processing system and a method for accessing data therein. The data processing system includes a microprocessor, an application specific integrated circuit (ASIC), and a memory. The ASIC is coupled between the microprocessor and the memory and is utilized to communicate with an external computer system for downloading a program code from the external computer system to the memory in which the program code is stored in a memory region of the memory through the ASIC. In addition, the ASIC is for mapping the memory region onto an external memory address space of the microprocessor. The microprocessor generates an address latch enable (ALEN) signal, program memory enable (PMEN) signal, read enable (RDEN) signal, write enable (WREN) signal, and a first address signal.

Abstract: The reliability and operability of semiconductor devices is improved using a circuit arrangement and method that improves the ability to manage data storage and retrieval. According to one example embodiment of the present invention, a memory device includes a dynamically configurable page table having a plurality of pages. The page table is dynamically configurable to at least two organizations, and each page includes a multitude of memory storage locations adapted to store data. A controller is adapted to track memory requests and to configure the page table to one of the at least two organizations during a memory refresh cycle, wherein the configuration is effected in response to the tracked memory requests. In this manner, the page table can be adapted to improve the effectiveness and speed of data storage and retrieval.

Abstract: When reading or writing data from or to a flash memory, a table indicating the correspondence between physical addresses of physical blocks composing together a storage area of the flash memory and logical addresses of logical blocks written in the physical blocks, is generated in segments of the flash memory.

Abstract: The present invention provides, at a lower cost, a highly reliable data reading method and data reading apparatus that can improve backward sequential reading performance. The disk drive is provided with a magnetic disk and a control section having an HDC, a RAM, an MPU controlling the operation of the entire HDD, including control of the HDC, a ROM, and an I/F for connecting to an external host device. The control section executes a backward reading detection step that detects backward reading, a step of receiving a command that reads a block of a first length from a first LBA, a step that reads a block of the first length from the first LBA when backward reading is detected, and a step that pre-fetches a second block from a second LBA smaller than the first LBA; when backward reading is detected, upon completion of the reading of data from the disk, the reading of data predicted to be requested by the next command begins immediately.

Abstract: An initial value of read address is set in a first initial address register; an initial value of write address is set in a second initial address register; and the number of data to be accumulated by an accumulator and the frequency of repetition of accumulation are set in an accumulator count register. A controller controls the timing of output of an initial read address from a first memory controller, the timing of initialization by an initializer, and the timing of output of an initial write address from a second memory controller. Reading of data, accumulation and writing of data proceed in parallel in each cycle of accumulation.

Abstract: A hardware arrangement for implementing synchronization control between multiple processors is disclosed. The hardware arrangement is provided with a plurality of communication registers which are arranged so as to store synchronization control data applied from the processors. A flag bit register generates a plurality of flag bits which are respectively assigned to a plurality of critical sections. Each of the flag bits indicates whether or not the corresponding critical section is available. In order to assure the mutual exclusion control, a flag bit access control register is provided which generates a plurality of control bits that are respectively assigned to the plurality of flag bits. The control bit is used to prevent two processors from using an identical critical section. A controller is provided so as to adequately control the above-mentioned registers.

Abstract: A processor having a hashed and partitioned register file includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of registers coupled to the execution unit. The plurality of registers are partitioned into a plurality of groups, such that registers within each group can store only data having associated addresses within a respective one of a plurality of subsets of an address space.

Abstract: The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract: To an existing instruction set, newly added are a condition code conversion instruction for converting a first condition code (N, Z, OV, C) to a second condition code (V, S) based on a reference condition code COND, a second conditional instruction having a reference flag SF, and an instruction of operation between two selected second condition codes. A VLIW processor comprises a second condition code register file 163, a condition code conversion circuit 12A, and a logic operation circuit 12E for performing a non-Boolean logic operation between two selected second condition codes.

Abstract: A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Instructions may be executed during delay slots after program branching while an execution pipeline is being restarted. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A software breakpoint instruction is provided for debugging purposes. In order to correctly emulate the operation of the instruction pipeline when a software breakpoint instruction is executed during a delay slot, the width (1110-1115) of the software breakpoint is the same as the replaced instruction. A limited number of breakpoint instruction length formats (1100, 1102) are combined with non-operational instructions (NOP, NOP—16) to form a large number of combination instructions that match any instruction length format.

Abstract: A processor includes at least one functional unit configured to execute an instruction. The processor also includes an instruction window configured to supply the instruction to the functional unit. The processor further includes a register file configured such that data and a result of execution of the instruction are temporarily stored in the register file. The processor still further includes a branch prediction circuit having a branch execution unit and a branch prediction table. The processor also includes a data value prediction circuit configured to predict a first operand value which will be used by the functional unit and a second operand value which will be used by the branch execution unit to predict a direction of a branch and to store the direction of the branch in the branch prediction table. With such a processor, a branch prediction is made by executing a branch instruction rather than by referring to the history of the branch instruction.

Abstract: A system for execution of code during power-on-self test (POST), the system including a mass storage device for storing computer programs; a microprocessor connected to the mass storage device, the microprocessor including an execution unit; a general purpose register connected to the execution unit, the general purpose register for storing a first data element; an MMX unit including a plurality of MMX registers, the MMX unit connected to the general purpose register, wherein the plurality of MMX registers are configurable as a virtual stack; a storage device connected to the microprocessor, the storage device for storing BIOS instructions; and a plurality of BIOS instructions stored on the storage device, the plurality of BIOS instructions readable by the microprocessor to thereby cause the microprocessor to execute a virtual stack push instruction wherein the first data element is moved from the general purpose register to a first of the plurality of MMX registers; and execute a virtual stack pop instructio

Abstract: A method and apparatus is provided for effecting secure document delivery in any of various document formats. A document is encrypted with the public key of a server associated with the recipient of the document, instead of with the public key of the intended recipient. The receiving server is located within a firewall. The encrypted document is forwarded to the server within the firewall. The server decrypts the document using its corresponding private key, converts the document to a now data representation, and then either forwards the document to the recipient inside the firewall, or re-encrypts the document with the public key of an intended recipient outside of the firewall or with the public key of another server that is associated with the intended recipient of the document.

Abstract: A cable television system provides conditional access to services. The cable television system includes a headend from which service “instances”, or programs, are broadcast and a plurality of set top units for receiving the instances and selectively decrypting the instances for display to system subscribers. The service instances are encrypted using public and/or private keys provided by service providers or central authorization agents. Keys used by the set tops for selective decryption may also be public or private in nature, and such keys may be reassigned at different times to provide a cable television system in which piracy concerns are minimized.

Abstract: An apparatus and method for user authentication for easily realizing the allocation of a complexity of rights when controlling access by a plurality of users to a plurality of objects. A verification apparatus sends to a proving apparatus required security information that shows the authority property required for access to an object, along with a challenge data and a modulo of a public key. A required security information inspection unit within the proving apparatus obtains the required security information stored in a response data memory and a control information representing a user's authority property stored in a control information memory. It then inspects whether an identifier of:the required security information is included in a list included in the control information. If the identifier is included, a response data is generated, upon! condition that all of challenge data, required security information, access ticket, control information and user identifying information are correct.

Abstract: A method and apparatus of protecting communications in a receiver having a first and a second module includes issuing a request to a transmitter. The identities of the first and second modules are verified based on information in the request. The transmitter transmits a predetermined message to the receiver after verification. The first and second devices are authenticated based on the predetermined message.

Abstract: A device and method for safely maintaining a secret code within an integrated circuit (IC) package. The complete secret code is divided into two parts. The first part of the secret code is stored in a non-volatile memory device, such as flash memories, and provided by an internal random number generator. The second part of the secret code is stored in a volatile memory device, such as registers, and provided by external visa data issued from an authority center. Such a configuration can guarantee that no one can ferret out the complete secret code by opening the sealed IC package. Accordingly, the secret code can be safely and confidentially maintained within the IC package.

Abstract: A system and method is disclosed for controlling access to computer resources using an untrusted network. The system preferably uses a hardware key connected to each subscriber client computer and adds software to the subscriber client computer and to the existing server computer. A clearinghouse is provided to store client and server identification data, including demographic data, including URL data, usage data and billing information. The clearinghouse authenticates the subscriber and server computers before an operating session occurs. For every new client session, a login mechanism requires the client computer to supply appropriate identification data, including a digital identification generated by the hardware key. The login parameters are verified by the clearinghouse and a session is then started. The system is adapted to protect preselected content from being printed or copied by a client using a web browser.

Abstract: A system and method of automatically configuring virtual private networks is provided. The virtual private networks disclosed, include multiple routers selectively connectable to the shared network, such that each of the routers is assigned at least one: shared network address, private network address and virtual private network identifier. Each router includes a controller configured to communicate a router configuration message over the shared network to other members of the same virtual private network. The router configuration message informs the other members of the virtual private network the address of the router and what devices are connected to the router.

Abstract: A portable computer system with universal serial bus (USB) port or ports and a method for controlling power of the universal serial bus (USB) port is described. When the main power of the portable computer system is supplied from a battery rather than an alternating current (AC) adapter, the power of the universal serial bus (USB) port is automatically shut down. In addition, the power of the universal serial bus (USB ) port is completely shut down while the universal serial bus (USB) port is not used in response to a setting state of the universal serial bus (USB) port, thereby reducing unnecessary power consumption. Further, when an over-current is detected from the alternating current (AC) adapter or the battery, the power of the universal serial bus (USB) port is shut down, whereby damage to peripheral devices coupled to the universal serial bus (USB) port can be prevented.

Abstract: A method of simple network synchronization in a bus extension system with expanded capabilities wherein a plurality of independently-operable multimedia multiplexing devices are connected to the same network in parallel. The method of network synchronization for multiplexing devices connected by parallel through an extension bus is provided wherein one of two or more multiplexing devices is used as a clock master and other remaining multiplexing devices as slave devices and wherein the multiplexing device acting as the clock master is operated in synchronization with a clock received from a network while the multiplexing devices acting as the slave devices receive a clock from a clock transmission line of the extension bus which is outputted after the clock master has established synchronization with the network clock and regenerate a clock leading the received clock in phase.

Abstract: A data synchronizer transfers information across an asynchronous interface by using system domain and core domain logic on either side of the asynchronous interface. Information registers receive data beats from a data bus coupled to an external system. Each data beat is loaded into the registers in sequential order. A corresponding system valid bit is provided for each register and is set when the corresponding register is loaded. In the core domain, a corresponding set of core valid bit registers is set in response to the system valid bit registers being set. A data sampler monitors the core valid bits in sequential order and controls a multiplexor to select a corresponding one of the registers that contains valid data. The data sampler resets the core valid bits which in-turn reset the system valid bits to signal the completion of a data transfer across the asynchronous interface.

Abstract: Provided is a method and components of an apparatus for implementing a method for assisting with adjustment of the timing of user-inactivity-dependent changes of operational state of an apparatus, by identifying user interactions following a change of operational state, determining when the user's interactions or lack of interaction following the change of state suggest that a change to an inactivity time period is desirable, and either automatically changing the inactivity time period or prompting the user to change the time period.

Abstract: A system and method for providing redundant, synchronized clocks in a computer system. Upon a failure of a master clock signal, the system switches over to a slave clock signal synchronized with the master clock signal. Switching logic is coupled to receive a first clock signal and a second clock signal. The switching logic selects either the first clock signal or the second clock signal as a local clock signal. The switching logic further monitors the first clock signal for a failure. If a failure is monitored, the switching logic accepts the second clock signal as the local clock signal in place of the first clock signal. One or more clock local loads operate according to the local clock signal. The switching logic may control the input to a phase locked loop (PLL) that provides the local clock signal to the local clock loads. The method includes a PLL synchronizing an output clock signal with the master clock signal. The output clock signal is used by at least one local clock load for timing.

Abstract: A method and system are disclosed for maintaining a central queue for sequentially processing data within a distributed processing system. The method and system transports data to a first central queue from one or more remote processing locations for subsequent processing. Each processing location maintains in memory data transported to the first central queue as well as information relating to the data transported. Upon the processing location associated with the first central queue experiencing a failure, a second central queue is created from the data maintained in the memory of each remote processing location. The information relating to the data transported to the first central queue is utilized so that the contents of the second central queue substantially match the contents of the first central queue prior to the failure. In this way, a redundant or backup central queue can be formed without the expense of maintaining dual central queues during normal operation of the distributed processing system.

Abstract: When communication networks are damaged or communication is restricted due to the occurrence of a disaster, etc., information required for disaster relief is rapidly and effectively obtained. The system has a plurality of server apparatus 2, a plurality of portable terminal equipment 1, and communication networks 20, 30 of different types to which both the portable terminal equipment 1 and the server apparatus 2 can be connected. The portable terminal equipment 1 accesses an available server apparatus 2 over an available communication network and obtains disaster relief information and resource information corresponding to damaged resources to thereby create or update a disaster relief plan file 5 and a resource information file 6. The server apparatus 2, in response to an inquiry from the portable terminal equipment 1, extracts the necessary information from the disaster relief information DB 3 and the resource information DB 4 and transmits the same to the portable terminal equipment 1.

Abstract: A method of managing data in a hierarchical data storage system employing data redundancy schemes includes prioritizing a data rebuild based on a most vulnerable data redundancy scheme in the storage system. A data storage system embodying this rebuild prioritization method is also described. Prioritizing the data rebuild includes enabling a rebuild of the most vulnerable data redundancy scheme prior to enabling a rebuild of any other data redundancy scheme in the system. The most vulnerable data redundancy scheme is determined by comparing a probability of losing data that can be prevented by a rebuild for each data redundancy scheme with respect to the potential for one or more next storage device failures in the data storage system.

Abstract: A disc storage system having a host computer interface adapted to coupled to a host computer, a disc storage medium having a disc surface and a spindle motor coupled to the disc adapted to rotate the disc. The disc includes spare data regions and permanent data regions. A transducer is positioned for reading and writing data on the disc surface. The system further includes a controller adapted to write data on the spare data regions to thereby provide a non-volatile write cache.

Abstract: The invention is utilized in the context of a peripheral device that is coupled to a network via a firewall which blocks unwanted incoming message traffic, except for incoming message traffic that is responding to a message dispatched from the peripheral device. A remotely located diagnostic device, which includes code for diagnosis of causes of peripheral device malfunctions, is connected to communicate via the network. The peripheral device includes a memory for storing a diagnostic application that is adapted to execute one or more diagnostic subroutines for diagnosing a cause of a device malfunction. The peripheral device is enabled to dispatch an event message to the remote diagnostic device and to receive a response message from the remote diagnostic device (all via the firewall and the network). The response message causes a diagnostic application to execute a subroutine on the peripheral device in an attempt to determine the cause of the event.

Abstract: An on-chip debug system includes a data band selector operable to transmit to an emulator the selected data bands generated by the selected components in an integrated circuit. The data band selector is directed by the emulator based upon instructions received from a host computer.

Abstract: A method and apparatus in a multiprocessor data processing system for managing a plurality of processors. Monitoring for recoverable errors in a set of processors is performed. Responsive to detecting a recoverable error for a processor in the set of processors, a determination is made as to whether the recoverable error indicates a trend towards an unrecoverable error. Responsive to a determination that the recoverable error indicates a trend towards an unrecoverable error, actions are initiated to stop the processor.

Abstract: A semiconductor device having multiple memory circuits and one or more logic sections includes a single test circuit for testing all of the memory circuits. The test circuit includes a test section that controls the memory circuits, for example, by initiating a read operation, with a control signal. Comparison/determination circuits, which correspond to the memory circuits, compare the data read from the memory circuits with expected value data, and generate determination signals. Since the various memory circuits are different distances (wire lengths) from the test section, a control section is provided which adds a delay to the control signal provided to the various memory circuits so that the memory circuits all receive the control signal at about the same time and perform their respective read operations at the same time.

Abstract: A semiconductor device comprising a memory circuit, a switch for relieving the memory circuit of its failures, and a logic circuit to be tested, facilitates a test of the logic circuit. When a switch control signal (SET) is “1”, for example, a switch (200) selects predetermined 1-bit data (=c) from a plurality of 1-bit data (=b) outputted in parallel form from a RAM (100) and outputs it to a logic circuit (300), where c<b.

Abstract: Disclosed is an alternating current (AC) scan diagnostic system in which one or a plurality of scan chains are tested by serially propagating predetermined bit patterns through the scan chain and comparing the output against an expected result. The system comprises identification phase, verifications and localization, and a characterization phases. The system is adaptable for use with on-board diagnostics and is adaptable for use with on-product clock generation systems.

Abstract: A method for finding the root causes of the failure of a faulty chip. The faulty chip comprises at least one defect. First, a type-searching step for the defect according to a defect size and a defect type to respectively predict a failure type of a predicted failure region relative to the defect is performed. Then, an influenced-range-searching step for the defect according to a defect location to respectively predict a failure range of a predicted failure region relative to the defect is performed. Finally, the predicted failure region of the defect and a real failure region which was electronically failed and been identified by the faulty chip are compared. If the predicted failure generated from the defect is located in the real failure region, the defect is interpreted to be one of the root causes of the failure of the faulty chip.

Abstract: The invention relates to an application-specific integrated circuit (ASIC) (1) for use in communication facilities of a digital network in which a data signal to be transmitted is composed of frames. To improve such an integrated circuit (1) in such a manner that external testing devices for testing the performance of the integrated circuit (1) can be dispensed with, the invention proposes to provide the integrated circuit (1) with a circuit (4) for executing the ASIC functions and with a data test circuit (3) having first means (5) for generating a framed test signal (6) and second means (7) for detecting bit errors in a received test signal (8).

Abstract: In a code transmission scheme for a communication system using error correcting codes, the transmitting side generates at least one transmitting side syndrome value by carrying out a syndrome calculation for the information to be transmitted, and transmits to a receiving side at least one information packet containing the information to be transmitted and at least one redundant packet containing the transmitting side syndrome value. Then, upon receiving at least a part of the information packet and the redundant packet, the receiving side obtains at least one receiving side syndrome value by carrying out a syndrome calculation for an information contained in the information packet as received, and performs error correction, if required, by calculating a difference between the transmitting side syndrome value contained in the received redundant packet.

Abstract: Error control coding is applied to data streams transmitted through transmission equipment such as a telecommunications switch having a distributed synchronous switch fabric. Each k-symbol dataword is encoded to generate an n-symbol codeword that is then sliced for transmission through the transmission equipment. After routing, error-correction decoding is applied to the resulting routed n-symbol codeword to detect and correct one or more errors in the codeword to generate a k-symbol routed dataword that is identical to the original incoming dataword. Depending on the coding scheme, different types and numbers of errors can be corrected in each codeword. For example, for Reed-Solomon [12, 8, 5] coding with Galois field (24), corrections can be made for up to four erasures with no random errors, up to two erasures and one; random error, or up to two random errors with no erasures.

Abstract: A turbo decoder control comprises an address generator for addressing systematic data, parity data, and systematic likelihood ratios according to a pre-determined memory mapping. The systematic data samples are accessed in the order required by the MAP decoding algorithm such that interleaving and de-interleaving functions in the MAP decoding algorithm are performed in real-time, i.e., without delay. Such memory-mapping in combination with data handling functions (e.g., multiplexing and combinatorial logic) minimizes memory requirements for the turbo decoder and allows for use of programmable interleavers, variable block lengths, and multiple code rates.

Abstract: The present invention provides a method for custom coding uplink signals and downlink beams in a satellite communications system. The method includes the step of applying, at a ground station (100), an outer code (102) to an uplink signal to produce an outer coded uplink signal. Next, the ground station (100) applies a selected reduced complexity inner code (104) to the outer coded uplink signal to produce a concatenated coded uplink signal. The ground station (100) transmits the concatenated coded uplink signal to a satellite (110). At the satellite (110), the inner code of the concatenated coded uplink signal is decoded (116) to produce an outer coded satellite data stream. Next, the satellite (110) applies a selected inner code (120) to a portion of the outer coded satellite data stream to produce a concatenated coded satellite data stream. The satellite (110) then transmits the concatenated coded satellite data stream in a downlink beam to a destination ground station (126).

Abstract: An error control apparatus includes: a deinterleaver for deinterleaving data of a predetermined number of bits coded by predetermined cyclic codes, which is to be interleaved in accordance with a predetermined interleaving order; a first cyclic code checking circuit for receiving an output of the deinterleaver and making a cyclic code check on the data of the predetermined number of bits by a check system corresponding to a coding system of the cyclic code; and a second cyclic code checking circuit for receiving an output of the deinterleaver and making a cyclic code check on the data of the predetermined number of bits by a check system corresponding to the coding system of the cyclic code simultaneously with the cyclic code check by the first cyclic code checking circuit in substantially the same time while canceling an interleave effect by the deinterleaver.

Abstract: A method for controlling the saving of information regarding printer operating conditions to its nonvolatile memory is provided. The method decreases the data save time to the printer's nonvolatile memory, and minimizes the effect that saving to the nonvolatile memory has on printer operation. The method groups printer status data relating to the printer's operating conditions into different groups or blocks of data and allocates each block to a different storage area in the printer's volatile memory and its nonvolatile memory. A particular data group stored in its assigned storage area in the volatile memory is saved to the corresponding storage area in the nonvolatile memory when one or more trigger events related to printer control to which that particular data group is responsive occur.

Abstract: A subframe data transmission device for a mobile communication system. A bit generator generates specific bits having a predetermined value. A bit inserter segments a received data bit stream into at least two subframes, and inserts the generated specific bits at locations where an error probability is higher in the respective subframes. A turbo coder codes the subframe data comprised of the data bit stream and the specific bits. The subframe is equal in size to an ARQ (Automatic Repeat Request) block, and the specific bits are inserted at a rear portion of the subframe. The bit inserter includes a delay for delaying the received data bit stream by the number of the specific bits to be inserted; and a selector for connecting, upon completion of receiving data bits for the subframe, the received data bits to the delay and applying an output of the bit generator to the turbo coder; and applying, when the specific bits are inserted, an output of the delay to the turbo coder.

Abstract: A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems. Each end of a channel is connected to a Channel Interface Block (CIB). The CIB presents a logical interface to the Channel, providing a communication path to and from a CIB in another IC. CIB logic presents a similar interface between the CIB and the core-logic and between the CIB and the Channel transceivers. A channel transport protocol is is implemented in the CIB to reliably transfer data from one chip to another in the face of errors and limited buffering.