Abstract: In a disk storage system for digital computers (e.g., optical or magnetic disk drives) a sampled amplitude read channel is disclosed comprising a convolutional code channel encoder for encoding check bits into channel data recorded to a disk storage medium, a trellis sequence detector for detecting a preliminary sequence from read signal sample values generated during read back, a convolutional code syndrome generator for generating an error syndrome from the preliminary sequence, and a post processor for evaluating the error syndrome to detect and correct errors made by the trellis sequence detector. The post processor remodulates the preliminary sequence output by the trellis sequence detector into a sequence of estimated sample values which are subtracted from the actual read signal sample values to form a sequence of sample errors.

Abstract: A turbo-code decoder includes a first reception signal memory, second reception signal memory, a priori memory, first adder, first selector, and second selector. The first reception signal memory stores an information sequence. The second reception signal memory stores first and second parity sequences. The a priori memory stores extrinsic/previous information in repetitive processing. The first adder adds the information sequence read out from the first reception signal memory and the previous information read out from the a priori memory. The first selector selects one of the first and second parity sequences read out from the second reception signal memory. On the basis of a polarity of a calculation result from the first adder and that of a selection output from the first selector, the second selector selects one of the sum from the first adder including a negative polarity, the selection output from the first selector including a negative polarity, a sum of the sum and selection result, and zero.

Abstract: A method is provided in a digital receiver interfacing with a point-of-deployment (POD) module and receiving a first data stream having a first predetermined pattern. The method for detecting failure of the POD module includes the steps of: receiving the first data stream; forwarding the first data stream to the POD module; receiving a second data stream having a second predetermined pattern from the POD module; monitoring validity of the first and second data streams; and if the first data stream is valid and the second data stream is invalid, providing a failure alert on the POD module.

Abstract: A CAD system includes a storage device for storing information for the types and positions of cell blocks to be disposed in an internal circuit area, prohibition of arrangement of power source lines and electrode pads, and a plurality of layout parts each including an electrode pad and a connection cell. Each of the layout parts is selected based on the distance between the electrode pad and an associated I/O cell, thereby obviating the step of wiring between the electrode pad and the I/O cell.

Abstract: An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide singular ideal IC package routing solution. Topological Global Routing provides a mathematical abstraction of the problem that allows multiple optimizations to be performed prior to detailed routing. Preliminary disregard of electrical routing segment width and required clearance allows the global topological solution to be determined quickly. The global topological solution is used in conjunction with necessary design parameters to determine the optimal geometric routing solution. Guide points are determined using the geometric routing solution. A detail router uses the guide points as corners when performing the actual routing.

Abstract: The present invention relates to a device for passively aligning at least one substrate-carried optical fiber with at least one optical device. The substrate is patterned with a buried etching stop layer. The substrate is then etched to provide a pattern of U-grooves whose depths correspond to the thickness of material that overlies the etching stop layer and whose positions on the substrate are aligned relative to the optical device. The optic fiber is disposed and fixed in the U-groove. The invention also relates to a device produced by means of said method.

Abstract: The present invention teaches a method for designing an integrated circuit. The design of the integrated circuit is replicated a number of times. The number of times must be odd. The input signals to the original module are also replicated. The replicated modules are configured to respectively receive the replicated input signals. A number of exclusive or gates is provided. The exclusive or gates receive the output signals from the replicated modules. The output signals from the replicated modules are compared to the output signals from the original module. The method is applicable to a bi-directional integrated circuit. Embodiments include the software to replicate the design. Another embodiment includes a computer system for replicating the design. Also, integrated circuits designed by the method described are included within the scope of the disclosure. Another embodiment includes designs produced by the method.

Abstract: A variable design tool utilizes memory units to determine at which point a design rule fails. The variable design tool can provide a bit map indicating the points of failures for particular rules. The bit map can also be utilized to determine misalignment errors. The memory cells, typically SRAM units are arranged in 4×4 matrices which are arranged in four 16×16 matrices.

Abstract: A computer process used to create a report to check a proposed project to insure conformity with existing standards. The software used utilizes a diagrammatic design program which allows creation of a model while checking compliance with the standard used in the proposed project. In the preferred embodiment example given, the method would first create a new project or open an existing project. Thereafter, the user would select a list of modules from rules algorithms for standards relating to the created or opened existing project. Next, the project would be designed by adding component parts and modifying their properties while maintaining compliance with the selected standards. Finally, a report, whether checklists, graphical layouts with dimensions or worksheets that enable the user to create a dimensioned graphical layout, would be created to demonstrate compliance with the selected standard.

Abstract: Disclosed is an apparatus for comparing CAD (computer aided design) design data comprising one or more components with a set of design rules generated relative said components and generating an output report of detected discrepancies. The output may include data (annotations) used to generate a visually high-lighted (red-lined) display whereby the CAD generated design errors may be easily ascertained. The apparatus includes the capability of transmitting the CAD data, converted to a standardized XML format, from a remote CAD design site to a difference engine site having the latest set of rules relative said components. The difference engine site may then return the results to the remote CAD design site for use by the device design operator. The results returned may be visually displayed in red-lined format as well as in an itemized list.

Abstract: A design-timing-determination process for an electronic design automation system approximates the timing of a whole design quickly and on-the-fly. Such allows a scheduling system to construct operation schedules that are ultimately realizable. A timing analysis is applied each time an individual operation is scheduled, and may be called many times to get a single operation scheduled. A graph representing combinational logic is partitioned into a collection of logic trees with nodes that represent gates and terminals, and arcs that represent connections. A compacted model of each logic tree is constructed by replacing them with equivalent trees having no interior nodes. The timing of the original circuit is analyzed along each path from the leaves to the roots. A propagation delay for each path is determined, and such is annotated onto each corresponding arc of the simplified tree.

Abstract: A method of accurately estimating a time delay caused by a target cell where a target supply voltage is applied to the cell. Time delays, caused by a representative cell, are represented as a function of supply voltages applied to the cell, thereby deriving an approximation function k1. An interpolation function k2 is derived from the approximation function k1 by reference to two points P1 and P2. P1 indicates a time delay T1 caused by the target cell where a supply voltage V1 is applied thereto, while P2 indicates a time delay T2 caused by the target cell where a different supply voltage V2 is applied thereto. Thus, the interpolation function k2 represents the time delays caused by the target cell as a function of supply voltages. And by using this interpolation function k2, a time delay caused by the target cell at the target supply voltage can be estimated accurately.

Abstract: Some embodiments of the invention are placers that use diagonal lines in calculating the cost of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations. For instance, some placers use diagonal lines as cut lines that divide the IC layout into regions.

Abstract: A method and apparatus for selectively viewing nets within a database editor tool. The present invention provides four primary features for selectively viewing nets. First, the present invention contemplates selecting a number of objects, and viewing only those nets that are either driven from or received by the selected objects. In a preferred embodiment, the number of objects are placed objects within a placement tool. Second, for those nets that are selected, and that are also coupled to un-placed cells, the present invention contemplate providing fly-wires from the corresponding selected objects to a predetermined location representative of an approximate expected location for the un-placed cells. Third, the present invention contemplate providing a vector filter which may permit only vectored nets with a selected bus width range to be viewed.

Abstract: A data processing system for designing a customized master slice data includes the steps of consecutively locating a cell base block based on the design data, a plurality of dummy gate blocks, and a possible number of intermediate blocks in the area of the semiconductor chip; replacing dummy gate blocks by gate array blocks while shifting the gate array blocks by half length; and locating intermediate blocks in an area generated by shifting the gate array blocks. The space between the gate array block and the cell base block is filled with the intermediate blocks for preventing interference therebetween.

Abstract: A layout structure and a method for generating a layout for an integrated circuit more efficiently to catch up with remarkable developments of fabrication technologies of today. In generating a layout for a CMOS circuit, a pair of p- and n-channel transistors is used as a layout unit if one of these transistors is the dual of the other. These two transistors of are placed closely to each other so that when wires are connected to the source or drain of the p-channel transistor and to the source or drain of the n-channel transistor, those wires can be extended substantially vertically to each other.

Abstract: Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.

Abstract: Methods, systems and articles of manufacture comprising a computer usable medium having computer readable program code means therein are provided for debugging multiple related processes simultaneously and more particularly provided for debugging multiple related processes simultaneously from one instance of a debugger. Being able to debug processes simultaneously in one instance of a debugger gives the user more control in recreating the specific ordering of events that generate a failure in processing. Further, being able to debug processes simultaneously from the same instance of a debugger provides usability gains and convenience by, for example, allowing the user to view information flowing between processes and the states of the processes.

Abstract: A source code translating method includes the steps of representing a particular source code in the form of an abstract syntax tree without using nodes representing expression statements, and converting such abstract syntax tree into a character string, wherein as the type of the root node in the abstract syntax tree being processed is if-statement (T71), a branch is taken to invoke the “procedure for producing if-statement” where a character string “if (” is first produced, and then, to produce “x==0” contained in the first occurrence of the subtree, the “procedure for outputting the abstract syntax tree as an expression” is recursively invoked, then a character string “)” is produced; to produce “y=0;” contained in the second occurrence of the subtree, the “procedure for outputting the abstract syntax tree as a statement” is recursively invoked, then a character string “else” is produced; and

Abstract: Compiler optimization methods and systems for preventing delays associated with a speculative load operation on a data when the data is not in the data cache of a processor. A compiler optimizer analyzes various criteria to determine whether a cache miss savings transformation is useful. Depending on the results of the analysis, the load operation and/or the successor operations to the load operation are transferred into a predicated mode of operation to enhance overall system efficiency and execution speed.

Abstract: A method, implemented by a compiler, for removing a store-load dependency from a critical path utilizes a compare address operation to determine at run time whether dependency actual exists. The operand to be stored is held in a temporary register and provided directly to the operations, using load operation result, in dependence on the value of the compare address operation result, so that the dependency is removed.

Abstract: A system for testing audiovisual stimuli, such as television series, commercials, etc. from a complex of interactions between stimuli, consumers and environmental factors includes: one or more sources of audiovisual stimuli; a part connected to the sources for presenting the stimuli to respondents; a switching part to be operated by the respondents for issuing commands such as a command to end the presentation of a stimulus; a part for registering the moments at which the switching parts are operated; a generator for generating further stimuli, such as textual information including questions, messages, commands and instructions; a part to be operated by the respondents for providing responses to the further stimuli such as providing answers to questions and providing reasons, such as reasons for ending the presentation of stimuli; and a part for registering the responses provided by the respondents.

Abstract: A digital video receiver, a conditional access module and method of transmitting data therebetween, the digital video receiver having a multi line socket for connection to the conditional access module, the socket having a pre-determined plurality of lines for transmitting and receiving transport stream data and a pre-determined plurality of lines for transmitting and receiving control data and resource/application data, the method comprising selectively transmitting resource/application data over the plurality of transport stream lines.

Abstract: An improved method and apparatus for portable digital entertainment system which melds direct microwave communications with digital technology to provide a system for “on demand” distribution of digital data, such as songs or video games. The apparatus includes a microwave cellular tower capable of transmitting and receiving a plurality of digital transmissions, a storage unit of user selectable songs and games coupled to the microwave cellular tower through a selection processor for managing the exchange of song and game selections between the storage unit and the microwave cellular tower, and a plurality of user portable digital cellular devices exchanging digitally encoded transmissions with the microwave cellular tower in response to a user's song or game selection request. The portable digital cellular devices include a liquid crystal display window which allows a user to select a desired song to be heard or game to be played.

Abstract: An entertainment system has a personal computer as the heart of the system with a large screen VGA quality monitor as the display of choice. The system has digital satellite broadcast reception, decompression and display capability with multiple radio frequency remote control devices which transmit self identifying signals and have power adjustment capabilities. These capabilities are used to provide context sensitive groups of keys which may be defined to affect only selected applications running in a windowing environment. In addition, the remote control devices combine television and VCR controls with standard personal computer keyboard controls. A keyboard remote also integrates a touchpad which is food contamination resistant and may also be used for user verification. Included in the system is the ability to recognize verbal communications in video signals and maintain a database of such text which is searchable to help identify desired programming in real time.

Abstract: A cash transaction machine having an antitheft mechanism capable of preventing the cash from being seized from a cash storage unit inside a housing through an opening formed in the housing is disclosed. The cash transaction machine having the antitheft mechanism according to the invention includes the housing having a hard outer wall with an opening, and a cash dispensing/receiving unit extending out of the housing through the opening from inside of the housing. At least the portion of the cash dispensing/receiving unit arranged outside of the housing is configured with a metal bottom plate, a transverse structure extending substantially parallel to the plane of the bottom plate, and a pair of metal side plates with the bottom ends thereof fixed to the bottom plate, and the ends of the transverse structure are secured to the side plates at a position above the bottom ends of the side plates.