Abstract: A specific address region of a cache address region is set in a non-cache region setting register together with a region setting valid bit in a cache memory. When the specific address region is accessed by a CPU core, access to an external memory is made if a corresponding region is set in a non-cache region by a region setting valid bit. Moreover, an invalidating bit is set to invalidate all cache memory data in the specific address region. In DMA transfer, an inclusion detection circuit detects whether a transfer destination address region is included in the set address region and forcibly sets an invalidating bit according to a result of the detection. A cache system is provided that is capable of setting an address region of a cache object region according to a system architecture with flexibility.

Abstract: The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position within the network. Embodiments according to the present invention can provide a relatively high performance storage access environment for the mobile users moving around a wide area. For example, in one applicable environment, there are several data centers in the wide area, and each data center has a local storage system that is connected to the other storage systems through a network. Copies of a user's volume can be made in some of the storage systems. A remote copy function is utilized for making real time copies of the user's volume.

Abstract: In a computer system with caching, memory transactions can retrieve and store groups of lines. Coherency states are maintained for groups of lines, and for individual lines. A single coherency transaction, and a single address transaction, can then result in the transfer of multiple lines of data, reducing overall latency. Even though lines may be transferred as a group, the lines can subsequently be treated separately. This avoids many of the problems caused by long lines, such as increased cache-to-cache copy activity.

Abstract: The present invention provides the ability to transfer data between a initiating computer system and a target computer system with a block data storage device, where the target computer system is remote relative to the initiating computer system, that is interface independent relative to the type of the block data storage device employed. In one embodiment, a virtual device driver is employed that implements a command set that is interface independent relative to the block data storage device.

Abstract: The present invention relates to a data processing system comprising a processor (100), at least one data memory (132), at least one program memory (134) and a main bus (110), common to the data and program memories and connecting these memories to the processor, characterized in that at least one of the memories has a rapid-access mode and in that the device also comprises a distribution interface (120) between the main bus (110) and the memories in order to alternately put in communication, by means of the main bus, one from among the data memory and the program memory with the processor, in a so-called active-access mode, and to keep the other memory in a so-called passive-access mode allowing subsequent rapid access.

Abstract: A memory apparatus having a volatile memory for storing data from a host, a nonvolatile memory capable of storing the data stored in the volatile memory, and electrically deleting the data, and a control circuit for controlling data transfer between the volatile memory and the nonvolatile memory. A capacity of a data storage area of the volatile memory is larger than that of a data storage area of the nonvolatile memory.

Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.

Abstract: The present invention provides a priority encoder comprising a first, second and third resolving-encoding circuit, each of which has a plurality of input terminals receiving a plurality of requests, determines one of the input terminals receiving one of the requests as a prior terminal, and outputs a forward request and an address of the prior terminal, wherein the forward requests of the first and second resolving-encoding circuit are received as the requests of the third resolving-encoding circuit, and a multiplexer receiving the addresses output from the first and second resolving-encoding circuit, and selectively outputting one of the received addresses according to the prior terminal determined by the third resolving-encoding circuit.

Abstract: Described is a system and method for allowing applications to interact with a common backup program in a uniform way. The system and method provides a communication mechanism for one or more applications to exchange information with the backup program regarding components of the applications. The information exchanged may include an identification of the components of each application. A component may be considered a group of files or resources that should be backed up or restored together. In this way, when a backup operation is initiated, each application may provide to the common backup program instructions describing the specific components to be backed up. In addition, each application may add other application-specific information useful during a restore of the backed up data.

Abstract: This invention relates to a copying method, disk storage system and storage medium for copying data from one logical disk to another logical disk, and makes immediate access in response to a copy command possible. Copying from logical disk 1 to logical disk 2 is performed for each area in the copy range, and when there is access, copying is interrupted. When performing update access of an uncopied area in the copy source 1, the area is copied from the copy source 1 to the copy destination, and then the area is updated. When performing reference access of an uncopied area in the copy destination 2, the corresponding area in the copy source 1 is referenced. When performing update access of an uncopied area in the copy destination 2, that area in the copy destination is updated, and copying is prohibited. In this way, it is possible to access the copy source 1 and copy destination 2 while copying is in progress, and it is possible to immediately regard that copying is completed by a copy instruction.

Abstract: A log of transactions is maintained on a persistent storage device. When a block of storage is allocated or deallocated, this transaction is recorded. If the persistent storage device is allowed to be slightly obsolete (i.e., not fully up-to-date), the log stored on the persistent storage device does not necessarily have to be updated right away. By delaying log updating until a certain number of transactions have transpired, memory seeks can be reduced, significantly improving performance. Further, directory information on the persistent storage device may be periodically updated from the log. This is preferably done infrequently enough so that the amortized cost for updating directory information is low.

Abstract: Methods and/or systems and/or apparatus for improved memory management include different allocation and deallocation strategies for various sizes of objects needing memory allocation during runtime.

Abstract: A method for managing computer memory, in accordance with the present invention, includes maintaining multiple sets of free blocks of memory wherein a free block is added to a set based on its size. In response to a request for a block of a request size, a set of blocks is searched for a free block which is at least as large as the request size but smaller than the request size plus a threshold. If such a block is found, the block is allocated in its entirety.

Abstract: Techniques for implementation of Java heaps are disclosed. The techniques can be implemented in a Java virtual machine operating in a Java computing environment. A Java heap potion comprising two or more designated portions is disclosed. Each of the designated heap portions can be designated to store only a particular Java logical component (e.g., Java objects, Java class representation, native components, etc.) A designated heap portion can be implemented as a memory pool. In other words, two or more designated heap portions can collectively represent a memory pool designated for a particular Java logical component. The memory pools allow for dynamic management of the designated heap portions. As a result, the performance of the virtual machines, especially those operating with relatively limited resources is improved.

Abstract: The invention concerns a method and an embedded microchip system (8) for the secure execution of an instruction sequence of a computer application in the form of typed objects or data, particularly written in “Java” language. The memory (1) is organized into a first series of elementary stacks (2, 3) for storing instructions. Each typed object or datum is associated with one or more so-called typing bits specifying the type. These bits are stored in a second series of elementary stacks (4, 5) that correspond one-to-one with with the stacks (2, 3) of the first series. Before executing predetermined types of instructions, a continuous verification is performed, prior to the execution of these instructions, of the matching between a type indicated by the latter and an expected type, indicated by the typing bits. If they do not match, the execution is stopped.

Abstract: A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.

Abstract: A memory to support a first address protocol in response to a first control signal and a second address protocol in response to a second control signal.

Abstract: M memory cells (MC) in each of which a ferroelectric capacitor (FC) and a selector transistor (CTR) are connected in series are connected in parallel between a drive line (DL) and a bit line (BL). One end of the bit line (BL) is connected to a gate electrode of a read transistor (STR). Thus, the number of memory cells connected to the bit line (BL) can be reduced so that wiring capacitance of the bit line (BL) can be lowered, without incurring any increases in area and cost, as in the case where a sense amplifier is used. As a result, a voltage induced to the bit line (BL) can be regarded as not depending on remanent polarization of the ferroelectric capacitor (FC). Accordingly, the area of the ferroelectric capacitor (FC) can be reduced, allowing high integration to be implemented.

Abstract: A computer system includes memory and at least a first processor that includes a memory management unit. The memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses. The translation table entries provide first and second memory address translations for a processor address. The memory management unit can enable either the first translation or the second translation to be used in response to a processor address to enable data to be written simultaneously to different memories or parts of a memory. A first translation addresses could be for a first memory and a second translation addresses could be for a second backup memory. The backup memory could then be used in the event of a fault.

Abstract: Caches are associated with processors, such multiple caches may be associated with multiple processors. This association may be different for different main memory address ranges. The techniques of the invention are flexible, as a system designer can choose how the caches are associated with processors and main memory banks, and the association between caches, processors, and main memory banks may be changed while the multiprocessor system is operating. Cache coherence may or may not be maintained. An effective address in an illustrative embodiment comprises an interest group and an associated address. The interest group is an index into a cache vector table and an entry into the cache vector table and the associated address is used to select one of the caches. This selection can be pseudo-random. Alternatively, in some applications, the cache vector table may be eliminated, with the interest group directly encoding the subset of caches to use.

Abstract: A circuit for recording digital waveform data includes (a) a first counter which counts the number of data constituting a first data sequence including a plurality of data different from one another, (b) a second counter which counts the number by which the same data is repeated to constitute a second data sequence, (c) a memory which stores all of data constituting the first data sequence and one of data constituting the second data sequence in this order together with the number counted by the first counter and the number counted by the second counter, and (d) a controller which transmits an address signal to said memory, and controls operation of the first and second counters.

Abstract: In a memory access process, by identifying the types of memories that can be activated without reducing operating speed and by reducing power consumption, a data processor capable of operating at a high memory-accessing speed is provided. Because memory types can often be differentiated based only on partial bits of the address obtained by addition, a partial bit adder and decision logic are used to make this differentiation at high speed. Because the partial addition preferably does not take into account the possible carry from the lower bits, two types of memories are chosen from memories and are both operated in case the carry should be “1” and in case it should be “0.” The result is chosen by a multiplexor and is output. A determination of the entry address of the memory may be similarly carried out by dividing the memory into odd and even entry number banks and utilizing a partial bit adder.

Abstract: Aspects of a method and system for digital signal processing within an adaptive computing engine are described. These aspects include a mini-matrix, the mini-matrix comprising a set of composite blocks, each composite block capable of executing a predetermined set of instructions. A sequencer is included for controlling the set of composite blocks and directing instructions among the set of composite blocks based on a data-flow graph. Further, a data network is included and transmits data to and from the set of composite blocks and to the sequencer, while a status network routes status word data resulting from instruction execution in the set of composite blocks. With the present invention, an effective combination of hardware resources is provided in a manner that provides multi-bit digital signal processing capabilities for an embedded system environment, particularly in an implementation of an adaptive computing engine.

Abstract: An acceleration engine may include a set of accelerators and a set of resources coupled to the accelerators. The resources may interface the accelerators to an interconnect, and may provide a programming interface to the accelerators. Since the resources handle interfacing the accelerators to a given interconnect, the accelerators may be insulated from the details of a given system. If more than one accelerator is included in the acceleration engine, some of the resources may be shared by the accelerators. For example, if the resources include a memory for storing data accessed by an accelerator, the memory may be shared between by the accelerators. A methodology for creating an acceleration engine is also described.

Abstract: A method providing an application computer program to be written independently of the structure of a directory information tree. The application program makes calls to an innovative API, the API accessing the structure of the directory information tree in an innovative template. If the structure of the directory information tree is changed, the template is changed, but the application is not changed.

Abstract: A main controller stores levels and information to be stored in accordance with the levels. An operation screen is used to enter operation information for operating a complex machine 1. A scanner engine and a plotter engine execute operations based on the operation information. A memory records only information on operations in a level corresponding to the entered level information among the operations performed by the complex machine.

Abstract: A data processor is composed of a register file including a plurality of registers each of which stores therein an operand data, a register pointer section which includes a plurality of register pointers, an instruction register, a data type converter unit, and a processing unit. Each of the register pointers stores therein a register address and a data type of the operand data stored in the register specified by the register address. The instruction register fetches an instruction word including an operation code, and an operand field. The operand field is representative of a register pointer address used for addressing a selected one of the register pointers to thereby indirectly addressing a selected one of the registers. The data type converter unit executes a data conversion on the operand data stored in the selected one of the registers to produce a converted operand data, on the basis of the data type stored in the selected register pointer specified by the register pointer address.

Abstract: In a parallel processor system for executing a plurality of threads which are obtained by dividing a single program in parallel each other by a plurality of processors, when a processor executing a master thread conducts forking of a slave thread in other processor, at every write to a general register in the master thread after forking, the fork source processor transmits an updated register value to the fork destination processor through a communication bus. The fork destination processor executes the slave thread for speculation and upon detecting an offense against Read After Write (RAW) related to the general register, cancels the thread being executed to conduct re-execution of the thread.

Abstract: A programmable unit includes a command execution unit for carrying out commands, a memory device for storing data required for command execution and data emitted from the command execution unit, and a buffer-storage device for buffer storing the data emitted from the command execution unit. The command execution unit writes to the buffer-storage device data to be transferred to the memory device. The data written to the buffer storage device is transferred to the memory device at a later time. The programmable unit is distinguished by forming the buffer-storage device as a stack, and/or by providing a control apparatus that, when required, causes data stored in the buffer-storage device to be moved temporarily to another memory device. Such a programmable unit can carry out any buffer storage of events that may possibly be required quickly and easily in all circumstances.

Abstract: A method, program, and system for modifying computer program instructions during execution of those instructions are provided. The invention comprises writing a first instruction into a memory location, wherein the instruction is a patch class instruction. This first instruction is then fetched from the memory location and executed. Concurrent with execution of the first instruction, the memory location is overwritten with a second instruction, which is also a patch class instruction. Because the first and second instructions are patch class instructions, if a program is executing from the memory location, or returns to execute from that location, it will fetch and execute either the first instruction or the second instruction. In one embodiment, reconciling the processor's execution pipeline with the memory location will ensure that the second instruction is fetched and executed if the program returns to execute from that location.

Abstract: An Instruction Pointer (IP) signal is received comprising an IP tag field and an IP set field. A plurality of entries corresponding to the IP set field are read, each of the entries comprising an entry tag, an entry bank, and entry data. Each entry tag and entry bank is then compared with the IP tag and each of the plurality of banks. In one embodiment, the IP tag is concatenated with a number representing one of the plurality of banks and compared to the entry tag and entry bank. Separate comparisons may then be performed for each of the other banks.

Abstract: A method, apparatus, and computer program product for handling IEEE 754 standard exceptions for Single Instruction Multiple Data (SIMD) operations. Each SIMD sub-instruction's corresponding IEEE 754 exception flag is bit-wise “ORed” with an accrued exception field if a trap enable mask field is configured to mask the exception, with the “ORed” result written back in the accrued exception field. If the trap enable mask field is configured to enable the exception, the accrued exception field and a current exception field are cleared, and an unfinished floating-point exception flag is set in a floating-point trap type field. The actual sub-instruction(s) causing the exception is determined through software.

Abstract: A system for booting a microprocessor controlled system wherein a basic interface between the processor and peripheral devices is copied from an application and file storage device into random access memory without usage of the microprocessor or need for a non-volatile code storage device.

Abstract: A cryptographically signed filesystem provides a central database resident on a server that contains database objects. The server creates startup software to be installed in a client system's read only memory. The startup software contains a hash value for a second stage loader. The server also creates software for a bootstrap loader object which typically contains the operating system for a client system and also the bootstrap loader's hash value and a digital signature that is unique to the server. A root filesystem object is also created containing operational code and data for the client system's functionality. A hash table file is stored in the bootstrap loader that contains the names of each file in the root filesystem along with their corresponding hash values. The startup software and objects created by the server are initially installed on a client device at the time of manufacture.

Abstract: Apparati, methods, and computer readable media for authenticating an entity (9) in a shared hosting computer network (4) environment. A service provider computer (2) contains a plurality of entity sites (5). Connected to the service provider computer (2), a trusted third party computer (1) is adapted to provide a conglomerated authenticity certification to the service provider computer (2). Coupled to the trusted third party computer (1) is a means (10) for enabling an entity (9) to seek to convert the conglomerated authenticity certification into an individualized authenticity certification covering that entity's site (5).

Abstract: A system and method for three-party authentication and authorization. The system includes an authorizer that authorizes requestors, a client that makes a request, and a local attendant that provides a conduit through which messages between the client and the authorizer pass. The authorizer, the client, and a peer on which the requested resource may be accessed are each in separate domains. A domain is defined as a set of one or more entities such that if the set includes more than one entity, a connection between any two of the entities in the set can be secured by static credentials that are known by each of the two entities. A subscriber identity module (SIM) may be used to generate a copy of a key for the client to be used in accessing a requested resource.

Abstract: A universal browser operates in conjunction with an underlying browser to provide a user of a PC with access to an enhanced service. The enhanced service can be post-marking for an electronic communication, encryption, or some other service or product offered by the universal browser provider. The universal browser is displayed as a frame, on a tool-bar, on a pull-down menu, as an icon, or the like on a page that has been accessed by the underlying browser.

Abstract: Data stored on a computer readable medium in a computing system is protected from being read within another computing system by encrypting a data structure, such as the FAT table of a disk recorded using a FAT-based file system or a portion of the master file table of a disk recorded using an NTFS file system. This data structure is used to find the files on the medium. Encryption and decryption preferably occur within a cryptographic processor of the computing system, with this data structure in a hard drive being encrypted as the computing system is shut down and decrypted after power on. In an alternate embodiment, a utility program provides for selective encryption and decryption of a data structure in a removable computer readable medium.

Abstract: A portion of a firmware program may be automatically upgraded during power on of a processor-based system. A firmware upgrade file signed by a private key is authenticated using a public key accessible to the firmware program. The authentication and upgrade is performed automatically. Interrupted upgrades are anticipated and resolved by the firmware program. The public key is duplicated and is itself upgradable, in case the private key changes. The firmware program may be locked to prevent both viewing and unauthorized upgrades of the public keys or other parts of the firmware program.

Abstract: A method for enabling the recipient of electronic mail (e-mail) to authenticate the originator of the e-mail without opening the e-mail, so that e-mail that carries a computer virus which activates upon opening the e-mail may be rejected. The originator and the recipient agree beforehand on a privately held authentication code, which is carried in an open field of the e-mail, i.e., carried in a field that is visible to an agent of the recipient without opening the e-mail.

Abstract: A method of connecting an end user associated with a first organization to an application hosted by a second organization using a double blind authentication technique, wherein the identity of the end user is kept from the second organization and the identity of the second organization is hidden from the end user, includes exchanging digital certificates between the first organization and the second organizations, sending an authenticated and encrypted first message using a digital certificate from the first organization to the second organization, and requesting a virtual user (ID) for use by the end user. Thereafter, the method validates the digital certificate at the second organization, decrypts the first message sent by the first organization, and responds to the first message by sending an authenticated and encrypted response message including an authorized virtual user ID to the first organization.

Abstract: A method and device to prevent the creation of disparities in an interrogation-response system programmed in a first mode, the Mode 4 (M4) and interrogated in a second mode, a National Mode (NM), initially having a same message structure but a different enciphering key, the format of the message being constituted by a header followed by an information block separated by a time interval T. The method comprises at least one step in which the time interval T between the end of the header and the beginning of the information block is modified into a time interval Ti different from T.

Abstract: A method for creating a secure powerline modem network transmits a private key (y) individually to each of the plurality of powerline modem devices (22) to be secured in a network such that each powerline modem device receives the private key in isolation of the network. Each of the plurality of powerline modem devices store the private key. A public key (X) is computed by a master device (32) in the network to be secured. The public key is transmitted from the master device to the plurality of devices. A shared key (Y) is computed at each of the plurality of powerline devices based on the public key and the private key, and communication within the secured network is performed by employing messages encrypted based on the shared key.

Abstract: We disclose methods and apparatuses for securing cryptographic devices against attacks involving external monitoring and analysis. A “self-healing” property is introduced, enabling security to be continually re-established following partial compromises. In addition to producing useful cryptographic results, a typical leak-resistant cryptographic operation modifies or updates secret key material in a manner designed to render useless any information about the secrets that may have previously leaked from the system. Exemplary leak-proof and leak-resistant implementations are shown for symmetric authentication, certified Diffie-Hellman (when either one or both users have certificates), RSA, ElGamal public key decryption.

Abstract: A system and method generate a read only memory (ROM) image for a ROM. The ROM image generator operates with a data image builder. The ROM image generator processes an input file to identify data images for a build. The image identifier generates tokens for building each data image. A data image builder uses the tokens as an input to build each data image. A ROM image builder builds the ROM image using each data image build and generates a data image build validating signature for each data image build, such as a checksum. Once each data image build and associated validating signature is written to the ROM image, the ROM image is completed with a checksum of the entire ROM image.

Abstract: Methods, systems and computer program products provide for a middle-tier server to impersonate a client to a plurality of servers. A common nonce associated with each of the plurality of servers is obtained and the common nonce to the client. The common nonce signed by the client is received at the middle-tier server and provided as a signature for transactions from the client to the plurality of servers so as to authenticate the client to the plurality of servers.

Abstract: Two digital signatures are generated associated with an electronic document. One digital signature (“content signature”) maybe based on a user input contained in the document and another digital signature (“document signature”) may be based on a stream of data representing the document. The document is sent along with the two signatures to a receiver system. The receiver system can verify the integrity of the document (and thus the user input) based on one or both of the signatures. Optionally, multiple content signatures may be used with each content signature being generated based on a portion of a document. In addition, each document may contain a control section which includes rules specifying permitted/prohibited actions against each portion.

Abstract: In a method for real-time registration having high protection against tampering by means of a security module, an encrypted initial security value for translog file analyzers is made available an unencrypted real-time message is secured by appending an authentication code that the security module generates by inserting a current security value into an algorithm for authentication code for each real-time message that is likewise employed by each translog file analyzer. The first security value is formed according to a first mathematical function known to the translog file analyzer that allows a derivation of following security values. The authentication code is formed according to a second mathematical function known to the translog analyzer that is applied to the real-time message and to the current security value and that serves for the verification of the real-time message.

Abstract: The invention provides a data processing apparatus capable of efficiently executing the embedding process of digital watermark information into object data, and also capable of, in the process of embedding the digital watermark information into the object data, acquiring the digital watermark information matching the purpose of use or means of the object data.

Abstract: One embodiment of the present invention provides a system that facilitates receiving content from a primary peer and forwarding it to a secondary peer, wherein blocks of the content are sent to the secondary peer prior to all of the blocks of the content being received from the primary peer. The system starts by receiving an encrypted list of checksums from a server, wherein each checksum in the list is associated with a corresponding block of the content. Next, the system decrypts the encrypted list of checksums to form a list of decrypted checksums. The system then receives a block of the content from the primary peer and calculates a checksum for the block of the content. The system subsequently compares the calculated checksum with a corresponding checksum from the list of decrypted checksums received from the server. If the calculated checksum matches the corresponding checksum, the system sends the block of the content to the secondary peer.