Abstract: A plurality of virtual client processes for accessing a server are simultaneously operated on test execution terminal, when accessing the server by each virtual client process, respectively unique virtual network addresses are set, a source network address in a transmission packet is rewritten into the set virtual network address from an actual network address, a destination network address in a reception packet from the server is rewritten into the actual network address from the virtual network address, and this packet is transferred to the client with this virtual network address set therein. Load tests of accesses to the server from a multiplicity of client terminals can be executed by a small number of test terminals without depending on network protocols.

Abstract: A management data distribution apparatus has, a control unit, a buffer memory element, at least one input port, and a telecommunications output. The at least one input port is arranged to receive management data from devices located within a network and to pass the management data to the control unit. The control unit is arranged to control output of the management data via the telecommunications output to a remote monitoring site over a telecommunications network. The control unit is also arranged to store management data arriving at the at least one input port when the said telecommunications output is in use in the buffer memory element, temporarily.

Abstract: A method is described for the automated determination of fault events by evaluation of field data of a production installation within a system for determining the effectiveness (overall equipment effectiveness (OEE)) of the production installation and for the analysis of causes of faults. The determination of the fault events takes place using a data processing device and programs stored in it for carrying out the functions of a fault event detector and an OEE script configurer. The OEE script configurer accesses a prescribed productivity model specific to a production installation type, generates an OEE script with likewise prescribed configuration data taken into account and stores it in an OEE script memory. The fault event detector accesses the OEE script, calls up field data from a data server, derives fault events from the field data according to processing instructions of the OEE script, and stores them in a fault database.

Abstract: A method of centralised data position information and storage and utilisation comprising the steps of arranging a byte stream of data into partitioned logical data, storing data position information relating to the logical data in a reserve storage area, transferring the information from the reserve storage area to a centralised storage area configured to store information relating to substantially all the partitioned logical data and utilising the information to locate a target data using a search algorithm.

Abstract: A driver circuit for use on an integrated circuit tester. In one embodiment, the driver circuit has a timing circuit and a driver. The timing circuit has two or more inputs to receive data signals at a first frequency and at least one output. The timing circuit generates a control signal having a second higher frequency and outputs signals based on the data signals and the control signal such that the output signals are independent of the effects of timing skew and timing jitter of the data signals. The driver has at least one input coupled to the at least one output of the timing circuit to receive the output signals and couple the output signals to a device under test.

Abstract: A method and apparatus are provided for channel equalization with a digital finite impulse response (DFIR) filter using a pseudo random sequence. A readback signal of a pseudo random bit sequence is obtained. Samples are obtained from the readback signal of the pseudo random bit sequence. Tap gradients are calculated responsive to the obtained samples. The tap weights of the digital finite impulse response (FIR) filter are modified responsive to the calculated tap gradients. Dibit samples and error samples are obtained from the readback signal of the pseudo random bit sequence and applied to a tap gradients calculator. Tap gradients are calculated by a bitwise multiplier and accumulation tap gradient calculation circuit. An attenuation function attenuates the calculated tap gradients by a programmable attenuation value.

Abstract: A method and corresponding architecture are disclosed for sharing redundant rows between banks of a memory array. The architecture is such that sub-arrays associated with different banks are alternated and coupled via a sense amp. In addition, sub-arrays belonging to the same bank are coupled via a single row decoder. This architecture allows for adjacent sub-arrays belonging to different banks to share redundant rows, thereby effectively doubling the number of redundant rows available for use in a given bank.

Abstract: A semiconductor integrated circuit that can accurately measure margins for input-output characteristics in the case of transferring data at a high speed between semiconductor chips mounted in the same package. A semiconductor chip includes a first delay section selected to perform a hold margin test in the case of transferring data to a separate semiconductor chip for delaying a clock signal and a second delay section selected to perform a setup margin test in the case of transferring data to the separate semiconductor chip for delaying output data. Furthermore, the semiconductor chip includes a third delay section selected to perform a hold margin test on a second latch section in the case of data being input from the separate semiconductor chip for delaying a clock signal from a clock input section and a fourth delay section selected to perform a setup margin test on the second latch section in the case of data being input from the separate semiconductor chip for delaying input data.

Abstract: To propose an inspection apparatus capable of automatically inspecting a product, that is, an inspection apparatus capable of performing automatic measurement and automatic judgment An inspection apparatus consists of a recording medium (12), a personal computer (11), a digital signal processor (DSP) 10, and a display device (14). An inspection program is recorded in the recording medium (12). The inspection program recorded in the recording medium (12) runs in the personal computer (11). The digital signal processor (10) has its action controlled based on a command issued from the personal computer (11), feeds a predetermined inspection signal to predetermined points on an inspected product (2), and acquires a result-of-inspection signal. It is judged from the result-of-inspection signal whether the inspected product is acceptable. The result of judgment is displayed on the display device (14).

Abstract: A method for driving a retransmission timer in a mobile telecommunications system using a radio link protocol. A mobile telecommunications system receives a frame transmitted from a transmitter and, if the received frame is determined to be erroneous, requests the transmitter to retransmit the frame and drives a retransmission timer. In this case, there is a probability that the retransmission timer will be held. For this reason, the method for driving the retransmission timer minimizes that probability.

Abstract: System and method for accelerating the convergence rate of turbo decoding by verifying bits in data frames whose CRC shows no bit errors. Verified bits are translated to bound nodes on a trellis of nodes representing a sequence of bits of the encoded code block. Verification of all bits signals a stop condition and decoding iterations can be terminated. Further, state transition metrics are limited when a node is adjacent to a bound node, allowing for acceleration of convergence by elimination of impossible state transitions. Also disclosed is a scheme to detect bit errors when the code block contains unframed data or partial data frames. This bit error detection scheme uses a recursive encoder to establish end node status. The end node state determination accelerates convergence rate recognition when incorporated with other stop conditions.

Abstract: The invention relates to methods and devices for converting a stream of data bits of a binary information signal 2 into a stream of data bits of a constrained binary channel signal 3 using multiple channel codes Cst, Cpc. Apart from a standard code Cst, that is designed for a high coding rate, a parity-check enabling code Cpc is used that allows realization of a certain, predefined parity-check constraint imposed on the constrained binary channel signal 3. This parity-check constraint is related to a predetermined error event of the channel. The amount of use of the parity-check enabling code Cpc is dependent on the need for preventing the certain error event. Also another channel code Csub can be used in this method in order to realise DC-control.

Abstract: A system for transferring data from a host computing system 10 to a magnetic tape cartridge 12. Data from the host computing system 10 is buffered in a burst buffer 14 before transfer to a logical formatter 16, where data is compressed and converted to a format suitable for storage on the magnetic tape cartridge 12. The logical formatter 16 arranges the data into ‘datasets. The datasets are written sequentially into a main buffer 24 and, as each row of a dataset is written into the main buffer 24, parity bytes (Reed-Solomon) are added.

Abstract: A data transfer device adapted to transfer data from a data storage medium having at least one data storage element the data transfer device comprising a head block having first and second transfer elements.

Abstract: A decoding circuit used to correct an error in a digital signal comprises: an input unit for entering coded digital signals ID in parallel in accordance with the number of interleaved codes; a processor including an error locator polynomial calculator and an error value polynomial calculator for processing data obtained serially from the interleaved codes that are received by the input unit; and an output unit for correcting errors by employing the output data that are received from the processor and the digital signals ID, and for outputting in parallel the obtained digital signals OD, for which an error has been corrected by a linear calculation on a Galois field, in accordance with the number of interleaved codes.

Abstract: A memory configuration scheme that enables parallel decoding of a single block of turbo-encoded data is described. In this scheme a single code block is divided into multiple subblocks and decoding is performed on subblocks in parallel. The turbo decoder memory is configured so that subblock decoders can access the common memory resources independently of each other. This scheme is different from existing parallel decoding schemes in that it achieves the parallel implementation by applying multiple decoders to a single code block, not by assigning multiple decoders to multiple code blocks. The advantages of this scheme include minimum memory requirement and minimum decoding latency. The minimum memory requirement results from the fact that it needs memory resources only for a single code block regardless of the number of decoders used.

Abstract: An improved method and apparatus for performing single-cycle operations (such as Viterbi decode) in digital processors is disclosed. In one aspect, the invention comprises methods for storing (“packing”) old and new metric data in memory that cooperate with a single operand instruction adapted to perform single cycle calculations such as the Viterbi butterfly. Accordingly, such calculations can be computed effectively in software in a single cycle. In another aspect, an improved memory addressing mode is used to write back two new output results at the completion of instruction execution. The improved packing of state metrics in memory, single operand instruction, and addressing mode can advantageously be integrated into any processor (e.g., DSP, RISC-DSP, or configurable processor) with appropriate memory. The user of such a processor may accordingly write software using the single operand instruction to perform Viterbi decode with the efficiency comparable to a dedicated hardware implementation.

Abstract: A digital signal processor performs turbo and Virterbi channel decoding in wireless systems. The computation block of the digital signal processor is provided with an accelerator for executing instructions associated with trellis computations. An ACS instruction performs trellis computations of alpha and beta metrics. Multiple butterfly calculations can be performed in response to a single instruction. A TMAX instruction is used to calculate the log likelihood ratio of the trellis.

Abstract: A method and apparatus for performing add-compare-select processing using carry-save arithmetic. Data compressors that operate based upon carry-save principles are utilized to render the correct result without requiring intermediate results to be resolved. Intermediate results are truncated to ensure that the dynamic range of the add-compare-select unit is not exceeded, whilst ensuring that the resolution of the intermediate results is not adversely affected. The computation of two competing paths is delayed and only the difference is computed directly, resulting in a reduction of the propagation path through the add-compare-select unit.

Abstract: An error correction code (ECC) block for a data storage disk, includes an array of data that is 88 rows by 172 columns. Each row includes ten bytes of inner parity code and each column includes sixteen bytes of outer parity making the array 104 rows by 182 columns. The ECC block is divided into eight sectors, each sector having eleven rows of data and two associated rows of outer parity, for a total of thirteen rows per sector. The ECC block in accordance with the present invention is half the size of a conventional ECC block but has a higher ratio of parity bytes to data. Consequently, the ECC block of the present invention is particularly advantageous with small form factor disks and first-surface media, i.e., disks with the recording layer on the exterior of the disk or under a very thin transparent layer.

Abstract: A system for co-ordinating the display of a multimedia tour in a selected geographical area comprises a display and an interface for receiving user input to monitor selected display characteristics of the tour. The system includes at least two media types retrievable from a storage medium for presentation on the display. A map of the selected geographical area is provided for presentation on the display. The system includes a marker for indicating a position on the map, and the marker is adapted for relative displacement with respect to the map. The system provides an inter-relater for synchronising the relative displacement between the map and the marker with the playback of the at least two media types on the display. The playback is performed according to the selected display characteristics of the tour.

Abstract: A method of displaying a document e.g. an XML document on a client computer the document comprising data as elements enclosed by tags. The method comprises the steps of retrieving a document from a document server, searching the document for code attribute information, retrieving program code from a code server and displaying the data in the retrieved document by means of the retrieved program code. The method further comprises the steps of retrieving program code from the client computer if the program code is present on the client computer, displaying data of the retrieved document in a default way if the program code could not be retrieved, and deciding whether the retrieved program code should be a plug-in to the method of displaying a document on a client computer. A system for displaying a document on a client computer with a document server with documents and a code server with program code.

Abstract: An edit command delegation (ECD) utility that provides a user with the ability to edit an electronic file in a creator application program while the electronic file is open in a separate viewing application program operable only for viewing the electronic file. In response to a user input to edit the electronic file, the ECD utility opens the electronic file and reads an application identification tag contained within the content of the electronic file. The application identification tag identifies a creator application program, which was used to create the electronic file and is operable for editing the content data of the electronic file. Once the ECD utility reads the application identification tag, the ECD launches the creator application program. The ECD utility then causes the creator application program to open the electronic file. Once the electronic file is open, the content data is displayed in a window controlled by the creator application program to allow the user to edit the content data.

Abstract: An improved system and method for pen-based handwritten and keystroke data input into a computer system is disclosed. The system and method receives pen-based data entry from multiple related input boxes within a handwriting area on a digitizer pad. Thread-based processing allows each input box or group of input boxes to be separately evaluated, providing for continuous character recognition. Character strokes entered into each input box or group of input boxes are saved and interpreted together to allow more complete recognition of naturally written characters. Improvements on keyboard layouts are also disclosed.

Abstract: Computer-implemented system and method for presenting routing information in a measurement system. A meta-routing tool receives user input specifying a device, then retrieves a topography description for the device indicating connectivity between a plurality of components in the device, e.g., from memory or from a server coupled to the computer via a network. The tool then determines routability information for the device based on the topography description, e.g., by walking the topography, and displays the routability information, which is then useable to determine routing for the measurement system. The routability information includes possible routes through the device, and may also indicate potential side effects for one or more of the routes, e.g., sub-systems used by the routes. The tool may receive user input indicating one of the possible routes, and display a component-wise path used by the indicated route, as well as any sub-systems used by the indicated route.

Abstract: A wiring layout method of an integrated circuit is disclosed. Checking of wiring area ratio is performed after an automatic wiring process. For a wiring other than a grid-shaped wiring, the line width W is classified into three steps of line-width range, and a minimum space width Smin between lines in each step of line-width range is defined in advance to satisfy a condition that Wmax/(Wmax+Smin)≦Pmax for a maximum line width Wmax in each step of line-width range. For grid-shaped wirings, a line width W is classified into two steps of line-width range. Further, in its upper step of line-width range, an allowable minimum area Amin (Amin≦Amin0) of a metal-removed area A is defined in advance to satisfy a condition that the wiring area ratio P is less than the allowable maximum value Pmax for a maximum line width Wmax. On the other hand, in its lower step of line-width range, made is a definition that the wiring area ratio P is same as the allowable maximum value Pmax for a maximum line width Wmax.

Abstract: A high level synthesis method for generating a logic circuit of a register transfer level from an operation description includes a control data flowgraph generation stage; a scheduling stage; an allocation stage; a data path generation stage; and a control logic generation stage. When generating a thread sharing a common memory with another thread operating in parallel therewith, a memory access request is represented by a node of a control data flowgraph so as to perform scheduling, and a control logic is generated. The control logic outputs a memory access request signal to a common memory interface in a state corresponding to a step to which the node is scheduled, and keeps the state until a memory access request acceptance signal from the common memory interface is changed to be active.

Abstract: A method for generating a patterned SOI photomask used for embedded DRAMs is described. The method systematically identifies embedded DRAM areas to be excluded from the SOI process and generates the shapes to be printed on the photomask so that the embedded DRAM may be fabricated on bulk silicon. The method includes the steps of: identifying and sorting DRAM array well shapes by common electrical net, resulting in a single array well shape for each electrical net (i.e., embedded DRAM cell). Next, all the n-band contacts touching a given array well shape are collected. These shapes are merged by common electrical net. A shape is then generated which is the smallest enclosing rectangle of the common electrical net of the n-band contact shapes. This represents the patterned SOI shape and defines the bulk areas onto which the embedded DRAM is to be built. Accordingly, the embedded DRAM macro is constructed in bulk areas while the logic is constructed in SOI.

Abstract: A functional testing technique is provided employing an abstraction matrix that describes a complex software component to be tested. The abstraction matrix includes state and event information. The technique is an automated process which parses the abstraction matrix to generate test cases and mapped expected results therefore. The test cases are separated based on layers of the software component and data structures are associated with the separated test cases of the layers. The data structures allow the test cases of the various layers to be uncorrelated. The software component executable is employed to generate test case execution threads from the test cases and mapped expected results for a particular layer. These execution threads can then be executed in parallel, thereby testing the software component.

Abstract: A platform independent analysis architecture analyzes memory images for computer programs. The analysis architecture is platform independent in that it is not tied to a particular version of a computer program and is not dependent on the presence or absence of patches. In addition, the analysis architecture is not tied to the hardware architecture on which the analysis architecture runs. The analysis architecture dynamically determines data type definitions for a computer program to account for the hardware architecture on which the computer program runs, the version of the computer program that is running and the presence or absence of patches. As a result, accurate views of data types may be discerned at run time so that the views of the data types may be employed in analyzing memory images such as crash dumps and run time dumps. This analysis architectures greatly assists parties in debugging computer programs as a result.

Abstract: Software development methods and tools are described to generate visual representations of a system's behavior over time, called “evolution diagrams,” to aid in debugging concurrent software systems. The diagrams take advantage of the exposure provided by coordination interfaces to present more complete views of system executions, explicitly showing events, message traffic between components, etc. The display is presented at a user-selectable hierarchical level of the system design, thus enabling a programmer to work at a design layer where the problem or its effect is easily recognized.

Abstract: A system and method for collecting and displaying object interaction on a target processor is provided which includes the steps of logging object interaction data on a target processor over a monitoring period, and displaying the object interaction data as a graph, the graph having a plurality of nodes and at least one line, each node being associated with a corresponding object, each line connecting two of the nodes and representing an interaction between the respective objects associated with the two nodes.

Abstract: In an architecture having conditional instructions, when a block to be executed if a given condition is true and a block to be executed if the condition is false are structured through if-conversion optimization as a signal basic block in an assembler program by a compiler, in the prior art it has not been possible to establish a correct correspondence between variables and resources when the program is run on a debugging device, resulting in an inability to correctly respond to a user request to display the contents of a variable. According to the present invention, a compiler generates, as debugging information on variables appearing in a source program and the allocation of hardware resources, location information made up of elements showing, for each entry of a variable, an address range within which the variable is valid, a condition flag which is made true within the address range when the variable is valid, and a resource allocated to the variable.

Abstract: One embodiment of the present invention provides a system that facilitates debugging a platform-independent virtual machine. The system operates by providing an agent on the platform-independent virtual machine, which provides a set of functions for accessing variables in the platform-independent virtual machine. The platform-independent virtual machine is adapted to call the set of functions within the agent. Next, the agent examines the current state of the variables in the platform-independent virtual machine. The agent communicates the current state of the variables to a host machine. An operator of the host machine can then analyze the current state of the variables.

Abstract: Debugger impact reduction through motion of an induction variable based breakpoint (“IV-breakpoint”) set within a program loop, where the IV-breakpoint and the loop are controlled by an induction variable having an induction rate, may include extracting, from program code within the program loop, the induction rate; extracting, from the IV-breakpoint, a final value of the induction variable for which the IV-breakpoint would be satisfied; and if the IV-breakpoint is satisfied and the induction variable has a present value that would be beyond the final value upon a next iteration of the loop based on the induction rate, removing the IV-breakpoint. Debugger impact reduction may further include setting, at one or more loop exit program positions, a reset breakpoint; and if one of the reset breakpoints is satisfied, removing the reset breakpoints and/or reestablishing the IV-breakpoint.

Abstract: A simulation system and method enabled through the use of an XML-based Simulation Reference Markup Language (SRML) and a corresponding system runtime environment. The simulation system comprises a simulation reference simulator adapted to receive an SRML simulation model including a simulation item. The simulation reference simulator comprises an item manager for loading properties of each item of the simulation model, and an event manager for processing the simulation model. A method of conducting simulations comprises the steps of defining a simulation model with Simulation Reference Markup Language, communicating the model to a simulation reference simulator, executing the model with the simulation reference simulator, and providing an output of the modeled events.

Abstract: A system, method and article of manufacture are provided for compiling software including unknown parameters. Initially, software is provided including a plurality of first variables without reference to at least one parameter and a plurality of second variables with reference to the at least one parameter. In operation, the software is compiled without the first variables being resolved.

Abstract: Improved techniques for representation of objects in a Java programming environment are disclosed. The techniques are highly suitable for representation of Java objects inside virtual machines, especially those that operate with limited resources (e.g., embedded systems. A cluster of Java object representations is disclosed. Each of the Java object representations provide a reference to a Java object and a reference to the class associated with the Java object. Accordingly, a two-tier representation is provided which allows efficient implementation of applications which need to access information regarding both Java objects and classes. This means that the processing required to perform applications such as garbage collection is reduced. In addition, one of the references in the two-tier representation can be implemented to provide direct access to the internal class representation associated with the object. As a result, quick access to information regarding Java objects can be achieved.

Abstract: A method for interpreter optimization includes receiving multiple data units organized according to a first endian order, reordering the data units according to a second endian order and interpreting the reordered data units. According to one aspect, the data units include at least one opcode having at least one operand, each operand including at least one data unit. According to another aspect, a class loader reorders the code within a classfile from big-endian format to little-endian format.

Abstract: A system for generating a patch file from an old version of data which consists of a series of elements and a new version of data which also consists of a series of elements. The old version of data is sorted with a data processor alphabetically according to an established alphabet to create a first sorted list of data. A pointer is maintained in order to indicate each element's original location in the old version. Similarly, the new version of data is sorted alphabetically to create a second sorted list of data with a pointer of each element to indicate the element's original location in the new version. Once the two sorted lists are created, they are recursively compared one word (a group of elements) at a time to search for a match of data. Upon finding a match of data, the first and second sorted lists are searched to find the largest sequence of coinciding elements preceding and succeeding the match of data. Each sequence of coinciding words is then stored in a coincidences list.

Abstract: The present invention provides an information processor that can move an application easily and safely. In the information processor, a control information retrieving part retrieves the control information that is used to execute a program and a destination defining part defines destination address information to move the program. Then, a moving part moves the program in accordance with the destination address information. Also, a control information changing part changes the control information based on the destination address information.

Abstract: An installation wizard is provided having panels that prompt a user to identify a location where a software prerequisite can be found prior to installing the TBI software. The wizard can optionally allow for the inclusion of files via a standard file browse dialog or via a URL. The prerequisite is then filly integrated into the install process so that, from the perspective of the installer, the installation proceeds seamlessly and without interruption.

Abstract: In one embodiment, a first stage software is bundled together with a first downloadable software available from a first server computer. The first stage software includes computer instructions for downloading a second downloadable software available from a second server computer. When an end-user wishes to download the first downloadable software, the second downloadable software is also offered to the end-user. Accepting the offer results in the first stage software downloading the second downloadable software onto the end-user's client computer. In one embodiment, the second downloadable software is downloaded in chunks.

Abstract: A method of generating personalized television programming content. The method involves developing a user profile and employing a filtering process to isolate relevant content to be presented. The filtering process involves the removal of content that does not fit the customization profiles of any of the system users usage patterns. The method further involves marking content suitable for a particular user and presenting the marked content to the user.

Abstract: In one aspect, the present invention provides a method of non-participatory user identification includes using sensor technology to collect data related to identifying characteristics of a user. The collection preferably requires no active identification measures by the user. The data can be extracted from the sensor technology 12 and matched to a template. This matching can, as an example, be performed using a matcher included in a recognition technology device 14. The user can then be identified based upon the template of data matched. Typically, the recognition technology device 14 will recognize when a new but known fingerprint is operating the user interface. The corresponding user profile may then be used to provide personalized content to the new user.

Abstract: Disclosed is a method and system in which “labels,” comprising supplemental information such as advertising, promotional, or informational elements including interactive elements, may be superimposed post-production into a video stream. This can be done by using overlay screens including interactive overlay screens or by combining video segments. As such, the labels do not have to physically be part of the actual scene during filming. Once a video stream is created, a space for available advertising is designated either manually or automatically by pattern recognition techniques. A list of available advertising space is generated. During viewing of television broadcasts, advertisements are placed in the video signal. Labels are displayed by superimposing an HTML page that is blank except for the advertisement onto the video signal. Advertisements can be superimposed post-production, and can be personalized and localized. The advertisements can be customized on a per-household basis.

Abstract: In a system KBS of up to N channels which are addressed linearly using channel addresses 0 . . . N−1, channel sets KB are formed by intermittent, that is to say in which at least some channel addresses are omitted, allocation of channels. For example, when switching systems are upgraded by adding further switching modules KM, this advantageously allows the scope of the channel sets KB to be changed without restricting the free access capability from output stages AS with single and double throughput.

Abstract: An arrangement for the control of viewing of a video/television program in which a rating code and a position code are transmitted with the video/television signal. The codes are decoded and processed via a microcontroller. A viewer of the video signal is able to enter codes of permitted program ratings using a remote control unit. The rating codes are based upon the content of the video signal. The position codes relate to the display position of possibly objectionable content. Based upon a comparison of the received codes and the permitted program ratings portions of video signal are blanked and/or muted. The position codes allow for sub-portions of the image display to be blocked rather than the entire display.

Abstract: Disclosed are an information processing apparatus and an information processing method, an information providing apparatus and an information providing method, and a program thereof. In an information processing apparatus, the apparatus comprises: an acquiring element for acquiring a file which includes channel data denoting numbers and names of channels of TV programs distributed by a provider and which corresponds to the provider; a generating element for generating internal data based on the channel data in the acquired file, the generated internal data specifying the numbers and names of the channels; and a reception controlling element for controlling reception of the TV programs by selecting the channels based on the internal data.

Abstract: A method and apparatus are described for adapting an entertainment schedule comprising a plurality of programme items. During the execution of the schedule, unforeseen conditions as represented by conditions data (106) may occur causing the data processor (101) to adapt the remaining portion of the schedule. The data processor co-operates with a tuner (118), a library server (120) and a timeshifter (122) to execute the adapted schedule. The timeshifter adjusts specified programme items received from the tuner (118) and library server (120) in conjunction with timeshifter storage (126) thereby ensuring a sequence of programme items are output at (128), the sequence comprising substantially the same material as contained in the original schedule prior to the occurrence of the condition.