Abstract: A device for detection of one or more analytes in a sample is disclosed. The device can simultaneously detect and quantitate multiple analytes in a sample. The device comprises an eletromagnetic radiation generator having one or more chemical sensors thereon. The chemical sensor interacts with or reacts with specific analytes in a sample. The presence of an analyte is detected by a comparison of the spectroscopic properties of the chemical sensor in the absence and presence of the analyte. A method is also disclosed for the detection and quantitation of analytes using the device of the present invention. In addition, a method of making the device of the present invention is also disclosed.

Abstract: Microfluidic devices and systems having enhanced detection sensitivity, particularly for use in non-fluorogenic detection methods, e.g., absorbance. The systems typically employ planar microfluidic devices that include one or more channel networks that are parallel to the major plane of the device, e.g., the predominant plane of the planar structure, and a detection channel segment that is substantially orthogonal to that plane. The detection system is directed along the length of the detection channel segment using a detection orientation that is consistent with conventional microfluidic systems.

Abstract: The present invention relates to a system and methods for facilitating the analysis of proteomic expression data. In this system, complex sequence-correlated peptide expression information and mass spectrum data are processed and stored in a relational database. Using a parallel computational method, the expression data and results are parsed and associated to rapidly yield peptide sequence information. The system automates necessary tasks associated with peptide data analysis and organizes large amounts of information needed to perform the data analysis in a logical and accessible manner.

Abstract: The present invention relates to a method for screening drugs for use in treating hypertension using the tubular renin-angiotensinogen system identified by the present invention. The invention further relates to a method to diagnose sodium status and sensitivity in an individual by measuring urinary angiotensinogen or angiotensin-I.

Abstract: A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).

Abstract: The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic precursor is provided proximate the substrate. The precursor is exposed to a reducing atmosphere to release metal from the precursor, and subsequently the released metal is deposited over the semiconductor substrate. The invention also includes capacitor constructions, and methods of forming capacitor constructions.

Abstract: A method of conducting a laser repair operation. A silicon wafer has a plurality of chips thereon. Each chips has a plurality of bonding pads, a plurality of testing pads, a plurality of fuses and a passivation layer for protecting the chips. The passivation layer exposes the bonding pads and the testing pads. A bump-forming process is conducted to form a bottom metallic layer and a bump sequentially over each bonding pad. Only a bottom metallic layer is formed over each testing pad. The bumps are formed, for example, by electroplating or printing. Testing is carried out by probing various bottom metallic layers above the testing pads. Finally, a laser repair is conducted.

Abstract: A technique for fabricating a plurality of thin film filters (“TFFs”), and other optical devices, from a wafer. A device or TFF wafer is affixed to a carrier having a pattern of notches formed thereon corresponding to a pattern into which the wafer is to be diced to form the TFFs. The notches are sized to allow clearance of a dicing apparatus. The wafer is diced at least partially into the notches to form the TFFs, and the TFFs may be individually optically tested with a light source aligned thereto, while they remain affixed to the carrier. The TFFs are removed from the carrier for operation, and the carrier can be re-used. To facilitate re-use, a releasable adhesive is applied to the wafer and/or the carrier, and the notches receive any excess adhesive when the wafer is being affixed to the carrier.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying a monocrystalline substrate of a semiconductor structure by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. An optical waveguide is formed in a monocrystalline layer grown on the semiconductor structure for distributing an optical signal to a selected portion of circuitry formed in the semiconductor structure. An optical source is formed in the semiconductor structure and coupled to the optical waveguide for generating a control signal and a data signal concurrently.

Abstract: An apparatus and method for suspending a movable structure form a support structure wherein first and second flat and thin arcuately shaped flexures are formed having spaced apart substantially planar and parallel opposing surfaces, each of the first and second flexures being structured for connection between a support structure and a movable structure to be suspended from the support structure and being aligned along a common axis of rotation between the support structure and the movable structure.

Abstract: Micromechanical devices are provided that are capable of movement due to a flexible portion. The micromechanical device can have a flexible portion formed of an oxide of preferably an element from groups 3A to 6A of the periodic table (preferably from the first two rows of these groups) and a late transition metal (preferably from groups 8B or 1B of the periodic table). The micromechanical devices can be any device, particularly MEMS sensors or actuators preferably having a flexible portion such as an accelerometer, DC relay or RF switch, optical cross connect or optical switch, or a micromirror part of an array for direct view and projection displays. The flexible portion is preferably formed by sputtering a target having a group 8B or 1B element and a selected group 3A to 6A element, namely B, Al, In, Si, Ge, Sn, or Pb. The target can have other major constituents or impurities (e.g. additional group 3A to 6A element(s)).

Abstract: In a method of depositing a silicon thin film by using a vertical plasma CVD apparatus having steps of holding a substrate having an area not smaller than 1,200 cm2 and having a conductive film formed thereon with a substrate holder, disposing the substrate to face an electrode, and depositing a silicon thin film under a power density of 100 mW/cm2 or more, the substrate holder is electrically insulated from the conductive film formed on the surface of the substrate by forming a separation groove in the conductive film.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The foregoing is utilized for a microcavity semiconductor laser coupled to a waveguide.

Abstract: A three-dimensional multichip module having a base structure formed by a plurality of chips secured together in a stack and a plurality of exterior chips mounted to the exterior faces of the base structure. The multichip module may incorporate memory chips, processor chips, logic chips, A to D converter chips, and other chips in a compact package. The module permits chips that require extensive cooling to be positioned within the structure in a manner such that a large surface area of the chip is not in contact with other chips. The module also permits extensive interconnection between chips within the module.

Abstract: A method to realize low-profile semiconductor devices by grinding a resin sealed block and realize level grinding by eliminating warpage of the resin sealed block. Semiconductor devices 10 are produced by step (B) in which multiple semiconductor chips 11 are mounted face down onto the surface of substrate 12, step (C) in which molding resin 13 is injected onto substrate 12 in order to form resin sealed block 18 in which multiple semiconductor chips 11 are sealed, step (E) in which resin sealed block 18 is cut halfway from the side of substrate 12, and step (F) in which resin sealed block 18 is ground from the side of molding resin 13 in order to separate it into individual semiconductor devices 10.

Abstract: In a method for manufacturing a printed circuit board, openings are perforated in a first resin substrate. Then, a conductive layer is formed on a surface of the first resin substrate and within the openings of the first resin substrate. Then, a second resin substrate is adhered to the conductive layer by an adhesive layer. Then, the first resin substrate is peeled off from the conductive layer, so that the conductive layer is transferred from the first resin substrate to the second resin substrate.

Abstract: A method of fabricating a thin film transistor array panel for a liquid crystal display is provided. A gate line assembly is formed on an insulating substrate. The gate line assembly includes gate lines and gate electrodes connected to the gate lines. A gate insulating layer is formed on the insulating substrate having the gate line assembly. A semiconductor layer is formed on the gate insulating layer. A data line assembly is formed, the data line assembly includes data lines crossing over the gate lines, source electrodes connected to the data lines and placed adjacent to the gate electrodes, and drain electrodes placed opposite to the source electrodes with respect to the gate electrodes. A protective layer is deposited onto the insulating substrate having the data line assembly. The protective layer is patterned to form first contact holes exposing the drain electrodes.

Abstract: Two kinds of TFTs are fabricated by the same process with a high production yield to manufacture an active-matrix circuit and a peripheral driver circuit on the same substrate. The active-matrix circuit is required to have a high mobility and a high ON/OFF current ratio. The peripheral driver circuit needs a complex interconnection structure. The active-matrix circuit and the peripheral driver circuit comprising the TFTs are fabricated monolithically. In this step, the gate electrodes of the TFTs of the active-matrix circuit is coated with an anodic oxide on their top and side surfaces. The gate electrodes of the TFTs of the peripheral driver circuit is coated with the anodic oxide on only their top surfaces; substantially no anodic oxide is present on the side surfaces.

Abstract: A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier materials.

Abstract: A method for manufacturing a monolithic apparatus including a plurality of materials presenting a plurality of coplanar lands includes the steps of: (a) providing a substrate constructed of a first material and presenting a first land; (b) trenching the substrate to effect a cavity appropriately dimensioned to receive a semiconductor structure in an orientation presenting a second land generally coplanar with the first land; (c) depositing an accommodating layer constructed of a second material on the substrate and within the cavity to establish a workpiece; (d) depositing a composition layer constructed of a third material on the substrate; (e) selectively removing portions of the composition layer and the accommodating layer to establish the semiconductor structure; (f) depositing a cap layer constructed of a fourth material on the workpiece; and (g) removing the cap layer to establish a substantially planar face displaced from the plurality of lands by a predetermined distance.

Abstract: There is disclosed a method of fabricating TFTs using a silicon film crystallized with the aid of nickel. The nickel is removed from the crystallized silicon film. The method starts with maintaining nickel in contact with the surface of an amorphous silicon film. Then, a heat treatment is performed to form a crystalline silicon film. At this time, nickel promotes the crystallization greatly, and nickel diffuses into the film. A mask is formed. A silicon film heavily doped with phosphorus is formed. Thereafter, a heat treatment is performed to move the nickel from the crystalline silicon film into the phosphorus-rich silicon film. This reduces the concentration of nickel in the crystalline silicon film.

Abstract: A semiconductor memory apparatus includes a first and second memory bank. Each of these memory banks has a plurality of row and column lines and at least one redundant column line. An activation device selectively activates the redundant column line, thereby causing the redundant column line to become a replacement line for a defective column line. The activation device includes a plurality of programmable addressing fuses, and a programmable selection fuse having at least two electrical selection fuse states. The programmable selection fuse is configured such that an addressing fuse in the first selection fuse state is electrically associated with the first memory bank and an addressing fuse in the second selection fuse state is electrically associated with the second memory bank.

Abstract: The present invention relates to a process for producing contact holes on a metallization structure, which can be used, for example, to produce electrical contacts between adjacent metallization levels. A dielectric layer is applied to interconnects which are covered with a hard-mask layer that is usually used for patterning the interconnects. Then, contact holes are etched through the dielectric layer, and this step is ended as soon as the hard-mask layer is reached. Then, the hard-mask layer is etched selectively with respect to the dielectric layer, so that the phenomenon where the contact holes break out into the space between adjacent interconnects is minimized. In this way the risk of short circuits is drastically reduced.

Abstract: A new method is provided for the creation of PIP capacitors for mixed-mode processes. The process starts with the creation of Shallow Trench Isolation regions in the surface of a substrate, defining active regions and the region over which the PIP capacitor is to be created on the surface of the substrate. The PIP STI region is etched, lowering the surface of the PIP STI region. A first layer of polysilicon is selectively deposited in the opening created in the layer of STI over which the PIP is to be created, the first layer of polysilicon is polished. The wells for the isolation of the gate electrode and the PIP STI region are implanted in the surface of the substrate. A layer of insulation, serving as the layer of dielectric for the capacitor, is blanket deposited over the surface of the substrate. The deposited layer of insulation is patterned and etched, leaving the layer of insulation in place overlying the first layer of polysilicon.

Abstract: In a chip package, when a Ni/Au layer is formed by electroless plating, there is no problem with density increasing of interconnections and the like, since leads for plating and tie bars are not formed. However, the adhesive strength of solder balls to ball pads is low, so that the adhesion tends to be unstable. In the present invention, no leads for plating are formed, while the adhesive strength of solder balls to ball pads is improved by electroplating the ball pads with a Ni/Au layer. In addition, an increase in the density of interconnections and an improvement of the electrical properties is also obtained. The Ni/Au layer is formed by electroplating on the base metal layer surface which is not covered with a DFR (Dry Film Resist) by applying an electric current to the base metal layer.

Abstract: An improved method of fabricating a non-volatile semiconductor device having a BPTEOS oxide film is provided. The present method utilizes the step of performing a RTA at a temperature of about 800° C. immediately after the deposition of the BPTEOS film so as to densify and stabilize the same. Then, a CMP step is performed so as to planarize the BPTEOS film.

Abstract: A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e.g., wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.

Abstract: The present invention relates to a process of forming a phase-change memory. A lower electrode is disposed in a first dielectric film. The lower electrode comprises an upper section and a lower section. The upper section extends beyond the first dielectric film. Resistivity in the upper section is higher than in the lower section. A second dielectric film is disposed over the first dielectric film and has an upper surface that is coplanar with the upper section at an upper surface.

Abstract: This invention relates to a method of forming a word line, more particularly, to the method of forming a word line in an embedded dynamic random access memory (eDRAM). The present invention uses a sandwich structure in silicon (Si)/tungsten silicon (WSi)/buffer layer to be the structure of the word line in the embedded dynamic random access memory to keep the enough thickness of the nitride layer, which is on the gate, and to proceed the self-aligned contact process in the embedded dynamic random access memory region in the following process to increase the efficiency of the process. The gate, which is formed by using the present invention method and is proceed the metal salicide process in the logic region that is in the embedded dynamic random access memory, will keep the low resistance of the word line and will increase the efficiency of the embedded dynamic random access memory.

Abstract: A method for fabricating a nonvolatile semiconductor memory device according to the present invention includes patterning an insulating film for forming a tunnel insulating film and a conductor film for forming a floating gate electrode and forming a well region of a first conductivity type in the logic circuit portion of a semiconductor substrate. This prevents the well region in the logic circuit portion from experiencing a thermal budget resulting from the formation of the insulating film and the conductor film.

Abstract: Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices.

Abstract: An N-channel radiation-hardened transistor has source and drain regions that are fully enclosed by an intrinsically radiation-hardened thin gate-oxide, which substantially reduces radiation-induced intra-device and inter-device leakage currents. The width of the polysilicon gate directly between the source and drain can be the minimum feature size allowed by the design rules of a given process. The width of the polysilicon surrounding the device is chosen by design rules from the minimum allowed to some wider value to allows the polysilicon overlap to be sufficient to self-align the source and drain without compromising the doping under the field region. The polysilicon should be sufficiently wide so that it completely overlaps any transitional oxide such as LOCOS or trench oxide. The gate capacitance of the N-channel transistor can be tuned to balance SEU hardness and switching performance.

Abstract: A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

Abstract: A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition.

Abstract: A method for manufacturing a capacitor of a semiconductor device is provided. The method includes the steps of: forming a first electrode on a semiconductor substrate; forming a dielectric layer on the first electrode; forming a second electrode on the dielectric layer; first annealing the capacitor having the first electrode, the dielectric layer, and the second electrode under oxygen atmosphere; and second annealing the capacitor having the first electrode, the dielectric layer, and the second electrode under vacuum.

Abstract: A method for the simultaneous formation of a gate electrode and a local interconnect or other interconnect structure in a semiconductor device is provided. In an embodiment of the method, an insulating layer disposed adjacent to a gate transistor is patterned to form an opening for the interconnect structure, and a sacrificial layer (e.g., silicon nitride) of the gate stack is removed to form a recess in the gate stack and expose an underlying conductive layer (e.g., polysilicon). A conductive material such as tungsten is deposited to simultaneously fill the recess of the gate stack and the opening in the insulating layer to form the interconnect structure. Exemplary interconnect structures include local interconnects, contacts, buried contacts, plugs, contact landing pads, and filled trenches.

Abstract: A process flow for forming a sacrificial collar (132) within a deep trench (113) of a semiconductor memory cell. A nitride liner layer (120) is deposited over a substrate (111). A thin polysilicon layer (122) is deposited over the nitride liner layer (120), and an oxide layer (124) is formed. A resist (116) is deposited within the trenches (113) and etched back. The top portion of the oxide layer (124) is removed, and the resist (116) is removed from the trenches (113). The wafer (100) is exposed to a nitridation process to form a nitride layer (128) over exposed portions of the polysilicon layer (122). The oxide layer (124) and polysilicon layer (124) are removed from the bottom of the trenches (113). The nitride liner layer (120) is removed from the bottom of the trenches (113). The polysilicon layer (122) is removed from the top of the trenches (113) to leave a sacrificial collar (132) in the top of the trenches 113 formed by nitride liner layer (120).

Abstract: The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic precursor is provided proximate the substrate. The precursor is exposed to a reducing atmosphere to release metal from the precursor, and subsequently the released metal is deposited over the semiconductor substrate. The invention also includes capacitor constructions, and methods of forming capacitor constructions.

Abstract: In a process for manufacturing a dielectric capacitor using a SBT film as its dielectric film, an IrO2 film 2, Ir film 3, both making up a lower electrode, an amorphous film 4 as a precursor film of the SBT film, and a Pt film 5 as an upper electrode are sequentially made on a Si substrate 5. Then, the Pt film 5, amorphous film 4, Ir film 3 and IrO2 film 2 are patterned into the form of the dielectric capacitor, and the amorphous film 4 is annealed to change the amorphous phase in the amorphous film 4 to a crystal phase of a perovskite type crystalline structure and thereby obtain the SBT film 6. Therefore, even when the decrease in area of dielectric capacitors progresses, a dielectric capacitor with good characteristics can be realized, and a semiconductor storage device using a dielectric capacitor having good characteristics can be obtained.

Abstract: The present invention provides a method of manufacturing an interdigitated semiconductor device. In one embodiment, the method comprises simultaneously forming first electrodes adjacent each other on a substrate, forming a dielectric layer between the first electrodes, and creating a second electrode between the first electrodes, the second electrode contacting the dielectric layer between the first electrodes to thereby form adjacent interdigitated electrodes. An interdigitated capacitor and a method of manufacturing an integrated circuit having an interdigitated capacitor are also disclosed.

Abstract: A method of producing a wafer comprising conducting a baking treatment on a sintered silicon carbide cut in the form of wafer. An embodiment in which the temperature for the above-mentioned baking treatment is 1350° C. or more, embodiments in which the temperature for the above-mentioned baking treatment is 1400 to 1550° C. and the pressure for the above-mentioned baking treatment is 10−4 Torr or less, and the like are preferable. A wafer which can be produced by the above-mentioned method of producing a water. Embodiments in which the above-mentioned flexural strength measured by a flexural test method (JIS 1601) is 700MPa or more, the above-mentioned element composition ratio Si/C in all parts is 0.48/0.52 to 0.52/0.48, and the above-mentioned density is 2.9g/cm3 or more.

Abstract: A method of manufacturing a semiconductor device comprises providing a semiconductor substrate that includes a first active region having a first area, a second active region having a second area that is larger than the first area and an isolation region. Then, a mask layer is selectively formed on the first and second active regions. A trench is formed on the isolation region of the substrate. A first isolation material is deposited on the trench and the mask layer so that the trench is filled with the first material and the first material covers the first and second active regions. The first material is subjected to a chemical mechanical polish so that the mask layer formed on the first active region is exposed while the mask layer formed on the second active region is still covered by the first material. Then, a second insulation material is deposited on the exposed mask layer and the first material.

Abstract: A method of preparing a semiconductor structure comprises:

Abstract: Systems for assembling wafer stacks are provided. An embodiment of the system includes a vacuum chamber, a media deposition component and a wafer stack assembly component. The media deposition component is arranged within the vacuum chamber and is configured to deposit storage media upon a first wafer. The wafer stack assembly component also is arranged within the vacuum chamber. The wafer stack assembly component is configured to align the first wafer and a second wafer relative to each other and bond the first wafer and the second wafer together while at least a portion of the vacuum chamber is maintained under vacuum pressure. So configured, the interior chamber of the wafer stack can be formed as well as maintained under vacuum pressure. Methods also are provided.

Abstract: Devices for manipulating, receiving and dispensing diced semiconductor materials, in which the semiconductor material is diced to provide partially connected dice in linear aggregations.

Abstract: A method for operating a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. The two doped regions are set to be a drain region and a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative high-level bias, and the source region and the substrate are applied with a grounded voltage. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative voltage in absolute value. In the mean time, the drain region is applied with the third negative bias and the substrate is applied with a grounded voltage. The third negative voltage is larger than the second negative bias in absolute value.

Abstract: A laser annealing method includes preparing a plurality of polycrystalline silicon film samples having different grains sizes, obtaining the energy density condition corresponding to the polycrystalline silicon film sample having the highest degree of scattering, adding a certain value of the energy density to the energy density condition obtained in the preceding step so as to determine a set value of the energy density, and irradiating the amorphous silicon thin film with a laser beam at the set value of the energy density determined in the preceding step so as to carry out the laser annealing.

Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

Abstract: In order to prevent abnormal oxidation of the side wall of a polycide gate conductor layer in the oxidation heat treatment process after the RIE processing of the polycide gate conductor layer in a semiconductor memory cell, the heat treatment for oxidizing the side wall of the polycide gate conductor layer is conducted in two steps with different conditions. By conducting the first heat treatment process in an inert atmosphere, a thin oxide film is formed on the side wall of the polycide tungsten/gate conductor layer. Then by conducting the second heat treatment process in an atmosphere with a strong oxidizing property, a thick oxide film without abnormal oxidation can be formed.

Abstract: The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material.