Abstract: Metal bumps are formed by using a bump material containing a metal material which melts only partially at a first temperature and melts entirely at a second temperature higher than the first temperature. A resin film is first formed on a surface of a substrate provided with electrodes. Then, openings are formed in the resin film for exposing the electrodes. Then, the bump material is loaded into the openings. Then, the bump material is heated to the first temperature for melting only part of the metal material, followed by cooling the bump material below the first temperature. Then, the resin film is removed. Finally, the bump material is heated to the second temperature for entirely melting the metal material.

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Abstract: A method to realize extremely low profiling of semiconductor devices without reducing the yield and productivity. Semiconductor devices 10 are fabricated using step (B), in which multiple semiconductor chips 11 are mounted on substrate 12 having multiple adjoining chip mounting areas with their functional planes 11a facing the plane of said substrate; step (C), in which molding resin 13 is supplied to aforementioned substrate 12 in order to seal aforementioned multiple semiconductor chips 11; step (D), in which aforementioned molding resin 13 on aforementioned substrate 12 is ground together with said semiconductor chips 11 from its front side until aforementioned semiconductor chips 11 reaches a prescribed thickness; and step (F), in which substrate 12 mounted with aforementioned semiconductor chips 11 is cut into dice together with aforementioned molding resin 13 to form individual semiconductor devices 10.

Abstract: The invention includes a method of fabricating a circuit in a manner to place certain structures within a predefined distance of one another. Electrical connections are formed between certain structures of silicon, by annealing a conductive material to cause silicon out-diffusing to form local interconnects. The silicon out-diffusion can be facilitated without a masking step thereby simplifying as well as speeding up the fabrication process. The invention also includes a local interconnect thus formed.

Abstract: A method and apparatus for bus compression in an array processing system, involving providing a data bus making multiple data bus connections between two separate processing modules; compressing bus signals outputted by at least one of the processing modules with an associated bus modulator effective to permit concurrent transfer of a plurality of bits of information per connection; transferring the compressed signals via the data bus to a bus demodulator associated with the other processing module, wherein the demodulator reconstructs the bus signals before inputting the signals to the other processing module; wherein at least one of the processing modules is formed at least in part in CMOS in a unique semiconductor structure.

Abstract: This invention provides a method for manufacturing a semiconductor device capable of forming a fine interconnection structure without making the resistance at the through hole high. More specifically, the present invention provides a semiconductor device having a first interconnection formed on the surface of a first layer insulating film and a second interconnection provided on the upper part of the first interconnection and electrically connected to the first interconnection, and wherein the first interconnection is formed so that the width of the lower part may become narrower than that of the upper part.

Abstract: An interlayer film covering a semiconductor device formed on the semiconductor substrate has a film having ability of gettering the metal impurities invading from an upper portion of the interlayer film, and with this ability, the metal impurities are prevented from reaching the semiconductor substrate.

Abstract: Disclosed is a method for manufacturing multilayer ceramics, and in particular, a method for manufacturing multilayer ceramics with improved interlayer bonding by laminating ceramic tapes manufactured from slurry under vacuum and sintering them. The method comprises the steps of: admixing an organic substance comprising a dispersion agent, a plasticizer, and a binder with ceramic powder to give slurry; defoaming the ceramic slurry under vacuum, followed by casting the defoamed ceramic slurry into ceramic tapes; laminating the ceramic tapes at room temperature to 100° C. under vacuum less than 1 atm; burning out the organic substances from the ceramic tapes laminated under vacuum; and sintering the laminated ceramic tapes free of organic substances.

Abstract: A method is provided for selectively depositing a silicided metal nitride diffusion barrier layer in a semiconductor structure including providing at least one anisotropically etched opening extending through at least one insulating layer and in closed communication with a metallic underlayer; conformally depositing a metal nitride layer over the at least one anisotropically etched opening under conditions such that the metal nitride layer has a relatively higher deposition rate onto the sidewalls of the at least one anisotropically etched opening for a period of time compared to a deposition rate over the metallic underlayer; and, exposing the metal nitride layer to a silicon containing gaseous ambient under conditions such that silicon is incorporated into the metal nitride layer to form a silicided metal nitride layer.

Abstract: Disclosed herein is a method of etching platinum using a silicon carbide mask. The method comprises providing an etch stack including a patterned silicon carbide layer overlying a layer of platinum, then pattern etching the platinum layer using a plasma generated from a source gas comprising Cl2, BCl3, and a nonreactive, diluent gas. The silicon carbide mask can be deposited and patterned using standard industry techniques, and can be easily removed without damaging either the platinum or an underlying doped substrate material. The method provides a smooth platinum etch profile and an etch profile angle of about 75° to about 90°. Also disclosed herein are methods of forming semiconductor structures useful in the preparation of DRAM and FeRAM cells.

Abstract: A method for forming a hybrid active electronic and optical circuit using a lithography mask. The hybrid active electronic and optical circuit comprising an active electronic device and at least one optical device on a Silicon-On-Insulator (SOI) wafer. The SOI wafer including an insulator layer and an upper silicon layer. The upper silicon layer including at least one component of the active electronic device and at least one component of the optical device. The method comprising projecting the lithography mask onto the SOI waver in order to simultaneously pattern the component of the active electronic device and the component of the optical device on the SOI wafer.

Abstract: A method for forming a hybrid active electronic and optical circuit using a lithography mask. The hybrid active electronic and optical circuit comprising an active electronic device and at least one optical device on a Silicon-On-Insulator (SOI) wafer. The SOI wafer including an insulator layer and an upper silicon layer. The upper silicon layer including at least one component of the active electronic device and at least one component of the optical device. The method comprising projecting the lithography mask onto the SOI waver in order to simultaneously pattern the component of the active electronic device and the component of the optical device on the SOI wafer.

Abstract: Disclosed is a copper-based metal polishing solution which hardly dissolves a Cu film or a Cu alloy film when the film is dipped into the solution, and has a dissolution velocity during polishing several times higher than that during dipping. This copper-based metal polishing solution contains at least one acid selected from aminoacetic acid and aminosulfuric acid, an oxidizer, and water.

Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.

Abstract: An aqueous solution containing sulfuric acid and hydrogen peroxide is used for a soft etchant in a soft etching step in a smear removing process performed prior to a catalyst applying process for chemical copper plating after formation of via holes through an insulating layer of a multi-layer substrate by irradiation of laser. The concentration of sulfuric acid is 1.4 times or less higher than the concentration of hydrogen peroxide. Preferably, the concentration of sulfuric acid is in a range of 5 to 50 g/l, and the concentration of sulfuric acid is lower than the concentration of hydrogen peroxide. More preferably, the concentration of sulfuric acid is in a range of 5 to 10 g/l, and the concentration of hydrogen peroxide is in a range of 30 to 35 g/l. As a result, smear can be certainly removed without excessively etching a conductive layer in the smear removing process.

Abstract: Embodiments of the present invention relate to a method and a system for determining an exposure time of a wafer photolithography process is applied to a wafer photolithography system and is used to determine the preferred exposure time for the L(N) batch production wafer. In one embodiment, at least three batches of the batch test wafers are recalled in a time sequence and the corresponding test values are obtained. A mean value of the test values corresponding to the at least three batches of the batch test wafers is calculated with a predetermined mathematical model. The calculated mean value is compared with a predetermined qualified examination value, and a margin value between the mean value and the qualified examination value is thus determined to adjust and generate an appropriate process exposure time. The preferred process exposure time is then employed as the exposure time of the L(N) batch production wafer.

Abstract: A method of forming structures in semiconductor devices through a buffer or insulator layer comprising the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by CMP.

Abstract: A method of cleaning a semiconductor fabrication processing chamber involves recirculation of cleaning gas components. Consequently, input cleaning gas is utilized efficiently, and undesirable emissions are reduced. The method includes flowing a cleaning gas to an inlet of a processing chamber, and exposing surfaces of the processing chamber to the cleaning gas to clean the surfaces, thereby producing a reaction product. The method further includes removing an outlet gas including the reaction product from an outlet of the processing chamber, separating at least a portion of the reaction product from the outlet gas, and recirculating a portion of the outlet gas to the inlet of the processing chamber.

Abstract: In a first aspect, a system is provided that includes (1) a substrate support adapted to hold and rotate a substrate; (2) a source of fluid adapted to supply fluid to a surface of a substrate held by the substrate support; and (3) a shield positioned to capture fluid supplied by the source of fluid and displaced from a substrate held and rotated by the substrate support. The shield includes a radiused surface adapted to carry the captured fluid away from the substrate held by the substrate support. Apparatus and methods in accordance with this and other aspects also are provided.

Abstract: A method of creating and using a polishing substrate having a coating layer that includes providing a substrate having a predetermined pattern disposed on a surface of the substrate and coating the surface of the substrate with an abrasive to form a coated substrate conforming to the predetermined pattern is described. In addition, an apparatus enabling preparation and use of a fixed abrasive polishing member is described that includes a patterned substrate, an abrasive coating a surface of the patterned substrate and a vacuum deposition chamber in which the abrasive is applied to the surface of the substrate. In addition, rather than a fixed abrasive, non-abrasive material may be applied to the surface of the patterned substrate, in which case, a conventional slurry may be used in planarization of an applied semiconductor wafer.

Abstract: A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.

Abstract: A method for forming a high resistance resistor with an integrated high voltage device process is disclosed. First and second field oxide areas are formed on a substrate and an undoped first polysilicon layer is deposited. A first photoresist layer having a resistor pattern is formed on the first field oxide area and a first ion implant process is performed with the first photoresist layer as a mask which is then removed and an oxide nitride oxide (ONO) layer is formed on the first polysilicon layer. The ONO layer and the first polysilicon layer are etched to form a resistor on the first field oxide area and a first electrode of a capacitor on the second field oxide area. A second polysilicon layer is formed on the capacitor ONO layer as a second electrode of the capacitor. A second photoresist layer is formed on the substrate, the resistor and the capacitor and has an opening pattern to expose the resistor. The ONO layer is removed from the resistor.

Abstract: A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer and a Cr layer are sequentially deposited on a substrate on which a gate wire is formed. Next, the Cr layer is patterned to form a data line, a source electrode and a drain electrode. The doped amorphous silicon layer and the amorphous silicon layer are patterned at the same time, and the doped amorphous silicon layer is etched by using the data line, the source electrode and the drain electrode as etch stopper. Subsequently, a passivation layer is deposited and patterned to form a contact hole. An ITO layer is deposited and patterned to form a pixel electrode. According to the present invention, an oxide layer is prevented by performing a sequential deposition of the four layers in a vacuum state. As a result, the on current of the TFT is increased, and HF cleaning is not necessary because no oxide layer is formed. Therefore, the overall TFT manufacturing process is simplified.

Abstract: A method for the fabrication of a gate stack, in particular in very large scale integrated semiconductor memories, uses a combination of a damascene process and a CMP process to produce a gate stack which includes a polysilicon section, a silicide section and a covering-layer section thereabove. The gate stack can be fabricated by using conventional materials, has a very low sheet resistance of <1 ohm/unit area and may carry self-aligning contact sections.

Abstract: A method of etching the trench portions of a thermal inkjet printhead using a robust mask that precisely defines the area of the substrate surface to be etched and that protects the adjacent drop generator components from damaging exposure to the silicon etchant. The process in accordance with the present invention uses as a mask some of the material that is also used in patterned layers for producing the drop generator components on the substrate. The placement of the mask components on the substrate occurs simultaneously with the production of the drop generator components, thereby minimizing the time and expense of creating the silicon-etchant mask.

Abstract: An amorphous material containing silicon, carbon, hydrogen and nitrogen, provides a barrier/etch stop layer for use with low dielectric constant insulating layers and copper interconnects. The amorphous material is prepared by plasma assisted chemical vapor deposition (CVD) of alklysilanes together with nitrogen and ammonia. Material that at the same time has a dielectric constant less than 4.5, an electrical breakdown field about 5 MV/cm, and a leakage current less than or on the order of 1 nA/cm2 at a field strength of 1 MV/cm has been obtained. The amorphous material meets the requirements for use as a barrier/etch stop layer in a standard damascene fabrication process.

Abstract: A method is described for improving the exposure focus for modern steppers used in the lithography of semiconductor substrates such as wafers. A wafer is sawed from a semiconductor ingot in a particular direction relative to a reference point on the ingot. As a result of the sawing, a series of raised and recessed formations manifest on the surface of the wafer. After various layers have been added to the wafer and the photoresist layer is ready to be removed, the wafer is aligned with the stepper so that a dynamic focus area of the stepper is aligned with the formations and/or the sawing direction. Such alignment improves the critical dimension control and reduces variability in printing small geometry features during lithography, resulting in higher yields.

Abstract: An etching end point judging device which uses emission spectroscopy for dry etching. The device includes an AND converter for obtaining time series data of emission intensity of a specific wavelength produced during etching, a first digital filter for performing smoothening of the time series data, a differential operator for obtaining a differential coefficient of the smoothened time series data, a second digital filter for smoothening the calculated differential coefficient of the time series data, and a discriminator for judging the etching end point by comparing said smoothened differential coefficient with a value set beforehand.

Abstract: A patterned organic masking layer is formed outwardly of a feature layer to be etched. It has at least one feature pattern having a minimum feature dimension of less than or equal to 0.3 micron. The feature layer has a thickness which is to be etched to form the one feature pattern in the feature layer. The feature pattern is plasma etched into the feature layer using the masking layer as a mask. The plasma etching comprises at least one etching segment where at least 30% of said thickness of the feature layer is etched using an etching gas comprising one gas compound comprising carbon, hydrogen and at least one halogen present at greater than or equal to 70% concentration by volume as compared to all carbon, hydrogen and halogen containing gas compounds in the etching gas.

Abstract: First of all, a semiconductor substrate is provided. Then a photoresist layer is formed on the semiconductor substrate, and the photoresist layer is defined to form a pre-region. Afterward, an ion-implanting process is performed by using the photoresist layer as an ion-implanting mask to form an ion-implanting region in the semiconductor substrate of the pre-region. Because the surface of the photoresist layer is bombarded with ions, a hard mask is formed on the photoresist layer. Subsequently, an etching process with fluorine-based plasma is performed to strip the hard mask. An ashing process with the temperature about, but more than 250° C. is performed by way of an oxide plasma process to remove the photoresist layer. Finally, a soak process with a sulfuric acid and a cleaning process with the RAC are performed to remove the remainder of the photoresist layer.

Abstract: Methods for fabricating semiconductor devices are described, including methods which improve an etching selection ratio of a film to be etched against metal silicide, Si, and photoresist. One method for fabricating a semiconductor device includes the steps of forming Ti silicide films 9a-9c on the gate electrode 3 and the diffusion layers 6 and 7 of source/drain regions, forming an interlayer dielectric film 10 on the Ti silicide films, and dry-etching the interlayer dielectric film to form in the interlayer dielectric film 10 a contact hole 10a located above the gate electrode, and contact holes 10b and 10c located above the diffusion layers of the source/drain regions, wherein etching gas used for the dry-etching is gas including at least fluorocarbon gas and one of O2 gas and O3 gas, and the temperature of the semiconductor substrate is 30° C. or lower when the dry-etching is conducted.

Abstract: In one aspect, the invention includes a method of removing at least a portion of a material from a substrate, comprising: a) first etching the material in a reaction chamber; b) second etching the material in the reaction chamber; and c) cleaning a component of the material from at least one sidewall of the reaction chamber between the first etching and the second etching.

Abstract: An oxide etching recipe including a heavy hydrogen-free fluorocarbon having F/C ratios less than 2, preferably C4F6, an oxygen-containing gas such as O2 or CO, a lighter fluorocarbon or hydrofluorocarbon, and a noble diluent gas such as Ar or Xe. The amounts of the first three gases are chosen such that the ratio (F—H)/(C—O) is at least 1.5 and no more than 2. Alternatively, the gas mixture may include the heavy fluorocarbon, carbon tetrafluoride, and the diluent with the ratio of the first two chosen such the ratio F/C is between 1.5 and 2.

Abstract: Method of forming a metal pattern on a dielectric substrate A method of reproducibly manufacturing circuit carriers with very fine circuit structures, more specifically with structure widths of 50 &mgr;m and less, is described in which a substrate provided with a base metal surface is provided, a layer of varnish is applied onto the substrate by an electrophoretic method, the layer of varnish is ablated in at least parts of the regions that do not correspond to the metal pattern to be formed, the base metal surface being laid bare, the bare base metal surface is etched, the layer of varnish being ablated by means of ultraviolet irradiation, more specifically with an ultraviolet laser beam.

Abstract: A SIMOX substrate having a buried oxide layer and a surface single crystal silicon layer formed therein is produced by a method which comprises implanting oxygen ions into a silicon single crystal substrate and subsequently performing a heat treatment at an elevated temperature on the substrate. The method is characterized by performing the former stage of the heat treatment at a temperature of not lower than 1150° C. and lower than the melting point of single crystal silicon in an atmosphere obtained by adding oxygen under a partial pressure of not more than 1% to an inert gas and subsequently performing at least part of the latter stage of the heat treatment by increasing the partial pressure of oxygen within a range in which no internal oxidation is suffered to occur in the buried oxide layer. It can also be prepared by performing the former stage of the high temperature heat treatment at a temperature of not lower than 1150° C.

Abstract: A method for improving the coating capability of low dielectric layer is disclosed. The method includes steps of an etching stop layer is deposited a semiconductor substrate, an adhesion promoter layer is spun-on the etching stop layer. The pre-wetting process being performed on the adhesion promoter layer to enhance the coating capability of the low-k dielectric layer, and thus improve the coating quality through the pre-wetting process of baked adhesion promoter layer before the low-k dielectric layer is applied.

Abstract: Disclosed are methods for forming a silicon oxide layer of a semiconductor device capable of insulating between fine conductive patterns without causing a process failure, and for forming a wiring having the silicon oxide layer. After forming conductive patterns on a semiconductor substrate, an anti-oxidation layer is sequentially formed on the conductive patterns and on the semiconductor substrate. The anti-oxidation layer prevents an oxidant from penetrating into the conductive patterns and the semiconductor substrate. A reflowable oxide layer is formed by coating a reflowable oxidizing material on the anti-oxidation layer while burying the conductive patterns. The silicon oxide layer is formed by thermally treating the reflowable oxide layer. Then, the silicon oxide layer filled between conductive patterns and the anti-oxidation layer exposed to the semiconductor substrate are etched so as to form a contact hole, thereby forming the wiring of the semiconductor device.

Abstract: A process for producing a semiconductor device which comprises forming a layer of an organic polymer resin on a surface of a semiconductor element, treating the formed layer by pattern working and curing, etching the element using the patterned and cured layer as a mask, exposing an electric conductive layer at open portions, treating the element with oxygen plasma at a temperature of 100° C. or higher and cleaning the electric conductive layer at the open portions.

Abstract: A pattern is transferred to a resist film on a wafer by a reduction projection exposure method using a half-tone phase-shift mask in which is formed a half-tone phase-shifter pattern including a thin-film pattern functioning as an attenuator and a resist pattern functioning as the photosensitive composition for phase adjustment. This method improves the accuracy of dimensions of the pattern transferred to the wafer.

Abstract: Hand-held tools for gripping a railway contact rail to facilitate grounding thereof are provided. A first member includes a first jaw at an end thereof, a handle at an opposite end thereof, and a first intermediate portion extending between the first jaw and the handle. A second member is pivotally attached to the first member and includes a second jaw at an end thereof, a set of ratchet teeth at an opposite end thereof, and a second intermediate portion extending between the second jaw and the set of ratchet teeth. The first and second jaws are configured to pivot relative to each other so as to grip respective opposite side portions of a railway contact rail when the handle is moved downwardly such that the second intermediate portion is in electrical contact with a top portion of a railway contact rail.

Abstract: The present invention provides a method of making an electronic parts mounting board, comprising the steps of:

Abstract: A method is provided for attaching a connector with connector tails to a printed circuit board (PCB) having contacts. The method includes steps of: supplying and supporting the PCB; applying solder paste to the PCB contacts; inserting mounting hardware through the connector holes; presenting the connector to the PCB in a position above and parallel to the PCB; lowering the connector to align the mounting hardware with PCB orifices; pressingly engaging the connector tails against the PCB contacts to make the connector tails coplanar; tightening the mounting hardware to secure the connector to the PCB; and soldering the connector tails to the PCB contacts. In one embodiment, the mounting hardware is a rivet. In another embodiment, the mounting hardware is a nut and bolt. In yet another embodiment, the mounting hardware is electrically non-conductive.

Abstract: The present invention provides an assembly for attaching a high current conductive line to a support. The assembly comprises a base that includes a first interlocking member and a hanger that includes a second interlocking member removably engaging the first interlocking member. The hanger also includes a retaining section attached to the second interlocking member, wherein the retaining section is shaped to receive and support the conductive line.

Abstract: A connector lock for securing and supporting a fully engaged connector assembly against disconnect even when subjected to vibrational forces experienced during launch into outer space. The connector lock includes a base portion and a pair of end portions extending substantially parallel to each other. Each end portion includes a pair of spaced-apart arms formed of flexible material and positioned so as to flex apart as a connector assembly is inserted between the arms. The arms snap back toward their original positions to prevent inadvertent release of the connector assembly.

Abstract: A connector assembly (2) includes and arc prevention shunt (20) in one of two mating electrical connectors (10, 30). The shunt (20) engages a terminal (34) when the connectors (10) and (20) are in a partially mated configuration. If the terminal (34) is hot, current will pass from the shunt (20) to a relay coil (62) to close contacts (64) in a Form C relay (60). When the normally open switch contacts (64) are closed a bypass circuit (52) disconnects the terminals (14, 34) in the connectors (10, 30) so arcing will not occur when the connectors (10, 30) are mated or unmated under load. When the connectors (10, 30) are in the fully mated or fully unmated, the shunt (20) is electrically isolated from the terminals (14, 34).

Abstract: The present invention relates to a contactor (1) comprising at least two spaced-apart fixed contacts (2, 3) and an at least sectionwise electrically conductive, movable contact bridge (9) having at least two contact points (8) which are associated with said fixed contacts (2, 3). The contact bridge is adapted to be moved to a switched position by a switching force (B) and to a rest position by a pretensioning force (V) which substantially counteracts the switching force (B). The pretensioning force (V) is produced by a pretensioning means (13). A particularly advantageous distribution of the pretensioning force to the two contact points and a reliable switching operation is achieved in that one contact (2) is arranged between the other contact (3) and a point where the pretensioning force (V) acts on the contact bridge (9).

Abstract: An installation apparatus and method for actuating the electrical connection of a land grid array module to a printed wiring board is provided. A backside stiffener with load posts is attached to a printed wiring board. A load plate, module, plurality of load columns, and spring plate are operably connected to the load posts. An actuation screw operably connected to the springplate is rotated imparting an actuation force to the module. The backside stiffener includes a local stiffener, wherein the local stiffener causes a deflection in the printed wiring board complementary to the deflection of the module when the actuation force is applied.

Abstract: A connector is provided, by which terminal fittings can be securely electrically connected to each other and a connector housing is provided, by which a terminal fittings in a mating connector housing can be securely electrically connected to a terminal fittings received in the connector housing. A connector having a lock security mechanism includes a female housing and male housing. The female housing includes a body part for receiving a male terminal and a tube-shaped bushing. A first rib protruding from the outer surface of the bushing is provided. The male housing includes a body part for receiving a female terminal and a tube-shaped bushing. A second rib protruding from the inner surface of the bushing is provided. When the female housing is coupled with the male housing, the first rib comes in contact with the second rib.

Abstract: A twin-Thermoelectric cooler design including two independent thermoelectric coolers sharing the same base (hot side ceramic plate). People familiar with the art understand that the number of independent TEC sharing the same base is not limited to two. Depending on application needs any number of TECs can be constructed on the same base and be controlled independently.

Abstract: A cable includes a number of coaxial wires. Each of the wires has a central conductor encompassed by a dielectric sheath, and the sheath is encompassed by a conductive shield. The wires are arranged side-by-side in a row at an end of each wire, where a termination element is connected. The termination element has opposed major faces, with an array of first contacts on a first face, and an array of second contacts on the opposed face, each of the first contact being electrically connected to a corresponding second contact. Each of the central conductors of the wire elements is connected to a corresponding one of the first contacts. An electronic device may include circuit boards at each end, with contacts arranged for compressive contact with the second contacts. The termination element may be captured between a clamp and the board, with an elastomeric spring maintaining compression, and pinned holes in the termination element and board ensuring registration of the contacts.